Chad Nelson, Brian Peck,Chetan Kumar N G

MotivationScheduling overhead has been a major limiting factor in the implementation of dynamic priority scheduling algorithms in Real Time Application.

Overhead due to:Time-tick processingRuntime priority calculationContext Switching

Solution: Build the scheduler in hardwareASIC implementation is not flexible and difficult to

modify.

Project ProposalTo build Reconfigurable Hardware Scheduler to support multiple scheduling disciplines(EDF and RM) and make it runtime reconfigurable.

Platform/ToolsXilinx Virtex-5 FXT FPGA ML507 Evaluation Platform, Xilinx ISE, Modelsim

Advantages:Minimizes processor time wasted by schedulerReduce time-tick processing overheadProvides accurate timingTask sets can be modified during runtimeSupports multiple scheduling algorithms

High Level Design

Processor TaskTable

Sleep Queue

Ready Queue

Runtime Controller

CPU Interfa

ce

Current Task

Clock

Priority Queue Cell

Task Register

Comparator

Multiplexor

Data from Left Cell

Data from Right Cell

New Data

Task Registers

Period WCET Priority Memory Address

Status

Block RAM (Indexed by Task ID)

Task Deadline Period Priority

Task ID

Status

Ready Queue and Current Task Register

Task Activation Time Task ID Status

Sleep Queue

Initialization

Task Preemption

InterconnectionCPU Interface in fabric connected to

PowerPC processor via Processor Local Bus (PLB).

PowerPC CPU Interface

plb_v46MPLB

SPLB

Interrupt

HandlerSPLB

Slave RegistersUse Slave Registers to communicate with

Runtime Controller.

CPU Interfac

e

RuntimeControlle

r

Reg0

RegN

Slave Registers

Task Switchingvoid RHS_CONT_Intr_Handler(void * baseaddr_p) { Xuint32 baseaddr; Xuint32 IpStatus; Xuint32 taskInfo; baseaddr = (Xuint32) baseaddr_p; IpStatus = RHS_CONT_mReadReg(baseaddr, RHS_CONT_INTR_IPISR_OFFSET); if (IpStatus) { taskInfo = RHS_CONT_mReadSlaveReg0(baseaddr, 0); // switch task. }}

Interrupt DelayImportant to keep delay minimal.Long interrupt handling delay would render

use of hardware scheduler pointless.

EDF SimulatorWritten in C#Used to benchmark our hardwareGather data on the performance aspects of a

software implementation of the EDF Scheduling algorithm# tasksutilization# preemptions# context switches

Simulator DataTest Tasks Calc Sched Total

% Time used by Scheduler

Preemptions

Context Switches

Utilization

1 11 455 535 990 54.04% 127 5040.89613

34

2 9 497 414 911 45.44% 86 3440.98731

23

3 9 438 141 579 24.35% 103 4100.87265

17

4 10 382 451 833 54.14% 102 4100.78779

8

5 7 371 91 462 19.70% 60 2360.71543

9

6 8 472 379 851 44.54% 82 3240.93004

74

7 7 513 133 646 20.59% 85 3360.99452

48

8 5 348 78 426 18.31% 47 1840.69076

379 5 346 269 615 43.74% 55 222 0.69879

10 13 503 579 1082 53.51% 130 5790.99083

24

11 16 492 276 768 35.94% 135 5360.99563

17

12 9 472 457 929 49.19% 93 3700.95015

81

13 12 490 478 968 49.38% 101 4000.95706

92

14 9 469 485 954 50.84% 103 4100.94529

77

15 10 486 535 1021 52.40% 116 4600.98104

02

Simulator Data# Tasks

v. % Scheduler Time

# Tasks v.

# of Preemptions

Current Project Status

What has been done?Design and Implementation of priority queuesBlock RAM module, which will be the task table.Controller and Timer Module.

In Progress:CPU interface unitSoftware to simulate context switching

Future Work

Implement Dynamic Scheduling Algorithms

Dynamic scheduling algorithms like slack stealing algorithm which has large scheduler overhead could be implemented .

Reduce processor power consumptionProcessor consumes considerable power to run the scheduler even

when there are no tasks in the system.A low power scheduling co-processor can be used to put the

processor in deep sleep mode when no active tasks are present in the system.

ReferencesP. Kuacharoen, M. Shalan, V. Mooney, “A Configurable

Hardware Scheduler for Real-Time Systems” Center for Research on Embedded Systems and Technology School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta, Georgia 30332, USA.

S. Saez, J. Vila and A. Crespo, “A hardware Scheduler for Complex Real-Time Systems,” ISIE, pp. 43-48, 1999.

S. Moon, J. Rexford and K. Shink, “Scalable hardware priority queue architectures for high-speed packet switches,” IEEE Transactions on Computer, vol. 49, no. 11, pp. 1215-1227, November 2000.

Questions/Comments/Suggestions

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