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Recent Trends in Memory Technology Reliability
IEEE EDS – SCV Seminar Based on 2017 Int’l Reliability Physics Symp. Memory Year-In-Review
August 8, 2017
Bob Gleixner
Micron Technology, Inc.
2
Industry trends in semiconductor memory technology
� NAND flash production is rapidly shifting from planar to 3-D (vertical string)
� DRAM continues to scale (planar) while looking for a path to higher performance (3-D packaging)
� Emerging memories are slowly emerging
3
Publication trends by memory type
� MRAM trending up while PCM/PRAM is down
2013-2014
2015-2016
% Change
DRAM 725 766 +5
NAND 542 551 +2
RRAM 369 399 +8
PCM+PRAM 227 208 -9
MRAM 251 323 +28
Total 2114 2247 +6
Source: IEEE Xplore keyword search
4
Agenda
� Focus on the main development directions for each technology
� Review recent device and process technology papers, specifically those that focus on reliability
– Intent is to summarize what is being studied, not provide a “top ten papers” list
� Summarize results for the main technology groups:
– NAND: planar and 3D
– DRAM: silicon and TSV/die stacking
– Emerging memory
5
NAND Overview
� Academic and industry/academic partnerships prevalent for planar NAND studies
– Focusing on cell physics
– Practical understanding is very mature, pursuing the “ultimate limit” of understanding
� 3D NAND publications are generally industrial based
– Many are marketing driven
– Some studies of failure modes
6
Time Dependent Threshold-Voltage Fluctuations in NAND Flash Memories:From Basic Physics to Impact on Array Operation
�Mechanisms of Vth evolution in planar NAND cells are well characterized
GODA ET AL, MICRON AND POLITECHNICO DI MILANO2015 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)
Usage Time Domains
Cell Distributions
Vth shift mechanisms
7
Time Dependent Threshold-Voltage Fluctuations in NAND Flash Memories:From Basic Physics to Impact on Array Operation
�While planar NAND nears its scalability limits, 3D NAND shows a path to tighter distributions
GODA ET AL, MICRON AND POLITECHNICO DI MILANO2015 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)
Tighter Vth distributions for 3D
RTN
De-trap
8
First Detection of Single-Electron Charging of theFloating Gate of NAND Flash Memory Cells
�“This letter provides the first direct experimental detection of single-electron charging of the floating gate of a mainstream Flash memory cell”
�Data collected on 16nm planar FG NAND
C. M. COMPAGNONI, ET AL., MICRON AND POLITECHNICO DI MILANOIEEE ELECTRON DEVICE LETTERS, VOL. 36, NO. 2, FEBRUARY 2015
Electrons
Programming pulses
RTN
e-
9
Cycling-Induced Charge Trapping/Detrapping inFlash Memories - Part I: Experimental Evidence
�A physical picture for the trapping/detrapping processes in FG NAND is proposed to reproduce threshold-voltage instabilities over array lifetime
D. RESNATI, ET AL., POLITECNICO DI MILANO AND MICRONIEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 63, NO. 12, DECEMBER 2016
Vth shift during bake
Vth shift experiments after pre-bake
10
Cycling-Induced Charge Trapping/Detrapping inFlash Memories - Part II: Modeling
D. RESNATI, ET AL., POLITECNICO DI MILANO AND MICRONIEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 63, NO. 12, DECEMBER 2016
�Model assumes 2-step process of structural relaxation + carrier exchange
Model applied to prior data
11
Three-Dimensional 128 Gb MLC Vertical NAND Flash Memory With 24-WL Stacked Layers and 50 MB/s High-Speed Programming
�3D NAND has become the main focus for product development, providing some relief from the planar cell scaling limitations
KI-TAE PARK ET AL., SAMSUNGIEEE JOURNAL OF SOLID-STATE CIRCUITS, 2015 AND 2016
Charge trap cell w/vertical channel
Tighter Vth w/ less cell coupling
12
In depth analysis of post-program VT instability after electrical stress in 3D SONOS memories
� Conclude that Vth instability after stressing is due to e- emitted from defects generated in the TuOx by h+ injection during erase pulses
A. SUBIRATS ET AL., IMECIEEE 8TH INTERNATIONAL MEMORY WORKSHOP (IMW), 2016
Insensitivity to temperature implies #3Early Vth loss is a function of P/E cycles
Sensitive toVwait
13
Comprehensive evaluation of early retention (fast charge loss within a few seconds)
characteristics in tube-type 3-D NAND Flash Memory
� A fast charge loss within a few seconds, which is referred to as early retention, was observed in word-line stacked 3-D NAND flash memory for the first time
BONGSIK CHOI ET AL., KOOKMIN UNIVERSITY & SK HYNIX2016 SYMPOSIUM ON VLSI TECHNOLOGY
High speed measurements
Sensitivity to program/erase level and sequence
14
DRAM
� Planar node evolution faces “standard” scaling challenges (higher fields and currents, smaller noise tolerance)
� Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM) provide an architecture path to higher performance but add packaging risks
Pawlowski, Hot Chips 23, 2011
www.AMD.com
15
Flipping Bits in Memory Without Accessing Them:An Experimental Study of DRAM Disturbance Errors
�Row-to-row disturb (aka row hammer) has become a significant reliability risk
YOONGU KIM ET AL.,, INTEL AND CARNEGIE MELLON UNIVERSITY2014 ACM/IEEE 41ST INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA)
Increasing errors w/ scaling
Errors increase with refresh interval Errors have a row-proximity pattern
16
Row-Hammer Mitigation
� Approaches range from silicon to system…
� Efficient scheme to count “hot” row access (enabling victim refresh)
– “Counter-Based Tree Structure for Row Hammering Mitigation in DRAM,” Seyedzadeh et al., IEEE COMPUTER ARCHITECTURE LETTERS, Volume PP, Issue 99, 2016
� Understand possible methods of inducing an attack and identify software solutions
– “A New Approach for Rowhammer Attacks,” Qiao et al., 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)
17
Suppression of Row Hammer Effect by Doping Profile Modification in Saddle-Fin Array Devices for Sub-30-nm DRAM Technology
�Optimized doping can reduce leakage between aggressor (hammered) and neighboring access devices
CHIA-MING YANG ET AL., CHANG GUNG UNIVERSITY AND INOTERAIEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 16, NO. 4, DECEMBER 2016
Increase P implant b/w WL devicesReduction in leakage to neighbor
Demonstrated reduction in RH fails
18
Roles of Residual Stress in Dynamic Refresh Failure of a Buried Recessed-Channel-Array Transistor (B-CAT) in DRAM
�Residual stress caused by grain growth of the metal gate can accelerate negative shift in threshold voltage
SEGEUN PARK ET AL., SAMSUNG AND SUNGKYUNKWAN UNIVERSITYIEEE ELECTRON DEVICE LETTERS, VOL. 37, NO. 7, JULY 2016
Model: Hole trap formation
Vth shift vs. residual stressTiN growth & stress vs. temperature
19
Impact of local stress in 3D stacking process on memory retention characteristics in thinned DRAM chip
�Underfill shrinkage-induced stress reduces cell retention
S. TANIKAWA ET AL., TOHOKU UNIVERSITY 2016 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM
Underfill shrinkage induces stress
Retention high near bumps
Retention vs. Si thickness & underfill
Raman shift vs. position
20
Impact of 3D Copper TSV Integration on 32SOI FEOL and BEOL Reliability
�Degraded CHC due to thinning + 3D thermal steps, other mechanisms were matched
M. G. FAROOQ ET AL., IBM2015 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM
4-chip DRAM stack over logic
% Idsat shift vs. 2D/3D+thinning
2D 3D 3D+thin
2D 2D post bake3D
% Idsat shift induced by thermal processing
21
Emerging Memory� STT MRAM
– Looking for a path to high density � small cell, low Ic, high kbT
� FERAM
– Looking for a path to high density � material w/ high signal + ease of integration
� PCM/PRAM
– Still trying to find a volume product path� MLC, high temperature capability
� RRAM
– Promising for high density, but filament variability / control is critical
� 3D Xpoint
– New technology, initial products are starting to ship
22
Data Retention Extraction Methodology forperpendicular STT-MRAM
�Bi-stable device with thermally activated switching requires new methods to measure retention / stability
L. TILLIE ET AL., CEA-LETI, SPINTEC, AND SINGULUS TECHNOLOGIES2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)
STP: Switching Time ProbabilitySFD: Switching Field DensitySCD: Switching Current DensitySPW: Switching Pulse Width
CoFeB + MGO pMTJ
Retention vs. stability
Stability vs. T
23
Technology for Reliable Spin-Torque MRAM Products
�Results from 256Mb pMTJ show reliability to 100C/10year + solder reflow conditions
J.M. SLAUGHTER ET AL., EVERSPIN AND GLOBALFOUNDRIES2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)
Write error rate ~5e-6, high stability
Robust cycling endurance, read disturb, and retention
24
4Gbit density STT-MRAM using perpendicular MTJrealized with compact cell structure
�DRAM select device + 90nm pitch for high density
S.-W. CHUNG ET AL., SK HYNIX AND TOSHIBA2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)
Raw Bit error rates ~1e-6
Chip error count after repair + ECC
25
Ferroelectric HfO2-based materials for next-generation ferroelectric memories
�Provides a potential path for scaling � good signal in thin films and “easy” integration
ZHEN FAN ET AL., NATIONAL UNIVERSITY OF SINGAPOREJOURNAL OF ADVANCED DIELECTRICS VOL. 6, NO. 2 (2016)
Comparison with perovskites
Endurance, 1T-1C device Retention and endurance, MFIS-FET
1010
26
Multilevel-Cell Phase-Change Memory:A Viable Technology
�Demonstrates a read methodology that is insensitive to resistance drift
A. ATHMANATHAN ET AL., IBMIEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, MARCH 2016
Resistance drift vs. initial R
Sensing with “eM” metric is drift tolerant
27
High Operating Temperature Reliability ofOptimized Ge-rich GST Wall PCM Devices
�Demonstrates automotive range temperature capability
J. KLUGE ET AL., CEA LETI AND STMICROELECTRONICS2016 IEEE 8TH INTERNATIONAL MEMORY WORKSHOP (IMW)
SET speed of ~500nS
High T read disturbRetention to ~100C (2.5eV)Resistance window across T
28
ALD-based Confined PCM with a Metallic Liner toward Unlimited Endurance
�Confined cell with metallic liner suppresses segregation and enables very high write endurance
W. KIM ET AL., IBM, ULVAC, AND MACRONIX2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)
Endurance to 1012
Sb-rich GST
Un-confined cell: Segregation leads to opens
Confined cell: Limited segregation
29
Reliability Characterization of a CommercialTaOX-based ReRAM
�Panasonic MN101L microcontroller with 64kB embedded ReRAM
JEAN YANG-SCHARLOTTA ET AL., JET PROPULSION LABORATORY, CALTECH, AND NASA2014 IEEE INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP (IIRW)
85C tail-bit retention capability
1T/1R architecture, byte-level access
1.1eV
BER 10-7 to 10-6 after ~1k writes
30
Challenges for High-Density 16Gb ReRAM with 27nm Technology
�Highlights importance of scaled selector on memory cell reliability
SCOTT SILLS ET AL., MICRON AND SONY2015 SYMPOSIUM ON VLSI TECHNOLOGY
LRS tails and retention limited by Icc of selector Reduced selector strength leads to HRS fails
16Gb BER’s higher due to selector variation
31
Understanding RRAM endurance, retention and window margin trade-off using experimental results and simulations
�Examined the link between atomic stability and intrinsic parameters
C. NAIL ET AL., CEA LETI, IMEP LAHC CNRS, LTM CNRS, WESTERN DIGITAL2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM)
Max energy dictates the total window + reliability
Migration barrier Ed defines the endurance vs. retention tradeoff
32
Programming Strategies to Improve Energy Efficiency and Reliability of ReRAM Memory Systems
MANQING MAO ET AL., ARIZONA STATE2015 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS)
�Beyond cell capability, array operation can significantly improve the device characteristics
Bias conditions
Bias can optimize window
Write endurance trades off with energy
33
3D Xpoint
� Announced by Micron and Intel, positioned as a high-performance NVM – fast read/write and high endurance
� Main features are a cross-bar architecture and a bulk switching mechanism
� Initial products launched by Intel in Spring of 2017
www.micron.com
34
Closing remarks
� “Evolutionary” memory technologies are going through “revolutionary” transitions
– Changes in materials and process integration require significant re-evaluation of reliability models
– Cannot blindly rely on JEDEC or other standards for stress conditions
� Emerging technology options continuing to expand in breadth and march toward production
– Reliability models (and interactions) must be developed from scratch
� Memory reliability is increasingly dependent upon system-level error management
� Maintaining cost & performance while managing reliability is becoming the critical gate to product deployment