Real-Time Solutions Using Mixed-Signal Front-End Devices with the Blackfin® Processor

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Engineer-to-Engineer Note EE-236

a Technical notes on using Analog Devices DSPs, processors and development toolsContact our technical support at [email protected] and at [email protected] visit our on-line resources http://www.analog.com/ee-notes and http://www.analog.com/processors

Real-Time Solutions Using Mixed-Signal Front-End Devices with theBlackfin Processor

Contributed by Prashant Khullar Rev 1 May 18, 2004

Copyright 2004, Analog Devices, Inc. All rights reserved. Analog Devices assumes no responsibility for customer product design or the use or application ofcustomers products or for any infringements of patents or rights of others which may result from Analog Devices assistance. All trademarks and logos are property

IntroductionCertain areas of telecommunicationsinfrastructure are evolving towards the creationof smaller, localized wireless networks. Theseso-called picocells can extend wirelessconnectivity to areas where terrestrial networksare not present. The development of this micro-infrastructure brings about the need for compactdevices that can perform some of the taskstraditionally associated with larger wireless basestations.

The Blackfin family of processors can begluelessly integrated with a mixed-signal front-end (MxFE) for these and a wide variety of otherreal-time applications. The Blackfin

architectures signal processing performance,ease of programmability, and flexible parallel port make it an ideal candidate for such roles.Additionally, MxFE devices integrate thenecessary analog front-end functionality onto asingle chip with a programmable architecture.

Hardware ArchitectureThe AD9866 MxFE is chosen for this discussion.The 12-bit data converters (A/D and D/A) on the

MxFE connect to the Blackfins parallel peripheral interface (PPI) without any externallogic. The PPI is a half-duplex 16-bit parallel

port which runs at up to half the speed of theBlackfin system clock (SCLK/2). At the

maximum SCLK frequency of 133 MHz, thistranslates to a PPI update rate of 66 MHz. TheMxFE serial interface for control registerconfiguration connects directly to the Blackfinsserial peripheral interface (SPI). Depending on

the applications bandwidth requirements, a half-duplex or full-duplex implementation can beused. The former can be accomplished using theADSP-BF531/BF532/BF533 line of processorswhich have a single PPI.

! Full-duplex applications require a dualPPI device such as the ADSP-BF561symmetric multiprocessor. Suchimplementations are not discussed inthis EE-Note.

As shown in Figure 1 , the parallel digitalinterfaces of the 12-bit ADC and 12-bit DACconnect directly to the Blackfin PPI. A fixednumber of samples is transferred directly usingDMA from the ADC to a buffer in the

processors internal memory. Signal processingmay then be performed on this block of data

before the PPI direction is reversed and the datais transferred out to the DAC.

General-purpose flag pins are used to alternatelyenable and disable the ADC and DAC in a

deterministic fashion. All data transfers aresynchronized by a single clock sourced by anoscillator running at frequencies up to 60 MHz.

of their respective holders. Information furnished by Analog Devices applications and development tools engineers is believed to be accurate and reliable, howeverno responsibility is assumed by Analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices Engineer-to-Engineer Notes.


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Real-Time Solutions Using Mixed-Signal Front-End Devices with the Blackfin Processor (EE-236) Page 2 of 5

Figure 1. Hardware Interconnection

The serial connection between the Blackfin andAD9866 is used to program the MxFEs on-

board register set. These registers control variousaspects of the devices operation including powermanagement, clocking, programmable gainamplifiers, and interpolation filters.

Software-Controlled Data Flow

To implement such a half-duplex communicationscheme, the PPI and DMA controller on theBlackfin processor need to reverse their directionof data transfer at specified intervals. This can beaccomplished in software using a block ofconfiguration code placed in an interrupt serviceroutine (ISR). In the tested implementation, ageneral-purpose timer was used to generate theinterrupts that trigger this routine at deterministicintervals. The timer period was chosenempirically such that the time betweensuccessive interrupts was adequate to ensure thatthe ongoing DMA transfer is able to completeand that the turnaround code is also able toexecute to completion.

The latency associated with the DMA/PPI turn-around code has two components. The first is thetime associated with switching context between

the main execution flow and the ISR. The delayinvolved with reconfiguring the GPIO, DMA,and PPI register sets constitutes the remainder ofthe turn-around time.

The subsequent quantitative analysis of thisdataflow uses the following abbreviations:

N: Number of Samples (Data WindowSize)

CCLK : Blackfin Core Clock Frequency

SCLK : Blackfin System Clock Frequency

DCLK : Data Clock/PPI Clock (synchronizesMxFE converters and PPI)

RX 0, RX 1 : first and second halves of the receiveddata window, respectively

TX 0, TX 1 : first and second halves of thetransmitted data window, respectively

P0, P1 : signal processing of first and seconddata window halves, respectively

The following benchmarks were obtainedempirically:

Context Switch Latency (Using EX_InterruptHandler withthe stack in L1 Data Memory) =

ISR Initialization Latency +


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a ISR Termination Latency =32 CCLK cycles

GPIO/DMA/PPI Reconfiguration Latency =25 SCLK + 73 CCLK cycles

(223 CCLK cycles at a 6:1 SCLK:CCLK ratio)

Total Turn-around Latency =25 SCLK cycles + 105 CCLK cycles

(255 CCLK cycles at a 6:1 SCLK:CCLK ratio)

To boost processing efficiency, a ping-pongscheme is implemented in software, whereby

signal processing tasks may be performed in parallel with DMA transfers. In particular, inputand output data buffers are broken into halves sothat one half may be processed while the other is

being read or written by the DMA controller.

The following data-flow diagram and executiontimeline illustrate this half-duplex ping-pongscheme.

Figure 2. Digital Dataflow

Figure 3. Execution Timeline

DMA

L1 Internal Memory Buffers

PPI

ADSP-BF533

MxFE Converters

Core Processing

DMACoreBus

(DCB) DMA

AccessBus

(DAB)

PPI_Data [11:0]

LoadData

StoreData

DCB

RX 0

RX 1

TX 0

TX 1



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a ! For applications that require larger andvariably-sized sample windows, the

above data flow can be modified easilyto place buffers in external SDRAM.

As demonstrated above, the turn-around latencyreduces the available bandwidth minimally. Themaximum throughput of this arrangement can bequantified as follows.

With CCLK = 750 MHz, SCLK = 125 MHz,DCLK = 60 MHz:

Turnaround Latency =255 CCLK cycles ! 20 DCLK cycles

Average bandwidth lost to turn-around latency =[1/(20 DCLK cycles)]*2 Bytes =(DCLK/20)*2 Bytes = 6 megabytes/second

Average RX Throughput = Average TX Throughput =[(DCLK/2) (DCLK/20)]*2 Bytes= 54 megabytes/second

Signal ProcessingThe real-time processing workload that can beaccommodated depends on the size of the datawindow. The time taken by the algorithm tocomplete must not exceed the deterministic timerequired for the parallel DMA transfer tocomplete. Appropriate selection of the windowsize is therefore essential. In general, signal

processing algorithms that execute slower than inlinear time become unmanageable as the windowsize grows large. On the other hand, algorithmsthat execute faster than in linear time may bemore efficient to implement with large windowsizes. The demonstrational example used to testthis system performed a 512-point Fast FourierTransform (FFT) followed by an inverse FFT ofthe same size on each half of the 1024-samplewindow. Both algorithms execute slower than inlinear time (O(n log n)); therefore they can beexpected to exceed the available processing timeif the data window size is increased indefinitely.

Half-Duplex SynchronizationData transfers between the AD9866 high-speedconverters and the Blackfin PPI are synchronized

using flag pins. The Blackfin processor acts asthe master device by toggling flag pinsconnected to the Transmit Enable (TXEN) andReceive Enable (RXEN) pins of the AD9866.

The active-high RXEN and TXEN signalsindicate when valid data is being read from theADC or written to the DAC by the Blackfin PPI,respectively. These signals are not transmittedover the analog medium. Therefore, in this half-duplex scheme, an external device connected tothe analog medium needs to be able to handle thealternating bursts of data transmission andreception.

One possible implementation is for the device tohave built-in circuitry to distinguish between

valid data and silence. A simple dead-bandcircuit, which enables data sampling after acertain analog voltage threshold is exceeded,would be appropriate. Additionally, the devicewould need to be programmed to receive andtransmit data bursts of a pre-specified length.

When interfacing to external devices that requireexplicit data framing, the TXEN and RXENsignals can be transmitted alongside the analogsignals.

ImplementationThe hardware components and configurationrequired to evaluate this design are outlined inthe r eadme. t xt file included in theVisualDSP++ project that accompanies thisEE-Note. A glueless 3-board interconnection isrequired. The AD9866 Evaluation Boardconnects directly to the ADSP-BF533/BF561EZ-Extender card, which interfaces to theADSP-BF533 EZ-KIT Lite Evaluation Board.

The VisualDSP++ software module thatdemonstrates the hardwares functionality iswritten entirely in embedded C. It provides a

proof-of-concept with enough flexibility andmodularity to fit a wide range of applications.



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Real-Time Solutions Using Mixed-Signal Front-End Devices with the Blackfin® Processor