Real Time Control - Interrupts

7/31/2019 Real Time Control - Interrupts

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D.Murali Krishna

Sr. Asst. Prof.,

Dept. of ECE


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Introduction: 8051 has interrupt handling mechanism for

The masking of interrupt source

Priority assignment

Use of vector address for ISR The mechanism uses the bits at the IE (Interrupt

Enable) and IP (Interrupt Pointer) registers.


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Interrupt Handling structure of an MCU


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Identification of the interrupts source.

Enabling (or) disabling of the sources. Finding (or) generating the address of ISR

Priority assignments, default assignments, increasing(or) lowering priorities as per need.


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Routine, Interrupt & ISR

Assume program or routine is executing and running atask.

The running task is at the foreground program.

The foreground program may call another routine at

some point of time using an instruction (Eg: ACALL,LCALL)

The CALL instruction executes as follows Saves the PC at the stack and re-adjusts the stack

pointer Gets the address of the called-routine

The return instruction restores the PC from the stackand re-adjusts the stack pointer


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On an interrupt, the execution of an instructions starts

for a service routine. This routine is called an Interrupt Service Routine

(ISR)


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Servicing of Interrupts in 8051:

When interrupt occurs the CPU does the follg. actions

Completes current instruction.

When EA=1, and the source which is unmasked by settingappropriate bit at IE=1, the servicing of that source willoccur as follows.

CPU pushes on to the internal stack two CPU registers PCH andPCL

Reset EA=0 momentarily and the sets it again to 1 automatically

at the ISR. CPU sets the PC bits as per the corresponding ISR_VECTADDR

After the first instruction at the ISR, servicing of any furtherinterrupts from any lower priority interrupt are the only onesdisabled until RETI executes and returns from the ISR occurs.


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A Vector address is a memory address where the CPU

changes the direction of program flow automaticallyfor the execution of the ISR.

An action on interrupt from a source can occur onlywhenever the CPU has been previously enabled by

program to respond to that interrupt


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Identification of an Interrupt Source:

When an interrupt source activates, a FLAG enableswhich is identification to the processor.

A Flag can be either at a register called

Interrupt status register (or) at the Interrupt pending register (or) may coexist with the

Control bits in the control register.

Example

TI & RI (bits of SCON) TF1 & TF0 (bits of TCON)

IE1 & IE0 (bits of TCON)


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Address of Interrupt Service Routine (ISR):

How does the CPU find (or) evaluate the ISR_ADDR? There are 3 methods

Direct Access Method

Vector Address Method Vector Address for ISR pointer method


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Direct Access Method Interrupt source itself provides the address to the CPU.

The source device puts the address through the databus.

For Eg., an external circuit, which sends an interruptmessage on INTR also send the ISR_ADDR in thesubsequent interrupt acknowledgement cycles at INTApin.


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Vector Address MethodAn interrupt source auto generates at the CPU vector

address, ISR_VECTADDR.

ISR_VECTADDR is a memory address where the ISR is(or) where it executes a call (or) jump instructions tothe actual location of the ISR


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Vector Address for ISR pointer method Interrupt source provides a vector address pointer,

ISR_VECTADDR_Pointer to the CPU.

ISR_VECTADDR_Pointer is an address from where theCPU fetches the ISR_ADDR, the address of the ISR for the

source. For internal interrupts, the ISR_VECTADDR_Pointer

automaticllay generates as per the interrupt type.

The external interrupt (Source) can also put the address

ISR_VECTADDR_Pointer through the data bus.


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Interrupt Latency and deadline:

Interrupt Latency can be defined as the interval b/w theinterrupt event and the start of the ISR.

It is defined as maximum permissible interrupt latencyplus execution interval of the ISR.

Ex: If a timer overflows at T0 and its routine initiates at T1, theninterrupt latency , Tlat= T1-T0.

If it is serviced latest by t2, interrupt deadline, Td=T2-T0.

One way to measure the real-time performance of a system is

Interrupt Latency


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Multiple sources of interrupts:

Hardware interrupts related to internal devices:

Timer overflows (8051)

Input capture interrupts (8052, 68HC11/12)

Out compare interrupts (68HC11/12) End of serial transmission and reception of a character

(8051, 68HC11/12, 80196)

Interrupt when Serial buffer is full (80196)

Interrupt on start of ADC and at the end of conversion.


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Hardware interrupts related to external devices:

They depend on the CPU.

Method of finding address example

Direct address access

INTR pin of 8086Vector address method

RST 5.5, 6.5, 7.5 pins in 8085, INT0 & INT1 of 8051

Vector address for ISR pointer method

NMI pin (8086)


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Software related interrupts:

Due to errors or instructionsInterrupt

Software instruction RST 1-7 inst. (8085)

INT type (8086)

INTO (8086)

SWI (68HC11/12)

Errors divide by zero (type 0),

illegal op code (type 6),

overflow (type 4)


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Non maskable interrupt sources:

All Interrupts of 8051 are maskableProcessor

80x86

NMI pin

68HC11/12

clock monitor failure

TRAP

external XIRQ pin


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Enabling (or) disabling of the sources

There are different maskable interrupts in 8051.

An MCU may require the follg. during the execution ofa foreground program Disable all interrupt sources to the running program

Clearing IE.7 bit, all interrupts will be disabled. IE.7 is thus also called primary level enable bit.

Enable interrupt structure responses but masks certainspecific source(s) or source group(s). For Eg., IE.6-IE.0 bits at the IE reg. do this

Setting IE.7=1, enables all interrupt event responses by theinterrupt structure of 8051 and clearing IE.4=0 masks theserial port interface interrupts.

IE.4 is called SI mask bit or secondary level enable bit


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There are certain interrupts that can be masked, so

those certain events do not respond by the interrupthandling structure.

All maskable interrupt sources can also be masked by asingle enabling/disabling bit.

Problem1: set the INT0 as negative edge triggered &INT1 as level0 activated. Enable INT0 & INT1 only andmask all remaining ones.

SETB IT0

CLR IT1

MOV IE, #85H


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Problem2:

Modify the codes to enable INT0 & INT1withouteffecting the other mask bit.

ORL IE, #85H

Problem3:

Run any program without any interruption withhighest priority.

Before the ISR program, CLR EA

At the end of procedure, SETB EA


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Polling to determine the interrupt sources &

assignment of priorities: Occurrence of event is identifiable from a bit (or) bits in

the Status register and/or in the

Interrupt pending register. Several interrupt events can occur in quick successions,

there are the follg. Possibilities.

Several interrupts occurring at the same time during the

execution of set of instructions & either all (or) a few ofthese are to be serviced in a certain order of priority

A program is under execution and an interrupt occurswhich happens to be a critical ISR, which should beexecuted on priority


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An interrupt is under servicing by a temporary

diversion to an ISR, and at that instant, anotherinterrupt occurs which should also be serviced as perprecedence assigned.

2 possibilities exist

Either the second is serviced only after the completionof the first interrupt

Either the second is to be serviced immediately, givingprecedence over the first


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Issues:

Several interrupts serviced under priority User assignable priority

Default priority

Interrupt Default priority

INT0 1TF0 2

INT1 3

TF1 4

TI/RI 5

Critical ISR


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Types of Polling Procedures:

Preemptive method:vectored priority method withdiversion to a higher priority ISR than present one

8051

Linux 2.6

Non-Preemptive method:vectored priority method

with no permissible diversion after each end of ISR

68HC11/12

Linux 2.4


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Problem:

There are 4 interrupts 1,2,3 &4 in priority order. Letinterrupt 3 be under service and interrupt 4 is pendingsince past 1ms. Now, if a higher priority interrupt 1occurs at time t having execution time 5ms. Calculate

the latency of interrupt 4.


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Preemptive method


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Non-Preemptive method


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Interrupt structure in INTEL 8051

An input 1 for 2 machine cycles at the RESET inputcauses the program to start from PC=0000H

The SFRs are all zeros

The IP, except its 7thbit, loads all bits 0s

User assigned priorities are initially set to LOW

The default SP=07H, WDCON = A5H to disable

watchdog timer 8051 provides seven sources of interrupts

If EA bit in the IE register is reset, then none of thesource group is recognized


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If EA=1, then source group is recognized and serviced.

When interrupt source is enabled for the service, The EA bit is temporarily made 0 till the first

instruction end


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Default assigned priority wise source groups

Group 1

INT0 (External) interrupt IE0 only (0003H)

Priority can be define by PX0 bit (HIGH or LOW)

If EA=1 & IE.0 bit is 1 then IE0 interrupt is identified on

Occurrence of a ve edge provided by the bit IT0 at the TCON isset

Occurrence of a level 0 if the bit, IT0 is reset.

This source is maskable through IE.7 and IE.0 bits


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Group 3 ( In selected family members)

SI device Serial Synchronous port Interface Vector address (0053H)

Priority can be define by PS1 (Ip.6) bit (HIGH or LOW)

When EA=1 & if this bit is 1 then an SI interrupt can

happen on occurrence of the first bit. The 1st bit interrupt enables a read of the address of the

slave using serial clock and data lines.

The Occurrence of this interrupt is identified by 1 at the

7th bit in SIINT register. This bit when sets does not clear automatically on start of

the interrupt service.


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Group 4

Timer 0 overflow identified by the TF0 (000Bh) Priority can be define by PT0 (Ip.1) bit (HIGH or LOW)

When EA=1 & IE.1=1, timer0 overflow TF0 bit sets 1 onoverflow event and automatically resets to 0 on start of

this interrupt source.


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Group 5

INT1 (External) interrupt IE1 only (0013H) Priority can be define by PX1 bit (HIGH or LOW)

If EA=1 & IE.2 bit is 1 then IE1 interrupt is identified on

Occurrence of a ve edge provided by the bit IT1 at the TCON is

set Occurrence of a level 0 if the bit, IT1 is reset.

This source is maskable through IE.7 and IE.2 bits


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Group 6

Timer 1 overflow identified by the TF1 (001Bh) Priority can be define by PT1 (Ip.3) bit (HIGH or LOW)

If EA=1 & IE.3=1, timer1 overflow TF1 bit sets 1 onoverflow event and automatically resets to 0 on start of

this interrupt source.


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Group 7

The SI serial port synchronous and synchronous UARTcommunication interrupts, TI & RI are in this group

When EA=1 & ES=1 the transmit data to be completed isidentified by the TI.

When interrupt is enabled, the receive data completionevent is identified by RI.

PS bit (PS.4 at the IP) defines the priority

Baud rate is programmed by T1 overflow interval or T2

overflow intervals

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Real Time Control - Interrupts