Readout Electronics for LAr TPC:(the small picture)

FLARE workshopNov 4-6,2004

Paul Rubinov

Statement of the problem

• So we have a LAr TPC:– How much signal do we collect?– How much noise do we have?

• Good news!– I don’t have to think about it:

• ICARUS already built a LAr TPCNIMA preprint

“Design, construction and tests of the ICARUS T600 detector”

Statement of the problem

• ICARUS already built a LAr TPCNIMA preprint

“Design, construction and tests of the ICARUS T600 detector”

Statement of the problem

Too simple: in fact the shape of the pulse depends on the geometry of the track relative to the wire!

Sometimes the induced plane looks bipolar, sometimes it does not!

Statement of the problem• Lets assume a “typical”

situation: 25000e signal on 500pF (ref A.Para) with a shaping time ~1us

Q:How hard is that?A:Not too hard…

• “Off the shelf” solution:MASDA-X by Tom Zimmerman

Solution of the problem• “Off the shelf” solution:MASDA-X by Tom Zimmerman

at ~1.4s, N=65e+5 e/pF=2500e noise

(but this chip optimized for <100pF!)2.5 e/pF is easy… for Tom et.al.

• e.g. VA-1ch (IDEAS) is 125e+2.6e/pF @=1.25S

• Key features: fat transistors (W/L), MUCHO current (Ids)

• e.g.: VA-1ch => 10mA preamp biasMASDA-X=> 0.8mA preamp

bias

Digression on noise

http://www.inst.bnl.gov/MicroElectronics/PDF/NSS99_Invited_slides.pdf

a1~1/gm and gm~(Cgs1/2)(Ids

1/2)/L

Cost

Cost

Cost• ASICs are an extremely powerful

tool.– If you can explain what you need,

you will get it.– A new ASIC costs $1M

(roughly, including everything)

– For 250 K ch, that does not sound so bad

• Other semi custom options also exist.

• In this case a front end ASIC probably makes sense.

Cost

Cost

• The point is the problem is not the FRONT END electronics.

• The problem is the SYSTEM.

• HV, cables, connectors, grounding, shielding, leakage currents, and on and on…