Reading Guides from Textbook (Brey)ftp.it.murdoch.edu.au/units/ICT106/Lectures/ICT106_06_05_LF.pdf• INTEL Microprocessors 8086/8088, 80186/80188, 80286, ... • Barry B. Brey, DeVry

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school of information technology

ICT 106Fundamentals of Computer Systems

Topic 5ALance Fung

Introduction to the Intel Microprocessors and its Architecture

Ref: Brey (Chapter 1 and 2)Or Irvine (Chapter 1 and 4)

ICT 106 _Week 5_06 2 school of information technology

Text Book

• INTEL Microprocessors 8086/8088, 80186/80188, 80286, 80386, 80486, Pentium, Prentium ProProcessor, Pentium II, III, 4, 7/E

• Barry B. Brey, DeVry Institute of Technology

• Publisher: Prentice HallCopyright: 2006Format: Cloth; 912 pp

• Should be under A$100 from Murdoch Bookshop


Reading Guides from Textbook (Brey)• Week 1 – Section 1-1 (Introduction)• Week 2 – Sections 1-3 and 1-4 (Numbering Systems, Data

types and Representation)• Week 3 – (C Array, Functions and Structure)• Week 4 – Section 1-2 and Chapter 2 (Microprocessor

Architecture)• Week 5 – Chapter 3 (Addressing Mode, and C pointers and

bit manipulation)• Week 6 – Chapter 4 (Data Movement Instructions and

Assembly language program development)• Week 7 – Chapter 5 and 6 (Arithmetic, Logic and Program

Control instructions)


• Week 8 – Chapter 7 (High Level Language Interface)• Week 9 – Chapter 8 (Programming the microprocessor, low

level implementation of procedure calls and Functions)• Week 10 – Chapter 11 and 12 (I/O interface and Interrupts)• Week 11 – Chapter 15 (Introduction to Bus interface)• Week 12 – (Operating System and Memory Management)• Week 13 – Revision • Appendixes

– A: Assembler, Visual C++ and DOS– B: Instruction Set– C: Flags– D Answers to selected Questions and Problems

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Recommended Reading Guide from Irvine (4th or 5th edition)• Week 1 – Section 1-1, 1-2 (Introduction)• Week 2 – Sections 1-3 (Numbering Systems, Data types

and Representation)• Week 3 – (C Array, Functions and Structure)• Week 4 – Chapter 2 (Microprocessor Architecture)• Week 5 – Section 3-1, 3-2 and 3-3 (Addressing Mode, and C

pointers and bit manipulation)• Week 6 – Sections 3-4, 3-5 and 3-6 (Assembly language

program development)• Week 7 – Chapter 4 (Data Movement, Arithmetic, Logic and

Program Control instructions)


• Week 8 – Chapter 12 (High Level Language Interface)• Week 9 – Chapter 5 and 8 (Programming the microprocessor,

low level implementation of procedure calls and Functions)• Week 10 – Chapter 12 and 13 (I/O interface and Interrupts)• Week 11 – Chapter 14 and 15 (Disk Fundamentals and BIOS

Programming)• Week 12 – (Operating System and Memory Management)• Week 13 – Revision • Appendixes

– A: MASM Reference– B: Instruction Set– C: BIOS and MS-DOS Interrupts– D Answers to Review Questions


Comments on Text Book (Brey)• 1st edition of Brey’s book was published in 1987. The 7th

edition was published in 2006.• It is a popular text for UG units in Intel Microprocessor

architecture.• While ICT106 is not oriented towards hardware or

architecture, the text covers over 50% of the syllabus of the unit.

• In particular, it gives very comprehensive introduction to the Intel Microprocessor family.

• It is beneficial to understand the limitations and specifications from the hardware perspective.

• The text also serves as a good reference on the hardware and architecture aspects.


Comments on Text Book (Irvine)

• 5th edition in print. Popular for UG courses in Assembly language programming, Fundamentals of computer systems or architecture. Text has been published for 15 years.

• Based on Intel or AMD processors, MASM and running in Windows platform.

• Goals of book are designed to broaden the student’s interest and knowledge in topics relating to assembly language:

– Intel processor architecture and programming– Real and protected mode programming– Assembly language program structure– Programming methodology– Computer hardware manipulation– Interaction between assembly language program, OS and other application

programs

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Overview of Intel Microprocessors

• 4004 the first microprocessor (4-bit) 16K RAM

• 8008 (8-bit)• 8080 (8-bit) 64K RAM, 2Mhz clock• 8086 (16-bit) 1M RAM, 5MHz clock• 80286 (16-bit) 16M RAM, 16MHz clock


32 bit Microprocessors

• 80386, 4G RAM, 33 MHz clock• 80486, 4G RAM, 66 MHz clock• Pentium, 4G RAM, 66 MHz clock• Pentium Pro, 64G RAM, 133 MHz clock• Pentium II, 64G RAM, 233 MHz clock• Pentium III, 64G RAM, 500 MHz clock• Pentium 4, 64G RAM, 1.5 GHz clock


The P architecture (the Core Versions)

• P1 – 8086/8088 class • P2 – 80286 class • P3 – 80386 class • P4 – 80486 class • P5 – Pentium class• P6 – Pentium Pro/Pentium II, Pentium III,

and Pentium 4 class


Memory Organization (revision)

• Memory is organized in byte-sized (wide) chunks of data• Memory is numbered in bytes• Memory is number in hexadecimal addresses or locations• Modern memory is 64-bits wide containing 8 bytes per

memory physical location (note data bus width in Pentium Pro and above)

• However, Main memory in DRAM is SLOW! (40 ns per random access)

• Buffering and double clock edge transfers can speed memory access times to about 25 MHz

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Cache Memory

• A temporary high speed memory that buffers the slower DRAM from the higher speed microprocessor.

• Usages in bursts of 4 memory-sized chunks of data (that is, 4, 64-bit numbers)

• Level 1 (small cache for local high-speed storage)

• Level 2 (larger cache for local high-speed storage)

• Level 3 (large cache on Pentium 4 chip)

Microprocessor-based Computer (Fig 1.6, Brey)

Conceptual views of 486 and Pentium processors (Fig 1.5, Brey) Memory Map of PC (Fig 1.7, Brey)

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Windows Memory Map (Fig 1.10, Brey)


Memory for DOS Vs Windows

• 1M memory system for DOS• 4G memory system for Windows• DOS is a 16-bit system• Windows is a 32-bit system• DOS TPA is 640K bytes• Windows TPA is 2G bytes (or with a

modification to the registry, 3G bytes)

Computer Structure (Fig 1.12, Brey)


What are buses?

• Address Bus – selects a location in the memory or a specific I/O device

• Data Bus – transfers data between the microprocessor and the memory or I/O

• Control Bus – selects I/O or memory and causes a read or a write

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Memory Organization (size of data access)

• 8086/8088 – 8- or 16-bits in width• 80286 – 16-bits in width• 80386/80486 – 32-bits in width• Pentium/Pentium 4 – 64-bits in width


Another look at the 80x86 CPU RegistersRegister 8-bit name 16-bit 32-bitAccumulator AH AL AX EAXBase index BH BL BX EBXCounter CH CL CX ECXData DH DL DX EDXStack pointer SP ESPBase pointer BP EBPSource index SI ESIDestination index DI EDIInstruction pointer IP EIPFlags FL EFL

Programming Model of 8086 to Pentium 4 (Fig 2.1, Brey)

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Segments• All segment registers are 16 bits:

Code segment CSData segment DSStack segment SSExtra segment ESF Segment FSG Segment GS

• The above 80x86 registers can generally be categorised as follows:


80x86 CPU Registers

• General-purpose Registers– These are: AX, BX, CX, DX– Also called data registers – used for arithmetic and data

movement– AX: the accumulator register – is favoured by the CPU for

arithmetic operations– BX: the base register – can hold the address of a function or

variable. Three other registers with this ability are SI, DI, and BP. BX can also be used foe arithmetic and data movement


• CX: the counter register – acts as a counter for loop instructions. These instructions automatically repeat and decrement CX.

• DX: the data register – has a special role in multiply and divide operations. Eg, when multiplying, DX holds the high 16 bits of the product


Segment Registers• CPU contains four segment registers

which are used as base addresses for program instructions, data, and the stack

• Segment registers address a section of memory in a program. A segment is either 64K in length (real mode) or up to 4G in length (protected mode).

• All code (programs) reside in the code segment.

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• CS: the code segment register – holds the base address of all executable instructions in a program

• DS: the data segment register – is the default base address for variables. The CPU calculates their addresses using the segment value in DS

• SS: the stack segment register – contains the base address of the stack

• ES: the extra segment register – is an additional base address for variables


Index Registers• Index registers contain the offsets of data and

instructions• The term offset refers to the distance of a

variable or instruction from its base segment• Index registers speed up processing of strings,

arrays and other data structures containing multiple elements

• BP: the base pointer register – contains an offset from the SS register (as does the SP). The BP register is often used by a function/procedure to locate variables that were passed on the stack by a calling function


• SP: the stack pointer register – contains the offset of the top of the stack. The SP and SS registers combine to form the complete address of the top of the stack

• SI: the source index register – takes its name from the string movement instructions, in which the source string is pointed to by the SI register

• DI: destination index register – acts as the destination for string movement instructions


Status and control

• IP: instruction pointer register – always contains the offset of the next instruction to be executed within the current code segment. The IP and CS (code segment) registers combine to form the complete address of the next instruction

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• Flags: The flags register is a special register with individual bit positions assigned to show the status of the CPU or the results of arithmetic operationsEach relevant bit position is given a name; other positions are undefined. EG, the 8086/8088 flags register has the following bit positions defined:


EFLAG and FLAG Registers (Fig 2.2, Brey)


Two types of flags• Status flags: O = overflow

S = SignZ = ZeroA = Auxiliary CarryP = ParityC = Carry

Control Flags: D = directionI = InterruptT = Trap


New Flag Bits

• IOPL – I/O privilege level for Windows • NT – nested task• RF – resume flag• VM – virtual mode• AC – alignment check• VIF – virtual interrupt• VIP – virtual interrupt pending• ID = CPUID instruction available

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• Note: You don’t have to memorise each flag position!! Fortunately there are special instructions designed to test and manipulate the flags. A flag (or bit) is set when it equals 1; it is clear (or reset) when it equals 0. The CPU sets flags by turning on individual bits in the Flags register.

Do I need to remember the position of the flags?


Real Mode Memory Addressing

• Real mode memory is the first 1M of the memory system.

• All real mode addresses are a combination of a segment address plus an offset address.

• The segment address (16-bits) is appended with a 0H or 00002 to form a 20-bit address. (or multiplied by 10H)

• The effective address is this 20-bit segment address plus a 16-bit offset address.

Real mode Addressing (Fig 2-3, Brey) Arrangement of segments in an Application program (Fig 2-5, Brey)

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Defaults• Default 16-bit addresses are programs in CS, stack

data in SS, and most other data in a program in DS.• Default 32-bit addresses are programs in CS, stack

data in SS and most other data in DS.• What’s the difference? 16-bit addresses use offset

addresses in BX, SI, DI, BP, or an offset numeric value. 32-bit addresses use offset addresses in EAX, EBX, ECX, EDX, EBP, EDI, ESI or a numeric value.

• Programs resides in segment CS addressed by IP/EIP

• Stack data resides segment SS addressed by SP/ESP


Effective Address Calculations

• EA = segment x 10H plus offset(a) 10023 = 10000 + 0023(b) ABC34 = AAF00 + 0134(c) 21FF0 = 12000 + FFF0

Example (a) contained 1000 in the segment register, example (b) contained a AAF0 in the segment register, and example (c) contained a 1200 in the segment register.


Relocation

• Segment and offset addressing allows for easy and efficient relocation of code and data.

• To relocate code or data only the segment number needs to be changed. For example, if an instruction appears at offset address 0002 the segment address does not matter because if it changes so does the effective address of the instruction.


Protected Mode

• The Windows operating system domain.• 4G of memory with 2G for the system and

2 G for the application• Protected mode still uses segment and

offset addresses, but the offset address is 32-bits

• Protection is provided by restricting access through priority levels and access rights

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Descriptors describe memory

• A descriptor is selected by the number placed in the segment register.

• The descriptor describes the base address (starting address) and limit (offset to the ending address) of a segment.

• The descriptor also defines the privilege level and access rights to a memory segment.

Descriptor Formats (Fig 2.6, Brey)


• The base address is a 32-bit address (Pentium class) that addresses the start of a memory segment.

• The limit is a 20-bit number added to the base address to address the last address of a segment.

• The limit has a modifier bit called Granularity (G) that select a multiplier of 4K for the limit (4K is 12-bits) (20-bits +12-bits is 32-bits)


• base = 23000000H and a limit of 012FFH

G = 0Segment start = 23000000HSegment end = 230012FFH

G = 1 (limit = 012FFFFFH)Segment start = 23000000HSegment end = 242FFFFFH

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Segment RegisterUsing DS to access memory (Fig 2.9, Brey)

Program Invisible Registers


Paging

• The paging mechanism translates a logic address (address generated by the program) into a physical address (address that accesses a memory location).

• It does this by sectioning the address into three parts: (1) directory, (2) page table, and (3) memory offset.

• The directory and page table fields are each 10-bits wide and the memory offset is 12-bits.

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Control Registers Linear Page Address (Fig 2.12, Brey)

Paging Mechanism (Fig 2-13, Brey)


Assembly and Machine Language

• An example of some machine language is shown below. This machine code is what the CPU would accept as valid code to add three numbers:

1011100000000111000000001000101111011000101110000001000000000000000000111100001100000101

• This is the language (mother tongue) of the CPU !!

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• The same program is shown below in hexadecimal notation:

B807008BD8B8100003C305


• The above hex program could be entered using the DOS utility program DEBUG as follows:

Select Start|Programs|MS-DOS Prompt When MS-DOS prompt appears, type Debug and press Enter. To see some of the functions provided by DEBUG, type a ‘?’ at

DEBUG’s ‘-‘ prompt. (Further features of DEBUG will be covered in the next topic).

Type the following code • C:\WINDOWS>DEBUG• -E 100 B8 07 00 8B D8 B8 10 00 03 C3 05 15 00 A3 16 01

B4 4C CD 21


• This is actually machine code entered in hex. Each hex digit represents 4 binary digits – the zeros and ones that the machine understands. To quit debug, type q

• The above code is a little easier to read, but the function of the program is still not clear.


• Once again, the same code; this time in assembly language.MOV AX,7MOV BX,AXMOV AX,10ADD AX,BXADD AX,15MOV [0116],AXMOV AH,4CINT 21

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• The function of the program now becomes much clearer by checking the code. If there is any doubt about the program’s function it is easy to look across to the comments on the right to clear things up.

• The above examples show the correspondence between machine language and assembly language.

• An assembly language instruction is a symbolic representation of a single machine instruction.


• It consists of a mnemonic (a short alphabetic code, eg, MOV) followed by a list of operands.

• It is important to note here that each assembler instruction corresponds directly to one machine level instruction. A high level language may have as many as ten machine instructions per one high level language instruction.


• To check if the above is really the program, use DEBUG to unassemble the hex code entered previously using the E command and compare with the above commented assembly language statements:

u 100To exit Debug, type q


Example of entering and disassembly of code using DebugC:\WINDOWS>DEBUG-E 100 B8 07 00 8B D8 B8 10 00 03 C3 05 15 00 A3 16 01 B4 4C

CD 21-U 100, 1161486:0100 B80700 MOV AX,00071486:0103 8BD8 MOV BX,AX1486:0105 B81000 MOV AX,00101486:0108 03C3 ADD AX,BX1486:010A 051500 ADD AX,00151486:010D A31601 MOV [0116],AX1486:0110 B44C MOV AH,4C1486:0112 CD21 INT 211486:0114 C3 RET1486:0115 2E CS:1486:0116 0000 ADD [BX+SI],AL

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• (Note that each line of display produced by Debug’s Unassemble command consists of 3 parts:

1. on the left: hex address of the leftmost displayed byte in segment:offset format

2. in the middle: hex representation of the displayed area

3. on the right: ASCII representation of bytes that contain displayed characters.)


R – show Registers

-RAX=0000 BX=0000 CX=0000 DX=0000

SP=FFEE BP=0000 SI=0000 DI=0000DS=1486 ES=1486 SS=1486 CS=1486

IP=0100 NV UP EI PL NZ NA PO NC1486:0100 B80700 MOV AX,0007


T- Trace command-TAX=0007 BX=0000 CX=0000 DX=0000

SP=FFEE BP=0000 SI=0000 DI=0000DS=1486 ES=1486 SS=1486 CS=1486 IP=0103

NV UP EI PL NZ NA PO NC1486:0103 8BD8 MOV BX,AX-TAX=0007 BX=0007 CX=0000 DX=0000


NV UP EI PL NZ NA PO NC1486:0105 B81000 MOV AX,0010


-TAX=0010 BX=0007 CX=0000 DX=0000


NV UP EI PL NZ NA PO NC1486:0108 03C3 ADD AX,BX-TAX=0017 BX=0007 CX=0000 DX=0000

SP=FFEE BP=0000 SI=0000 DI=0000DS=1486 ES=1486 SS=1486 CS=1486 IP=010A

NV UP EI PL NZ NA PE NC1486:010A 051500 ADD AX,0015

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-TAX=002C BX=0007 CX=0000 DX=0000 SP=FFEE BP=0000

SI=0000 DI=0000DS=1486 ES=1486 SS=1486 CS=1486 IP=010D NV UP EI

PL NZ NA PO NC1486:010D A31601 MOV [0116],AX

DS:0116=0000-TAX=002C BX=0007 CX=0000 DX=0000 SP=FFEE BP=0000

SI=0000 DI=0000DS=1486 ES=1486 SS=1486 CS=1486 IP=0110 NV UP EI

PL NZ NA PO NC1486:0110 B44C MOV AH,4C


U – Unassemble command-U 100, 1161486:0100 B80700 MOV AX,00071486:0103 8BD8 MOV BX,AX1486:0105 B81000 MOV AX,00101486:0108 03C3 ADD AX,BX1486:010A 051500 ADD AX,00151486:010D A31601 MOV [0116],AX1486:0110 B44C MOV AH,4C1486:0112 CD21 INT 211486:0114 C3 RET1486:0115 2E CS:1486:0116 2C00 SUB AL,00


-TAX=4C2C BX=0007 CX=0000 DX=0000


NV UP EI PL NZ NA PO NC1486:0112 CD21 INT 21-TAX=4C2C BX=0007 CX=0000 DX=0000

SP=FFE8 BP=0000 SI=0000 DI=0000DS=1486 ES=1486 SS=1486 CS=FDB4

IP=1FD7 NV UP DI PL NZ NA PO NCFDB4:1FD7 63 DB 63


Little endian• In 80x86 computers, the numbers are

stored in memory locations using the little-endian method.

• i.e., the individual bytes forming the binary number are reversed when stored in memory, eg, examine the first instruction in the above program example, MOV 0007h to AX:

1486:0100 B80700 MOV AX,0007

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• The bytes containing 07 and the 00 (of value 0007) are reversed when stored in memory locations:

B8 010007 010100 0102


• In the little endian method, the high byte is stored in the high address and the low byte is stored in the low address (i.e., “the byte with the lower address contains the less significant part of the number”)

• In the hex number 0007h, 07 is the low byte (less significant byte) and is thus stored in the byte with the lower address (0101), the 00 is the high byte (more significant byte) and is stored in the byte with the higher address.


• When numbers are loaded from memory back into registers, the bytes are reversed to their original form.

• Similarly, the hex number 1234 will be stored in memory bytes as follows:

3412

• The same number when brought into a 16-bit register will be stored as

12 34


• And the hex number 12345678 will be stored in memory bytes as follows:

78563412

• The same number when brought into a 32-bit register will be stored as

12 34 56 78

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• In the big endian method, the high byte is stored in the low address and vice versa. Motorola 68000 processors which are used in the Macintosh computers use the big endian method.

• The terms little endian and big endian originated from a Gulliver’s Travels story about how an egg should be opened – from the little end or the big end.

• It may seem as trivial whether to break the egg from the little end or the big end, but converting software from one architecture to another is not !!


Format of Machine instructions:• Instructions are represented as binary numbers• Every instruction includes a code (called

opcode) that specifies the operation it performs.• The rest of the instruction specifies operands: the

number of operands, the locations of operands, and possibly the data types of operands.

• Methods used to combine the various pieces of information in an instruction are quite complicated and only the general forms will be looked at here.


• Single Operand Instructions:Opcode dd

• Double Operand Instructions:Opcode dd ss

• ‘opcode’ specifies the operation to be performed

• ‘ss’ specifies the location of the source operand

• ‘dd’ specifies the location of the destination operand


• By convention, the first operand is the destination operand and the second operand is the source operand.

• An operand can be a register, a variable, a memory location, or an immediate value, eg,

15 (immediate operand)num (variable or memory operand)AX (register operand)[0400] (memory location)

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Improved Instruction Execution Cycle

• Starting with 80386 CPUs, an improved instruction execution cycle was introduced which incorporated parallel stages in the execution cycle. These stages and the parts of the CPU that carry them are:


• Bus Interface Unit (BIU): accesses memory and provides I/O

• Code Prefetch Unit: receives instructions from BIU and appends them to the instruction prefetch queue

• Instruction Decode Unit: Decodes machine instructions from the prefetchqueue and converts them into microcode


• Execution Unit: executes the microcode instructions produced above

• Segment Unit: translates logical addresses to linear addresses and performs protection checks

• Paging Unit: translates linear addresses into physical addresses, performs page protection checks, and keeps a list of recently accessed pages.

Documents

Reading Guides from Textbook (Brey)ftp.it.murdoch.edu.au/units/ICT106/Lectures/ICT106_06_05_LF.pdf• INTEL Microprocessors 8086/8088, 80186/80188, 80286, ... • Barry B. Brey, DeVry