R E S U M E Ravi Teja Reddy rraviteja21@gmail.com | +1 (352) 283 9598 | linkedin.com/in/reddyraviteja

O B J E C T I V E

Actively seeking full time opportunities in Digital VLSI, FPGA, ASIC design, verification and validation.

E D U C A T I O N

University of Florida, Gainesville, Florida GPA: 3.45

Major : Master of Science in Electrical and Computer Engineering August 2015 - May 2017

Courses: Computer Architecture, Parallel Computer Architecture, Reconfigurable Computing, Analog IC Design, VLSI Design and Circuits, Mixed Signal IC Test, Principles of Computer System Design, Advance Systems Programming (Linux kernels & drivers).

SASTRA University, Tamil Nadu, India. CGPA: 8.38/10 Major : Bachelor of Technology in Electronics and Communication Engineering July 2009 - April 2013

S K I L L S

Languages: C, Verilog, Vhdl, Python, Parallel Programming (MPI, OpenMP, CUDA), Assembly Language Programming. Tools : Cadence virtuoso, Xilinx Vivado, Modelsim, Quartus Prime, MATLAB, LabVIEW, Canalyzer, NI Test stand, Vehicle Spy, Code Composer Studio, Modbus view. Version Control : Clearcase, SDOM, Git. | OS : Windows, Linux.| Soft Skills : Quick learner, team player, problem solving.

P R O F E S S I O N A L E X P E R I E N C E

Software Engineer at Robert Bosch Engineering and Business Solutions, Bangalore, India Jan-2014 - June 2015 Requirement Analysis, Design, Implementation and Testing the software for FIAT Light Duty trucks. Responsible of the implementation of Boost Recuperation System (BRS). Aim was to develop a fuel efficient system which provides additional torque to the system. The momentum loss during the vehicle deceleration is

converted to electrical energy and utilized to boost the engine during acceleration.

Summer Intern at Bloom Energy India Private Limited, Bangalore, India Dec-2012 - April 2013

Designed & developed a CAN to Modbus/RS485 interface that acts a gateway between off the shelf components and the system. The software acts as a bridge between high speed CAN frames generated by the system and the low speed off the shelf component that uses

Modbus protocol. Incorporated fault tolerance to handle the communication failures of CAN and Modbus networks.

H O B B Y P R O J E C T S

Gaussian Noise Generator using Box-Muller method [2016 – Verilog, Matlab, Xilinx Vivado, Modelsim]: Designed a pseudo white noise generator with a throughput of 2 signals per clock cycle. Implemented logarithm, square root and cosine functions

using piecewise polynomials. Verification of the output is performed for 10,000 samples using RTL test bench by comparing the bit quantized MATLAB output and the RTL

generated output.

Synchronous DRAM Controller [2016 – Verilog, Xilinx Vivado, Modelsim]: Controller takes the input from the cache and provides control signals to the memory module while satisfying the timing restrictions. Implemented – 2 stage pipeline & Cyclic Redundancy Check (CRC) to improve the performance and check for data corruption.

Cache Controller [2016 – Verilog, Xilinx Vivado, Modelsim]: Designed and implemented 2 way set associative virtually indexed physical tagged cache. Implemented Translation look aside buffer(TLB) for address look up and least recently used as replacement policy. The cache controller provides control signals based on TLB hit/miss. A latency of 1 clock cycle for reads and 2 clock cycles for a writes is achieved.

Serial Peripheral Interface [2016 – Verilog, Xilinx Vivado, Modelsim]: Designed SPI transmitter & receiver with configurable baud rate & number of slaves. Followed industry standard timing specifications.

G R A D U A T E P R O J E C T S

Parallelization of Lane and Obstacle detection on Nvidia Tegra X1 [2016 – CUDA, OpenCV]: Implemented Lane and obstacle detection on NVidia Tegra X1 and compared the speed up and granularity. Canny edge detection, Hough lines transform and morphological closing algorithms are parallelized.

8x2 SRAM memory block [2016 – Cadence Spectre, virtuoso]: Design, simulation and lay out of a very optimized 8x2 SRAM memory block on cadence using SCMOS 250nm process technology. Analyzed the cell stability, noise margins, timing, read write access times & power. Calculated bit line, word line and diffusion capacitances.

Power Enhancements in Cache [2015 – C, Simple scalar, Linux]: Implemented filter cache and trace cache architecture to reduce fetch stage efficiency and total energy consumption using Simple scalar tool. Qualitative analysis of these implementations are done for various configurations like associativity, size and block size.

FUSE file system [2015 – Python, Linux]: Implemented a hierarchical remote storage file system using FUSE, XMLRPC & Quoram approach with inbuilt fault tolerance. Enhanced the functionality to provide persistent using MongoDB and caching using MemCached.

Implementation of Linux Device Driver [2016 – C, Linux]: Multi-threaded programming using Pthreads. Tested for race conditions and deadlocks in character device drivers. Implemented character device driver and debugged the USB keyboard device drivers.

E X T R A C U R R I C U L A R A C T I V I TI E S

A team member of Gator Cricket Club, affiliated to the University of Florida.