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6/12/02 IBM RESEARCH Page [1] Area Array Cobra Probe Card With 5 GHz. Bandwidth Raphael Robertazzi IBM Research 6/12/02

Raphael Robertazzi IBM Research · 2017-03-26 · 6/12/02 IBM RESEARCH Page [2] Outline • Motivation: Test High Speed Area Array ICs In The Development Stage, At Wafer Level. –

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Page 1: Raphael Robertazzi IBM Research · 2017-03-26 · 6/12/02 IBM RESEARCH Page [2] Outline • Motivation: Test High Speed Area Array ICs In The Development Stage, At Wafer Level. –

6/12/02 IBM RESEARCH Page [1]

Area Array Cobra Probe Card With 5 GHz. Bandwidth

Raphael RobertazziIBM Research

6/12/02

Page 2: Raphael Robertazzi IBM Research · 2017-03-26 · 6/12/02 IBM RESEARCH Page [2] Outline • Motivation: Test High Speed Area Array ICs In The Development Stage, At Wafer Level. –

6/12/02 IBM RESEARCH Page [2]

Outline• Motivation: Test High Speed Area Array ICs In The

Development Stage, At Wafer Level.– Improve The Bandwidth Of Cobra Probe Cards

For At Speed (10Gb/s) Test.– Performance Equal To Or Better Than Membrane

Probes, Extension To Higher Frequencies.• New Hand Wired Space Transformer

Concept / Implementation.• Experimental Results.

– Rise Time / Bandwidth Measurements.– 10 Gb/s Serializer/Deserializer Wafer Level BERT

Test.• Conclusions.

Page 3: Raphael Robertazzi IBM Research · 2017-03-26 · 6/12/02 IBM RESEARCH Page [2] Outline • Motivation: Test High Speed Area Array ICs In The Development Stage, At Wafer Level. –

6/12/02 IBM RESEARCH Page [3]

Motivation

• Wafer Level, Developmental Testing Of High Pin Count Communications ICs.– Connection To C4 Arrays (Cobra Probe).– Large Numbers (~100) Of Medium Speed (0.5-1

Gb/S) Data Lines.– Microwave (10 Gb/S) Data Rates On Selected

Lines.– Complex, Multiple Power Domains.– Path To 40 Gb/s Test.

Page 4: Raphael Robertazzi IBM Research · 2017-03-26 · 6/12/02 IBM RESEARCH Page [2] Outline • Motivation: Test High Speed Area Array ICs In The Development Stage, At Wafer Level. –

6/12/02 IBM RESEARCH Page [4]

Conventional Cobra Probe Card

Substrate

Space XFMCobra Head

Pogo PinPad

Low SpeedLine

Page 5: Raphael Robertazzi IBM Research · 2017-03-26 · 6/12/02 IBM RESEARCH Page [2] Outline • Motivation: Test High Speed Area Array ICs In The Development Stage, At Wafer Level. –

6/12/02 IBM RESEARCH Page [5]

High Performance Cobra Probe Card

Substrate

50 Ohm Micro Coax

ATE Data Cable

Signal/Ground Twisted Pair

Space XFMCobra Head

Pogo PinPad

Transition Near Space XFM

Medium Speed Line High Speed Line

Low SpeedLine

Page 6: Raphael Robertazzi IBM Research · 2017-03-26 · 6/12/02 IBM RESEARCH Page [2] Outline • Motivation: Test High Speed Area Array ICs In The Development Stage, At Wafer Level. –

6/12/02 IBM RESEARCH Page [6]

Probe Card Photo

Page 7: Raphael Robertazzi IBM Research · 2017-03-26 · 6/12/02 IBM RESEARCH Page [2] Outline • Motivation: Test High Speed Area Array ICs In The Development Stage, At Wafer Level. –

6/12/02 IBM RESEARCH Page [7]

Space Transformer

C4 Image

Micro-Coax100 µm

Page 8: Raphael Robertazzi IBM Research · 2017-03-26 · 6/12/02 IBM RESEARCH Page [2] Outline • Motivation: Test High Speed Area Array ICs In The Development Stage, At Wafer Level. –

6/12/02 IBM RESEARCH Page [8]

Probe Card On HP83K Test System

High Speed Micro-Coax

Medium Speed Twisted Pair

Page 9: Raphael Robertazzi IBM Research · 2017-03-26 · 6/12/02 IBM RESEARCH Page [2] Outline • Motivation: Test High Speed Area Array ICs In The Development Stage, At Wafer Level. –

6/12/02 IBM RESEARCH Page [9]

Probe Card Features

• Space Transformer Manufacturable In 4-6 Weeks.• Addition Of Medium Speed Differential Lines Capable

Of 3-4 X Bandwidth Of Standard Space Transformer Lines (92 Ports).

• Addition of High Speed Lines Capable Of 20 XBandwidth of Standard Space Transformer (4 Ports).

• Other Improvements Relevant to Microprocessor Test And Decreased Probe Card Manufacturing Time.

Page 10: Raphael Robertazzi IBM Research · 2017-03-26 · 6/12/02 IBM RESEARCH Page [2] Outline • Motivation: Test High Speed Area Array ICs In The Development Stage, At Wafer Level. –

6/12/02 IBM RESEARCH Page [10]

TDT Characterization

HP54120B

Cobra Probe

500 Ohm Picoprobe

Page 11: Raphael Robertazzi IBM Research · 2017-03-26 · 6/12/02 IBM RESEARCH Page [2] Outline • Motivation: Test High Speed Area Array ICs In The Development Stage, At Wafer Level. –

6/12/02 IBM RESEARCH Page [11]

TDT For Medium And Low Speed Lines

Page 12: Raphael Robertazzi IBM Research · 2017-03-26 · 6/12/02 IBM RESEARCH Page [2] Outline • Motivation: Test High Speed Area Array ICs In The Development Stage, At Wafer Level. –

6/12/02 IBM RESEARCH Page [12]

Low and Med Speed Line Rise Time Comparison

2160980Low530355Med

τ10/90

(ps)

τ20/80

(ps)

Page 13: Raphael Robertazzi IBM Research · 2017-03-26 · 6/12/02 IBM RESEARCH Page [2] Outline • Motivation: Test High Speed Area Array ICs In The Development Stage, At Wafer Level. –

6/12/02 IBM RESEARCH Page [13]

TDT For High Speed Lines

Page 14: Raphael Robertazzi IBM Research · 2017-03-26 · 6/12/02 IBM RESEARCH Page [2] Outline • Motivation: Test High Speed Area Array ICs In The Development Stage, At Wafer Level. –

6/12/02 IBM RESEARCH Page [14]

High Speed Line Rise Time

6440

τ10/90

(ps)

τ20/80

(ps)

Page 15: Raphael Robertazzi IBM Research · 2017-03-26 · 6/12/02 IBM RESEARCH Page [2] Outline • Motivation: Test High Speed Area Array ICs In The Development Stage, At Wafer Level. –

6/12/02 IBM RESEARCH Page [15]

SerDes Output Experiment

HP54120B

Cobra Probe

SerDes ICτr < 20ps

Page 16: Raphael Robertazzi IBM Research · 2017-03-26 · 6/12/02 IBM RESEARCH Page [2] Outline • Motivation: Test High Speed Area Array ICs In The Development Stage, At Wafer Level. –

6/12/02 IBM RESEARCH Page [16]

SerDes Output Data

Page 17: Raphael Robertazzi IBM Research · 2017-03-26 · 6/12/02 IBM RESEARCH Page [2] Outline • Motivation: Test High Speed Area Array ICs In The Development Stage, At Wafer Level. –

6/12/02 IBM RESEARCH Page [17]

SerDes BERT Experiment

Page 18: Raphael Robertazzi IBM Research · 2017-03-26 · 6/12/02 IBM RESEARCH Page [2] Outline • Motivation: Test High Speed Area Array ICs In The Development Stage, At Wafer Level. –

6/12/02 IBM RESEARCH Page [18]

10 Gb/s Eye Diagram

Page 19: Raphael Robertazzi IBM Research · 2017-03-26 · 6/12/02 IBM RESEARCH Page [2] Outline • Motivation: Test High Speed Area Array ICs In The Development Stage, At Wafer Level. –

6/12/02 IBM RESEARCH Page [19]

10 Gb/s BERT Results At Wafer Level

Error Rate* =1.3 x 10-8231 –1

Error Free Over 30 Min. Experiment

27 –1 -> 223 –1

CommentPattern

* Repairing Rx Ground Should Allow Long Pattern To Run Error Free

Page 20: Raphael Robertazzi IBM Research · 2017-03-26 · 6/12/02 IBM RESEARCH Page [2] Outline • Motivation: Test High Speed Area Array ICs In The Development Stage, At Wafer Level. –

6/12/02 IBM RESEARCH Page [20]

Extending Bandwidth

• Bandwidth Of Current Design Limited By Cobra Head.– Rise Time Of High Speed Lines

Determined By L/R Time Of Head.

• Paths to Higher Frequencies:– Redesign Head For 50 Ohm Path From

Coax To Chip.– Reduce Distance Between Coax And Chip.

Page 21: Raphael Robertazzi IBM Research · 2017-03-26 · 6/12/02 IBM RESEARCH Page [2] Outline • Motivation: Test High Speed Area Array ICs In The Development Stage, At Wafer Level. –

6/12/02 IBM RESEARCH Page [21]

TFI Contactor Reduces L/R Time

Substrate

Space XFMTFI Contactor

Detail

100 µm

Lp = 20 pH, Lp/R = 0.4 ps

Page 22: Raphael Robertazzi IBM Research · 2017-03-26 · 6/12/02 IBM RESEARCH Page [2] Outline • Motivation: Test High Speed Area Array ICs In The Development Stage, At Wafer Level. –

6/12/02 IBM RESEARCH Page [22]

Conclusion

• Demonstration Of A New Cobra Probe Card With Increased Bandwidth:– 20X Bandwidth Improvement Over Conventional Cobra

Probe Card (Micro Coax).– 3-4X Bandwidth Improvement Over Conventional Cobra

Probe Card (Twisted Pair And Direct Cable To Card Connection).

• High Speed Line Bandwidth Limitation Gated By Cobra Head.Paths To Higher Frequencies:– Engineering 50 Ohm Cobra Head.– Using TFI Contactor.

• New Probe Card Can Be Constructed In 4-6 Weeks.