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RAD750Mohsin Farooq
Nicolas Schrading
Overview• Single board computer and processor• Radiation hardened up to 10,000 gray• 2.5V, 250nm, 6-layer CMOS technology• Exact same Superscalar RISC as PowerPC 750• 110 - 200MHz• Split 32KB L1 Cache, 256KB - 1MB L2 Cache
Companies InvolvedDesigned by: Manufactured by:
Used by:
Cost
~$200,000 per CPU!
Why?•Radiation: huge problem!
o Testing takes much longer o It has to be 100% reliable
Space Problems
• Extremely high reliability.• Need for long product lifetime.• Thermal Management.• Electromagnetic compatibility.• Large amount of radiation!
All must be done while minimizing cost!
The Problem of Radiation
Van Allen Radiation Belt Solar Flares and Galactic Cosmic Radiation
Electrons up to 10 MeV, protons up to 100s MeV
Several GeVs
Most energetic observed: 300EeV!
- Anything > 100MeV harmful to microlectronics
The Problem of Radiation• Single Event Upsets (SEUs) caused by high-energy particles
striking sensitive nodes in microelectronic device.o Cause unwanted state changes in memory/registers.o Cause pulses in logic or support circuitry.
• Destructive strikes known as Single Event Latchup (SEL), Single Event Gate Rupture (SEGR), or Single Event Burnout (SEB)
The Problem of RadiationSEL caused by high energy particle passing through a p-n transistor junction, creating a Thyristor effect: low-impedance path between power supply rails of MOSFET circuit.
Without a powercycle, high current permanently damages the circuit.
p-n junction
Equivalent circuit of latchup
The Problem of Radiation• SEGR - Heavy ion hits the gate while a high voltage is
applied to it. Local breakdown occurs in the insulating layer, causing overheating and destruction of the gate.
• SEB - If substrate under source region is forward-biased by a particle, and the drain-source voltage is higher than breakdown voltage, get high current and overheating.
Illustration of SEGR and SEB
Solutions
• Lead Room?o 1 square foot of lead weighs 59 lbs.o cost? $10,000 per pound.o Not feasible.
• Radiation Hardening?
Radiation Hardening• Add an insulating layer (silicon dioxide or sapphire) around both NMOS and
PMOS transistors.o Makes chip immune to SEUs.o Removes most SELs.o Chip can still be high speed and low power.o Drastic increase in substrate cost.
Radiation Hardening• Bipolar integrated circuits (TTL) are generally better than CMOS
• Power MOSFETS are the most susceptible to SEBo SEB can occur at less than 30 V biaso BJTs are less susceptible beginning at 400 V
• TTL logic generally takes more power and produces more waste heat
Radiation Hardening• MRAM much greater tolerance to SEUs than SRAM and DRAM.• Tie points throughout the processor force high-energy particles to discharge to
ground.• Parity bits to fix SEUs• Redundant components: Independently calculate answers, compare. Any system
that produces a minority result recalculates. If repeated errors occur from the same system, that board is reset.
• Turn off cache during travel through particularly radioactive areas.• Watchdog timer causes hard reset after system unresponsive.
A Challenger Appears!
Commercial PowerPC 750 vs RAD750
Rad750 much larger due to radiation hardening redesigns
BUT:5 - 6 orders of magnitude better in terms of SEU performance (radiation upsets)
PowerPC Instruction Set
• RISC• Instruction Set: PowerPC 32-bit• Integer Size: 32 bit• Physical Address space: 32 bits• Virtual Address space: 52 bits
o Divided into 4-Kbyte pages, each of which can be mapped to a physical page.
Execution units• Floating-point unit (FPU)• Branch processing unit (BPU)• System register unit (SRU)• Load/store unit (LSU)• Two integer units (IUs) • IU1: execute all integer instructions.• IU2: execute all integer instructions except multiply and
divide.
Block Diagram6 Execution Units:
Branch
System
Floating Point
2 Integer
Load / Store
Register Set● UISA Registers are user-level● General-purpose registers
(GPRs)● Floating-point registers(FPRs)● Condition register (CR)● Floating-point status and control
register (FPSCR)● All can be accessed by software
with either user or supervisor privileges.
Cache• Split 32-Kbyte, eight-way set associative instruction and data cache. (Harvard
architecture)• Pseudo least-recently-used (PLRU) replacement algorithm.• 32-byte cache block.• Two coherency state bits for each data cache block.
o Modified (M)o Exclusive (E)o Invalid (I)
• Single coherency state bit for instruction cache block.o Invalid (INV)o Valid (VAL)
Dynamic Branch Prediction
Uses a 512 entry x 2-bit Branch History Table and maintains two speculations
Branch Unit connected to instruction fetch for Branch Target Buffer (BTB)
Power Management• Dynamic power management powers down unused functional units by shutting
down their clocks.• 3 levels of decreased power:
o Doze: Keeps cache active with “snooping”-based cache coherence.o Nap: Disables snooping, keeps Phase Locked Loop (PLL) to maintain higher
clock rate.o Sleep: Shuts down PLL, requires 100us delay to return to higher
performance.
• Also has low-speed continuous operation mode
Power Management
• Thermal Assist Unito Monitor junction temperature through the incorporation of
an on-chip thermal sensor.o TAU provides thermal control by comparing the 750’s
junction temperature against user-programmed thresholds.
• Instruction Cache Throttlingo Reduce the instruction execution rate without overhead of
dynamic clock control.
Why not Core i7?
• Long process for radiation hardening • Parity logic needed for memory such as
“scrubber”.• Voting logic needed for redundant check bit
check. (increases chip area by a factor of 5)• Thorough testing of all features.
Future Improvements
• Magnetic Shield coupling:o Previously dismissed as unrealistically expensive.o But new experiments show promising results to make
compact (implying cheaper) protection.o Separate out electrons and protons of the solar wind
creating a separation of charge which would deflect particles away from the shield.
• Cost of payload per pound to decrease significantly in the upcoming years.
Conclusion
RAD750 is successful, widely used5-6 orders of magnitude better in radiation than commercial counterpart
Reliable
Sourceshttp://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.48.1291
http://www.klabs.org/DEI/Processor/PowerPC/rad750/papers/spacewire_con_2007.pdf
http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=00931184&tag=1
http://trs-new.jpl.nasa.gov/dspace/bitstream/2014/11883/1/02-0576.pdf
http://parts.jpl.nasa.gov/docs/Radcrs_Final.pdf
http://www.smpstech.com/power-mosfet-single-event-burnout.htm
https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/2F33B5691BBB8769872571D10065F7D5/$file/750cldd2x_ds_v2.6_16Oct2009dft.pdf
http://www.wired.com/wiredenterprise/2012/08/martian-computing-is-light-on-ram-heavy-on-radiation-shielding/