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Quick Start tutorial for Xilinx ISE with ISim

Fredrik Linde 2011 / Mazhar Hussain 2011 / Mikael Bylund 2014

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Xilinx ISE Project Navigator

Start Xilinx ISE

Chose New Project… in the Getting Started window or go to the menu File>New Project…

Create New Project

Name your project by filling in the field Name:

Location is the place where the project files will be saved. If you save your project to C:

remembers to copy all files to H: at the end of the Lab or you might lose your project. You are

strongly advised not to work with your project on your H: drive since this will give you long

access times.

Top-level source type shall be HDL in our case.

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When you have filled in your projects name hit Next.

Device Properties

Fill in your target device specifications and choose Synthesis Tool and Simulator and hit Next.

Create New Source

To add the first file, create a new source file by hitting New Source…

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Select Source Type

Select VHDL Module, name the file in the field File Name: and hit Next.

Define Module

Here you can name your entity and architecture, and define in and outputs. When ready press

Next.

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Summary

Read the summary and hit Finish.

Create New Source (revisited)

Now you are back to Create New Source, hit Next.

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Add Existing Sources

If you got files that you know that you want in your project you can add them now or just press

Next directly.

Project Summary

Read the project summary and hit Finish.

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ISE Project Navigator standard view

When the project is created you will be given a view looking like this

The file we created with the wizard can be reached through the tab (first.vhd) in the middle of

the screen just left to the Design Summary underlined with blue. You could also double click on

first –Behavioral in the Hierarchy window.

Add this code snippet between begin and end in the architecture and hit save.

process(clk)

begin

output <= not(clk);

end process;

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Simulations in ISim

Now you are going to simulate logic in the hardware description.

In the top left corner, after Sources for: there is a drop down menu. In the drop down menu

select Behavioral Simulation and the two windows below will change its content. If you now

click on first – Behavioral in the Hierarchy window then the window below will change to

Processes: first – Behavioral . In the Process window expand ISim Simulator and right click on

Simulate Behavioral Model then select Run from the menu. This will start a second program

called ISim that is used for simulations.

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ISim

ISim is a tool where you can look at the ones and zeros to see if the hardware is giving the

expected output at a known input. This is where we check that the logic in the hardware is

functioning correctly.

Zoom

With the wave window selected you can use the zoom in, zoom out, zoom full, and zoom to

cursors buttons, which is helpful to get the whole picture or going in to details when analyzing

the results.

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Force input and Run simulation

The signals start out being undefined. To make a one-time change to a value, you can use the

put command in the console at the bottom of the window. For instance, using put output 1 will

set the output value to 1. When you next run the simulation, this new value will show up in the

graph. You can run the simulation by pressing the Run for the time specified on the toolbar

button.

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If your hardware is clock driven you can set the clock signal to change over time. To do so, you

can use the console command isim force add clk 0 -value 1 -time 25 ns -repeat 50 ns. After you

run the simulation again, the result will show up in your wave window. You may need to adjust

the zoom level to see the region you are interested in.

Changing signal values manually works for simple tests, but for more

advanced tests you want to use a Test Bench. A Test Bench contains pre-

configured signal changes that will allow you to thoroughly test even large

number or signal combinations. If your test bench covers a larger time span

than the one chosen in the toolbar, you can either increase the toolbar run

time value or use the Run All option.

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How to create TestBench for your Project …………………………By Mazhar Hussain

The VHDL test bench contains procedures and functions written in VHDL which allow the user to

test their code against all possible input values.

After creating your *.vhd file now it’s time to create a testbench. Follow the steps to create your

own test bench

Step 1:

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Step 2:

Step 3:

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Step 4: