\

USN 06EC4s

Fourth Semester B.E. Degree Examination, Dec.09-Jan.10Fundamlntals of HDL

Time: 3 hrs' Note: Answer any FrvEfull questions, s;electing

at least TWO questions'from each pian.

PART - A-I a. Explain the structure of VHDL module and Verilog module.

b. Given A: 1000 and B = 0011, perform the following otrierations :i) AXr{oR Bii) Shift B t'wo position left logicaliii) Reduction NANDiv) Verilog concatenation {A, B},'i Veriloi ,ooiutu, A%8, (oslvrarks)Explain the Verilog data types.List the types of descriptions. Write VHDL code to describe one bit tull adder

"rffiXf]stylq description. (06 Marks)

2 a. What are the facts of data flow description? Explain with an example the execution of signalassignment statement in HDL. (06 Marks)

b. Derive a minimized Boolean function of the system that has three I bit input 'a' and I bitoutput 'b ' . The output 'b ' is '1 'when input 'a ' is 1,3, 6,7,otherwise 'b i is 'o ' , wr i te adatdflow ciescription in VHDL. What is the function of this system? (04 Marks)

c. Write the block diagram of a 4 bit ripple carry adder and its Boolean functions, Write adataflow description in verilog. Assume 3 ns propagation delay for all two input gates. Draw

c.d.

q,.e(J

E_o-otral,o

.ro

"9,ctut g)o .l:

HeEE=tF.EOC+'FsQCD

OF

=g

;=9,9EO

MEY6( )o,

s€Ebvo

=6g_:3(s3db9a_Etu;i o.Fo-

, . 5q( e.Eg6

ae. oc

LO

o'->EPor

'j5 .=gEo.c 't r>6Eo>

o<a- Crl

irt'oz.

Eooo

Max. Marks:100

(05 Marks)

(10 Marks)

(02 Marks)

(08 Marks)

the simulation waveform.

3 a. Explain the execution of process statement.b. Distinguish between :

i) VHDL IF and VHDL case iD VHDL Next and Exitiii) verilog repeat and verilog forever iv) Always and initial.

using behaviora! style of description.

4 a. Explain how binding is achieved in VHDL between :i) Entity and component ii) Library and module

b. Write a VHDL structural description of a full adder using two half addei and apWrite the simulation waveform.

c. Write a Verilog structural description of a N : 3 bitstatement.

c. Using Booth algorithm, find the product of two 4 bit numbers -3 and 8. Write a Verilog code(10 Marks)

(04 Marks)OR gate.

(08 Marks)magnitude comparator using generate

(08 Marks)

PART - B

5 a. What are the significance of procedure, tasks and functions? Differentiate between

" procedute/task and function. (04 Marks)

b' Write a code to convert the unsigned integer to CN: 4) binary using procedure. iot *".nric' Write a VHDL code for finding the word with the lowest ASCII value using file operations.

(08 Marks)

I of2

6a.

b.

c.

7a.

b.

c.

068C45

Explain the implementation of single dimensional and two dimensional arrays in'Vt{DL. .

. - : - -Write a block diagram and functi'on table of 128 x 16 static memory. \Mrite a Verilog code.

V"tfr G""de bl;;;1"ti";;;".f"*t by writing dgla in memorylocations 8; 18, 46,126

and read the contents_ of lwo mem.orl locatlons l8 and 4f,, -

Explain the fetch and exebute cycles of basic computer'for the following operatiorls :'

Halt, Add, Mult, NAND. (oSMarks)

8a.b.

Write mixed-language description of a mastqr slave Dfrom a Verilog module.Write a mixedJanguage description of an AND gateVHDL module.

,.,, Explain the mapping to gate level logic diagrarn.

nop invok''* " Y*JIHinvoking a venlog t"%frlT*l

(08 Marks)

What are the limitations of mrxed-language descriptions? '

, ' ' ' (04 Marks)

What is synthesis? List the general steps involved in synthesis. (08 Marks)

Give synthesis information extracted, when the input and output are defined as : ,i) bit

- ii) Std * logic - vector. (04 Marks)

rirrit. a behavioral code in Vrrpr and Verilog for the signal assignment statement Y : X.

**d.* : f

2 of2

Fundamentals of HDLTime: 3 hrs. Max' Marks:loo

Note: 7. Answer any FIVE full questions selecting at least TIVO from each paft.

06EC45

toaTbi t(06 Marks)(08 Marks)

(08 Marks)

PART _A1 a. Write the result of all shift and rotate operations in VHDL after applyrng thern

vector A : 1001010.b. Explain composite and Access data types with an example for each.

b. Explain vailog Repeat and Forever staternents with an example.s. Write verilog code for a 4-bit counter with synchronous hold.

c. Mention different styles (types) of descriptions. Explain mixed type and mixed languagedescriptions. (06 Marks)

2 a. How do you assign delay to a signal assignment statement? Explain with an example in

VHDL and verilog (04 Marks)b. What is a vector? Give an example for VHDL and verilog vector data types. (04 Marks)c. With ttre help of a truth table and K-maps write Boolean expression for a 2-bit magnitude

comparator. Write YHDL / verilog code (12 Marks)

3 a. Write VHDL code,f,or a D-latch using variable assignment and signal assignmentstatsments. With simulation waveforms clearly distinguish between the 2 statements.

(10 Marks)(04 Marks)(06 Marks)

4 a. What is binding? Discuss binding between two modules in verilog. (06 Marks)b. Write -{HDL behaviorat description of a tristate buffer. Use this as a component for

structural description of a 2to 4 decoder with histate oufput. (10 Marks)c. Explain the use of GeneriC (in VHEL) and parameter (in verilog) with an example.

(04 Marks)

(08 Marks)(04 Marks)

Table Q.5(c) below shows a file containing real numbers. Write a VHDL code for readingthe file, multiply the first number by 2, second by 5, third by 3 and fourth by 4. The products

5a.b.c.

6a.b.c.

7a.

b.

8a.b.

c.

'

Write verilog code to convert a signed binary to lnteger using task.Write VHDL / verilog function to find greater of 2 signed numbers.

t to be stored in real variables z,zl,z2 andz3 fpfctilelq.-t3.4 '5.564 0.23.55.32

Table Q.5(c) File file real . txt

Write a note on packages in VHDL (05 Marks)W:ite VHDL code for addition of two 5 x 5:rnatrices using a package. (07 Marks)Write the block diagram and function table of a SRAM. Using these, write a verilogdescription for 16 x 8 SRAM. (08 Marks)How to invoke a verilog module from a VHDL module? Explain with an example of amixed language description for a fuIl adderusing 2 half adders. (10 Marks)Write a mixed language description of a 9-bit adder consisting of three 3-bit carry-lookahead adders to show how a verilog module invokes VHDL entity. , (10l\rarks)

Explain extraction of synthesis information from Entity. (04 Marks)With an example explain verilog synthesis information extraction from module inputs andoutputs. (04lVlarks)Write VHDL /, verilog code for signal assignment statement Y : (2* x -t- 3) for an entitywith one input X of 2-bits and one output Y of 4-bits. Show mapping of this signalassignment to gate level.

****d.

________-f{

!

,//

AN06EC45

(07 Marl{s)(0E Marks)(05 Marks)

examples.' (06 Marks)

adder with active(08 Marks)(06 Marks)

(08 Marks)Verilog description for 4x 4-

(12 Marks)

(08 Marks)in VHDLA/erilog,

(12 Marks)

(08 Marks)(06 Marks)

(04 Marks)

Fourth Semester B.E. Degree.Examination, Dec 08 / Jan 09

Fundamentals of HDLTime: 3 hrs.

Note : Answer FIVE full questions, selecting atleast TWOquestions from each part.

PART - A:tlpes of HDL descriptions. Explain dataflow and behavioral descriptions.

b. Discuss different logical operators used in HDLS.c. Compare VHDL and Verilog.

2 a, Explain signal declaration and signal assignment statelnents with relevant

b. Write a data - flow description (in both VHDL and Verilog) for a fullhigh enablei

c. Write HDL codes for 2x 2-bit combinational an4y multiplier.

a. Explain IF and CASE statements with examples.b. Explain Booth algorithm with a flow chart. Write VHDL or

bit Booth algorithm.

a. What is Binding? Discuss the binding between library and components.b. Write the HDL descrilltion of 2:l multiplexer with active low enable

using structural style;

PART. Bt u: Explain the foitowing with syntal @ Prgcedures in VHDL (ii) Tasks in Verrlog

(06 Marks)b. Write VHDLA/erilog code to convert a fractional Binary to Real number using

b. Describe the development of HDL code for aq Arithrnetic Logic Unit and write(16 Marks)

gi|t

Fig.6(b)Assume the following operations : - Addition, Multiplication, Division, No Operation.

How to invoke a VHDL entity from a Verilog module. (08 Marks)Explain mixed language description of a JK Flip - Flop with a -clear pin and write thesimulation waveform. : (12 Marks)

Procedures/Tasks.c. Describe all f,rle processing tasks in Verilog. '

a. What is the necessity of Mixed-type description?

VHDLA/erilog code for an ALU, showp in fig.6(b).1fu*- . ,|

- L1nP&w

a. Describe synthesis inlbrmation extraction from entity and module with examples.

b. Explain mapping the signal - assignment and variable assignment statements to Gate=levelwith suitable examples. (10 Marks)

*****

7a.'b.

*'ffihl<tru^,'

t .LI

1,; I t-JIF

.i

1,!

, /I UsN

/

Time:3 hrs.

ta.

' , ,b.

Max. Marks:100

Notc : Ansryet any FIWfuIl questions choosing at least TWefrom each part.

06EC4s

of VHDL data(06 Marks)(06 Marks)

I Fourth semester B.E. Degree Examination, June/July 0gFundamentals of VHDL

part - A

Explain how data types are classified in HDL. Mention the advantagestypes over verilog.Writebehavioral?escripioriofthecircuitofFig.l(b)usingVIDL.

Fie'l(b) jF?t th: h".^ry| circuit of Fig.l(c) write-switch level description in verilog. Explain theadvantage of this type description over the other typ:e. 1oa ruart<sy'..

fr (p14p$

Ynr CNrtos)

flr'4Fig.l(c)

With illustrations briefly discussD Signal declaration and assignment statementsii) Concurrent signal assignment statements andiii) Constant declaration and assigrment statements.

l of2

2&"

(09 Marks)

b. For the multiplexer circuit of Fig.2(b), writein VHDL. Assume 10 nsec as propagationapplicable.

+\

06EC45' :

sigrlal declaration and assi gnment statementsdelay. Write your comments, wherever it is

(12 Marks)

(09 Marks)Explain how

(l l Marks)

Fig.2(b)Explain how an object that has a rvidth of more than I bit is declared in HDL using vectordata types. Give examples. (05 Marks)Write behavioral description of half adder in VHDL and verilog with propagation delay of5 nsec, Discuss the important features of their description in VHDL and verilog. (08 Marks)

a.

b.a.

5a.

b.6a.

b.c.

ta.

b.8a.

b.c,

b.

Explain the structure of various loop statements in HDL with examples.What is binding? Discuss binding between

i) Entity and architectureii) Entity and components andiib ninaing between library and module in VHDL with examples.

Write complete VFIDL description for full adder using two half adders.binding is incorporated with half adder.

Part * B

Explain the following syntax with examples :D Procedure ii) Task and iii) Function

How to invoke a verilog module from VHDL module? Write a mixed language descriptionof an 'OR' gate where VHDL code invokes the verilog module 'OR3' (3 input OR gate).

Write VHDL description of an N bit ripple carry adder using procedure.Describe all file processing procedures in VHDL with examples.Why mixed type description is needed? ExplainWrite a VIIDL code for finding largest element of an array.

Write a mixed language description of a 4 bit adder with zero flag.What are the limitations of mixed language description?Discuss some of the important facts related to synthesis.Discuss synthesis information from entity with examples.

2 of?

(08 Marks)(12 Marks)

(08 Marks)

(04 Marks)

(08 Marks)

(10 Marks)(10 lflarks)(05 S{arks)(07 Marks)(08lllarks)