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Logic Design 10CS33

Dept. of CSE, SJBIT Page 1

Question Bank Solutions

UNIT-I &II: Digital Principles, Digital Logic

1. Explain Duality Theorem? (Jan’10)

One can transform the given expression by interchanging the operation (+) and (•)

as well as the identity elements 0 and 1 . Then the expression will be referred as

dual of each other. This is known as the principle of duality.

Example x + x = 1 then the dual expression is x • x = 0

2. Differentiate between Positive Logic and Negative Logic (Dec’11) (Dec’12)

Positive Logic: With reference to positive logic, logical 1 state is the most positive logic or

voltage level and logic 0 state is the most negative logic or voltage level. In other words,

active high level is 1 and active low level is 0. For instance, V(0) = 0V and V(1) = 5V,

V(0) = 5V and V(1) = 15V.

Negative Logic: With reference to negative logic, logic 0 state is the most positive logic or

voltage level and logic 1 state is the most positive logic or voltage level. In other words,

active high level is 0 and active low level is 1. For instance, V(0) = 5V and V(1) = 0V,

V(0) = 15V and V(1) = 5V.

3. Using Karnaugh Map,simplify the following boolean expression and give the

implementation of the same using Dec,2010(8 m) & Dec’12

Logic Design 10CS33


i)NAND gates only(SOP) ii) NOR gates only (POS ) a. F(w,x,y,z)=∑m(0,1,2,4,5,12,14)+dc(8,10)

F(w,x,y,z)=∑m(0,1,2,4,5,12,14)+dc(8,10)

a. NAND Gate (SOP form)

C’D’ C’D CD CD’

A’B’ 1 1 1

A’B 1 1

AB 1 1

AB’ X X

F(A,B,C,D) = C’D’ + A’C’ + AD’ + B’D’

b. NOR gate (POS form)

F(A,B,C,D) = (A + C)(C+D)(A’+D)(B+D)

4. What are Universal gates? Implement the basic gates using Universal gates

only Dec’08/Jan’09/june 12/Dec ‘12 A universal gate is a gate which can implement any Boolean function without need to use any

other gate type. The NAND and NOR gates are universal gates.

Implementing an Inverter Using only NAND Gate The figure shows two ways in which a NAND gate can be used as an inverter (NOT gate).

1. All NAND input pins connect to the input signal A gives an output A’.

2. One NAND input pin is connected to the input signal A while all other input pins are

connected to logic 1. The output will be A’.

Implementing AND Using only NAND Gates An AND gate can be replaced by NAND gates as shown in the figure (The AND is replaced by a

NAND gate with its output complemented by a NAND gate inverter).

Implementing OR Using only NAND Gates

Logic Design 10CS33


An OR gate can be replaced by NAND gates as shown in the figure (The OR gate is replaced by a

NAND gate with all its inputs complemented by NAND gate inverters).

Thus, the NAND gate is a universal gate since it can implement the AND, OR and NOT

functions.

NAND Gate is a Universal Gate: To prove that any Boolean function can be implemented using only NOR gates, we will show that

the AND, OR, and NOT operations can be performed using only these gates.

Implementing an Inverter Using only NOR Gate The figure shows two ways in which a NOR gate can be used as an inverter (NOT gate).

.

Implementing OR Using only NOR Gates An OR gate can be replaced by NOR gates as shown in the figure (The OR is replaced by a NOR

gate with its output complemented by a NOR gate inverter)

Implementing AND Using only NOR Gates An AND gate can be replaced by NOR gates as shown in the figure (The AND gate is replaced by a

NOR gate with all its inputs complemented by NOR gate inverters)

Thus, the NOR gate is a universal gate since it can implement the AND, OR and NOT

functions.

Logic Design 10CS33


5. Find the PRIME IMPLICANT with the help of Qunie-Mc Clusky Method. F(w,X,Y,Z) = ∑m(1,3,6,7,8,9,10,12,13,14) June’11(08m) & Dec’12

No W X Y Z Index

1 0 0 0 1 1

3 0 0 1 1 2

6 0 1 1 0 2

7 0 1 1 1 3

8 1 0 0 0 1

9 1 0 0 1 2

10 1 0 1 0 2

12 1 1 0 0 2

13 1 1 0 1 3

14 1 1 1 0 3

List the minterm in increasing order of their index

No W X Y Z Index

1 0 0 0 1 1

8 1 0 0 0 1

3 0 0 1 1 2

6 0 1 1 0 2

9 1 0 0 1 2

10 1 0 1 0 2

12 1 1 0 0 2

7 0 1 1 1 3

13 1 1 0 1 3

14 1 1 1 0 3

No W X Y Z Index

1,3 0 0 _ 1 2

1,9 _ 0 0 1 2

8,9 1 0 0 _ 2

8, 10 1 0 _ 0 2

8,12 1 _ 0 0 2

3,7 0 _ 1 1 3

6,7 0 1 1 _ 3

6,14 _ 1 1 0 3

9,13 1 _ 0 1 3

10,14 1 _ 1 0 3

12,13 1 1 0 _ 3

12,14 1 1 _ 0 3

Logic Design 10CS33


Prime Implicant: A’B’D + B’C’D + A’CD + A’BC + BCD’ + AC’ + AD’

6. Simplify the following expression using Quine-Mc Clusky Method

(Dec’10,8m) & Dec’12

f(w,x,y,z) = ∑m(0,2,3,4,8,10,12,13,14)

Step 1: Represent each minter in its 1-0 notation

no. minterm 1-0 notation index

0

2

3

4

8

10

12

13

14

w x y z

w x y z

w x y z

w x y z

w x y z

w x y z

w x y z

w x y z

w x y z

0 0 0 0

0 0 1 0

0 0 1 1

0 1 0 0

1 0 0 0

1 0 1 0

1 1 0 0

1 1 0 1

1 1 1 0

0

1

2

1

1

2

2

3

3

Step 2: List the minterm in increasing order of their index.

No. w x y z index

0

2

4

8

3

10

12

13

14

0 0 0 0

0 0 1 0

0 1 0 0

1 0 0 0

0 0 1 1

1 0 1 0

1 1 0 0

1 1 0 1

1 1 1 0

Index 0

Index 1

Index 2

Index 3

W x y z index

Logic Design 10CS33


0.2

0,4

0,8

2,3

2,10

4,12

8,10

8,12

10,14

12,13

12,14

0 0 – 0

0 – 0 0

- 0 0 0

0 0 1 –

- 0 1 0

- 1 0 0

1 0 – 0

1 – 0 0

1 – 1 0

1 1 0 –

1 1 - 0

w x y z

(0, 2, 8, 10)

(0, 4, 8,12 )

__ 0 __ 0

__ __ 0 0(index 0)

(8,10,12,14) 1__ __ 0 (index 1)

F(w,x,y,z)=x z + y z +w z+w x y +w x z

PRIME IMPLICANTS AND IRREDUNDANT EXPRESSION

F(W,X,Y,Z)= ∑M(0,1,2,5,7,8,9,10,13,15)

A=X Y , B= X Z C= Y Z D= X Z

P = (A+B)(A+C) (B)(C+D)(D)(A+B)(A+C)(B)(C+D)(D)

P = (A +C)(BD) = ABD +BCD

F1(W,X,Y,Z)= ABD =X Y +X Z +X Z

F2(W,X,Y,Z) = BCD = X Z + Y Z +X Z

7. Explain different models for writing Verilog modules.Give an example for

each. June’12(08 m) A module is the building block in Verilog. It is declared by the keyword module and is

always terminated by the keyword endmodule.Each statement is terminated with a

semicolon, but there is no semi-colon after endmodule.

A module can be described in any one (or a combination) of the following modeling

techniques.

� Gate-level modeling using instantiation of primitive gates and user defined

modules.

� This describes the circuit by specifying the gates and how they are

connected with each other.

� Dataflow modeling using continuous assignment statements with the keyword

assign. � This is mostly used for describing combinational circuits.

Logic Design 10CS33


� Behavioral modeling using procedural assignment statements with keyword

always.

� This is used to describe digital systems at a higher level of abstraction.

Gate-level modeling: Here a circuit is specified by its logic gates and their interconnections.

� It provides a textual description of a schematic diagram.

� Verilog recognizes 12 basic gates as predefined primitives.

� 4 primitive gates of 3-state type.

� Other 8 are: and, nand, or, nor, xor, xnor, not, buf

//Gate-level hierarchical description of 4-bit adder

module halfadder (S,C,x,y);

input x,y;

output S,C;

//Instantiate primitive gates

xor (S,x,y);

and (C,x,y);

endmodule

Dataflow Modeling: Dataflow modeling uses continuous assignments and the keyword

assign.A continuous assignment is a statement that assigns a value to a net. The value assigned

to the net is specified by an expression that uses operands and operators.

//Dataflow description of a 2-to-4-line decoder

module decoder_df (A,B,E,D);

input A,B,E;

output [0:3] D;

assign D[0] = ~(~A & ~B & ~E),

D[1] = ~(~A & B & ~E),

D[2] = ~(A & ~B & ~E),

D[3] = ~(A & B & ~E);

endmodule

Behavioral Modeling : Behavioral modeling represents digital circuits at a functional and

algorithmic level.

� It is used mostly to describe sequential circuits, but can also be used to describe

combinational circuits.

� Behavioral descriptions use the keyword always followed by a list of procedural

assignment statements.

� The target output of procedural assignment statements must be of the reg data type.

� A reg data type retains its value until a new value is assigned.

//Behavioral description of 2-to-1-line multiplexer

module mux2x1_bh(A,B,select,OUT);

input A,B,select;

Logic Design 10CS33


output OUT;

reg OUT;

always @(select or A or B)

if (select == 1) OUT = A;

else OUT = B;

endmodule

8. Implement the following SOP function (July,2011)

F = XZ + Y’Z + X’YZ Being an SOP expression, it is implemented in 2-levels as shown in the figure.

Introducing two successive inverters at the inputs of the OR gate results in the shown

equivalent implementation. Since two successive inverters on the same line will not have an

overall effect on the logic as it is shown before. By associating one of the inverters with the

output of the first level AND gate and the other with the input of the OR gate, it is clear that

this implementation is reducible to 2-level implementation where both levels are NAND gates

as shown in Figure.

9. Differentiate between Analog and Digital Signals Jan’2012 & Dec’12

An Analog signal is any continuous signal for which the time varying feature (variable) of the

signal is a representation of some other time varying quantity, i.e., analogous to another time

varying signal. It differs from a digital signal in terms of small fluctuations in the signal which are

meaningful.

Logic Design 10CS33


A digital signal uses discrete (discontinuous) values. By contrast, non-digital (or analog) systems

use a continuous range of values to represent information. Although digital representations are

discrete, the information represented can be either discrete, such as numbers or letters, or

continuous, such as sounds, images, and other measurements of continuous systems.

10.

Comparison chart

Analog Digital

Technology: Analog technology records waveforms

as they are.

Converts analog waveforms into set of

numbers and records them. The

numbers are converted into voltage

stream for representation.

Representation: Uses continuous range of values to

represent information.

Uses discrete or discontinuous values

to represent information.

Uses:

Can be used in various computing

platforms and under operating systems

like Linux, Unix, Mac OS and

Windows.

Computing and electronics

Signal:

Analog signal is a continuous signal

which transmits information as a

response to changes in physical

phenomenon.

Digital signals are discrete time signals

generated by digital modulation.

Clocks: Analog clocks indicate time using

angles.

Digital clocks use numeric

representation to indicate time.

Computer:

Analog computer uses changeable

continuous physical phenomena such as

electrical, mechanical, hydraulic

quantities so as to solve a problem.

Digital computers represent changing

quantities incrementally as and when

their values change.

10. Compare TTL and CMOS families and the integration level of ICs

The Comparison of TTL and CMOS is clearly illustrated in the following table as an example of

differences in the logic families:

Logic Design 10CS33


TTL CMOS

• Faster

• Stronger drive

capability

• Low power consumption

• Simpler to make

• Greater packing density

• Better noise immunity

Integration Levels:

The devices greatly differ in the density of fabrication ie the levels of integration

used.Depending on the number of transistors/diodes/gates used in the chip they are broadly

classified as :

• SSI -small scale integration

• MSI -medium scale integration

• LSI -large scale integration

• VLSI -very large scale integration

• ULSI -ultra large scale integration

• GSI -giant scale integration

Levels of

integration

Transistors/package Gates/chip Applications

SSI 1-100 <12 Logic gates Op-amps

MSI 100-1000 12-99 Registers Filters

LSI 1000-10000 1000 8 bit processor, A/D converter

VLSI 10k gates/chip 16,32 bit processor

256KB memory

DS processor

ULSI 100k gates/chip 64 bit processor

8 MB memory

Image processor

GSI 1M gates/chip 64 MB memory

multiprocessor

Logic Design 10CS33


11. Prove that ABC + ABC' + AB'C + A'BC = AB + AC + BC ABC + ABC' + AB'C + A'BC

=AB(C + C') + AB'C + A'BC

=AB + AB'C + A'BC =A(B + B'C) + A'BC

=A(B + C) + A'BC

=AB + AC + A'BC

=B(A + C) + AC

=AB + BC + AC

=AB + AC +BC ...Proved

12. What is a karnaugh map? State the limitations of karnaugh map

A karnaugh map or k map is a pictorial form of truth table, in which the map diagram is made

up of squares, with each squares representing one minterm of the function. Generally it is limited

to six variable map (i.e) more then six variable involving expression are not reduced. ii) The map

method is restricted in its capability since they are useful for simplifying only Boolean

expression represented in standard form.

13. What are called don’t care conditions?

In some logic circuits certain input conditions never occur, therefore the Corresponding output never

appears. In such cases the output level is not defined, it can be either high or low. These output levels are

indicated by ‘X’ or‘d’ in the truth tables and are called don’t care conditions or incompletely specified

functions.

14. Explain the significance of Demorgan’s theorem July 2011

DeMorgan's theorems state that inverting the output of any gate results in the same function as

the opposite type of gate (AND vs. OR) with inverted inputs. • DeMorgan's Theorems describe

the equivalence between gates with inverted inputs and gates with inverted outputs. Simply put, a

NAND gate is equivalent to a Negative-OR gate, and a NOR gate is equivalent to a Negative-

AND gate.

• When "breaking" a complementation bar in a Boolean expression, the operation directly

underneath the break (addition or multiplication) reverses, and the broken bar pieces

remain over the respective terms.

Logic Design

Dept. of CSE, SJBIT

13.Does circuit in below figure

with timing diagram

Does circuit in below figure experience hazard? If so, verify th

with timing diagram (Jun’12) & Dec’12

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Page 12

experience hazard? If so, verify the same

& Dec’12

Logic Design

Dept. of CSE, SJBIT

Unit-3 :Data-Processing Circuits

1 Show that using a 3-to-

Boolean expression can be realized.

Σm(1,5,7)

2. Implementation of F(A,B,C,D)=

using a 16-to-1 multiplexer.

Processing Circuits

-8 decoder and multi input OR gate. The following

Boolean expression can be realized.F1(A,B,C) = Σm(1,2,4,5),

(July’11)

Implementation of F(A,B,C,D)=∑ (m(1,3,5,7,8,10,12,13,14), d(4,6,15)) By

1 multiplexer. (Dec,2010)

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Page 13

8 decoder and multi input OR gate. The following

, F2(A,B,C) =

(July’11)

∑ (m(1,3,5,7,8,10,12,13,14), d(4,6,15)) By

(Dec,2010) & (Dec’12)

Logic Design

Dept. of CSE, SJBIT

3. Explain the 8 word X 4 bit ROM with the help of block diagram.

4. Explain the Implementation of Full adder using PLA

SUM = X’Y’Cin + X’YCin’+ XY’Cin’ + XYCin

Carry = XCin +YCin + XY

Explain the 8 word X 4 bit ROM with the help of block diagram.

Explain the Implementation of Full adder using PLA

SUM = X’Y’Cin + X’YCin’+ XY’Cin’ + XYCin

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Page 14

Explain the 8 word X 4 bit ROM with the help of block diagram.

(July’11)

Logic Design 10CS33


5. Differentiate between PROM, PAL, PLA (Dec’10)

The three fundamental types of PLDs differ in the placement of programmable connections

in the AND-OR arrays. Figure shows the locations of the programmable connections for the

three types.

6. Implement 16:1 Mux using 4:1 (Jan’09)

Logic Design 10CS33


7. Implement 4:1 mux using 2:1 mux (Jan,2011),Dec’12

8. Implement 4:16 decoder using 2:4 decoders (Dec,09)

9. What is a Multiplexer. Design a 4:1 multiplexer using gate.

(July,2011), Dec’12

A multiplexer (or MUX) is a device that selects one of several analog or digital input signals

and forwards the selected input into a single line. A multiplexer of 2n inputs has n select

lines, which are used to select which input line to send to the output.Multiplexers are mainly

used to increase the amount of data that can be sent over the network within a certain amount

of time and bandwidth. A multiplexer is also called a data selector. They are used in CCTV,

and almost every business that has CCTV fitted, will own one of these.

Logic Design

Dept. of CSE, SJBIT

10. Write the HDL code for a 4:1 mux

module mux4x1_bh (i0,i1,i2,i3,select,y);

input i0,i1,i2,i3;

input [1:0] select;

output y;

reg y;

always @(i0 or i1 or i2 or i3 or select)

case (select)

2'b00: y = i0;

2'b01: y = i1;

the HDL code for a 4:1 mux (Dec’2010

mux4x1_bh (i0,i1,i2,i3,select,y);

(i0 or i1 or i2 or i3 or select)

10CS33

Page 17

(Dec’2010 &2012)

Logic Design 10CS33


2'b10: y = i2;

2'b11: y = i3;

endcase

endmodule

11. Design a binary Full-Adder

The tuth table for a Binary full adder is as in table below:

These

In the above truth table the following terminologies have been used to represent inputs and

outputs.

•Augend –xi •Addend –yi •Carryin-ci •Sum-si•

Carryout-ci+1 From the truth Table we can write the karnaugh map for the adder as below.

Sum = xy’c’+x’y’c+ x’yc’+xyc = c(x’y’+xy)+c’(xy’+x’y)

= (x ⊕ y) ⊕ c Carryout = xy + xc+yc = x(y+c) + yc

Logic Design 10CS33


The binary full adder is capable of handling nly one bit of an augend and addend along with a

carry-in generated as carry-out from the addition of the previous lower order bit position.

If 2 binary numbers each of n –bits are to be added then as a modified approach the parallel

binary ripple adder can be configured using n binary full adders.

Logic Design 10CS33


Unit 4: Clocks, Flip-Flops

1. With the help of block diagram, explain the working of a JK Master-Slave

flip flop. Dec’2010 & 2012

All sequential circuits that we have seen in the last few pages have a problem (All level

sensitive sequential circuits have this problem). Before the enable input changes state

from HIGH to LOW (assuming HIGH is ON and LOW is OFF state), if inputs changes,

then another state transition occurs for the same enable pulse. This sort of multiple

transition problem is called racing.

If we make the sequential element sensitive to edges, instead of levels, we can overcome

this problem, as input is evaluated only during enable/clock edges.

In the figure above there are two latches, the first latch on the left is called master latch

and the one on the right is called slave latch. Master latch is positively clocked and slave

latch is negatively clocked.

Logic Design 10CS33


2. Differentiate between combinational circuit and sequential circuit. Jan’2009

Combinational Logic Circuit :

The circuit in which outputs depends on only present value of inputs. So it is possible to

describe each output as function of inputs by using Boolean expression. No memory

element involved. No clock input. Circuit is implemented by using logic gates. The

propagation delay depends on, delay of logic gates. Examples of combinational logic

circuits are : full adder, subtractor, decoder, codeconverter, multiplexers etc.

Sequential Circuits :

Sequential Circuit is the logic circuit in which output depends on present value of inputs

at that instant and past history of circuit i.e. previous output. The past output is stored by

using memory device. The internal data stored in circuit is called as state. The clock is

required for synchronization. The delay depends on propagation delay of circuit and

clock frequency. The examples are flip-flops, registers, counters etc.

3. Show how SR flip flop can be converted to a JK flip flop. June’2011

Combinational

Logic Circuit inputs outputs

Combinational

Logic Circuit

inputs outputs

Memory Device

Logic Design 10CS33


In SR FF, S=R=1 condition is not allowed.

� JK FF is modified version of SR FF.

� Due to feedback from output to input AND Gate J=K=1 is toggle condition for JK FF.

� The output is complement of the previous output.

4. Explain the functionality of RS and D flip flops. June’09

RS Flip Flop:

If S=0 and R=1, Q is set to 1, and Q’ is reset to 0

If R=0 and S=1, Q is reset to 0, and Q’ is set to 1

If S=1 and R=1, Q and Q’ maintain their previous state.

If S=0 and R=0, a transision to S=1, R=1 will cause oscillation

D Flip Flop:

Avoids the instability of the RS flip-flop

Retains its last input value

Formally known as a “Delay” flip-flop

Logic Design 10CS33


May become unstable if transisions are too close together .Is generally implemented as a special

circuit, not as pictured here.

5. Write HDL design of D-Flip flop Dec’2010 //D flip-flop

module D_FF (Q,D,CLK);

output Q;

input D,CLK;

reg Q;

always @(posedge CLK)

Q = D;

endmodule

6. Write HDL design for JK flip-flop Jan’2009 &DEC’12 module JK_FF (J,K,CLK,Q,Qnot);

output Q,Qnot;

input J,K,CLK;

reg Q;

assign Qnot = ~ Q ;

always @(posedge CLK)

case({J,K})

2'b00: Q = Q;

2'b01: Q = 1'b0;

2'b10: Q = 1'b1;

2'b11: Q = ~ Q;

endcase

endmodule

7. Implement T flip flop using JK flipflop Dec’2010

Logic Design

Dept. of CSE, SJBIT

8. With the help of a neat diagram explain the working of a Master Slave JK

flip flop

9. What do you mean by characteristic equation of a flip

characteristic equation for SR flip flop

A descriptions of the next-

map for Qt+1 in terms of the present state and input.

With the help of a neat diagram explain the working of a Master Slave JK

What do you mean by characteristic equation of a flip

characteristic equation for SR flip flop June’12

-state table of a flip-flop . Constructing from the Karnaugh

map for Qt+1 in terms of the present state and input.

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Page 24

With the help of a neat diagram explain the working of a Master Slave JK

June’2011

What do you mean by characteristic equation of a flip-flop? Derive

June’12

flop . Constructing from the Karnaugh

Logic Design 10CS33


10. Give applications of J-K flip-flops. (Dec’09)

J-K flip-flops are used in shift registers. 2. J-K flip-flops are used in counters.

11. Draw the general block diagram of multivibrator. (Jun’08)

Ans. It is as shown:

Logic Design 10CS33


F1 and F2 are the options for the connections of passive components according to the types of

multivibrator to design.

For example

(a) Astable Multivibrator: F1 = C1 and F2 = C2.

(b) Monostable Multivibrator: F1 = C and F2 = R.

(c) Bistable Multivibrator : F1 = F2 = Parallel combination of R and C of different values.

Logic Design

Dept. of CSE, SJBIT

Unit-5: Registers

1. Explain a 4 bit universal shift register in detail and give its timing

diagram.(jun’12)

2. With neat timing diagram, explain the working of a 4

(Jan’12) & Dec’12

The serial in/serial out shift register accepts data serially

line. It produces the stored information on its output also in s

register can store up to four bits of data; its

Explain a 4 bit universal shift register in detail and give its timing

With neat timing diagram, explain the working of a 4-bit SISO register

The serial in/serial out shift register accepts data serially--that is, one bit at a time

line. It produces the stored information on its output also in serial form. With four stages, this

register can store up to four bits of data; its-storage capacity is four bits.

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Page 27

Explain a 4 bit universal shift register in detail and give its timing

bit SISO register

that is, one bit at a time on a single

With four stages, this

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Dept. of CSE, SJBIT

3. Explain Johnson Counter with neat diagram and timing diagram

The switch-tail ring counter, also know as the

limitations of the ring counter. Like a ring

on its' self. It requires half the stages of a comparable ring

the complement output of a ring

Johnson counter results. The difference between a ring

output of the last stage is fed back (Q or Q'). Carefully compare the feedback connection below

to the previous ring counter.

This "reversed" feedback connection has a profou

similar circuits. Recirculating a single

equal to the number of stages. Whereas, a Johnson counter divides by a factor equal to twice the

number of stages. For example, a 4

divides by 8.

Start a Johnson counter by clearing all stages to

power-up time. Referring to the figure below, the first clock

the right into ( QB QC QD). The

we start shifting 1s to the right, replacing the

4-stage Johnson counter recirculates four

Explain Johnson Counter with neat diagram and timing diagram

(Dec’08)

, also know as the Johnson counter, overcomes some of the

. Like a ring counter a Johnson counter is a shift register fed back

on its' self. It requires half the stages of a comparable ring counter for a given division ratio. If

the complement output of a ring counter is fed back to the input instead of the true output, a

results. The difference between a ring counter and a Johnson


This "reversed" feedback connection has a profound effect upon the behavior of the otherwise

similar circuits. Recirculating a single 1 around a ring counter divides the input clock by a factor


ges. For example, a 4-stage ring counter divides by 4. A 4-stage Johnson counter

Start a Johnson counter by clearing all stages to 0s before the first clock. This is often done at

up time. Referring to the figure below, the first clock shifts three 0s from (

). The 1 at QD' (the complement of Q) is shifted back into

s to the right, replacing the 0s. Where a ring counter recirculated a single

stage Johnson counter recirculates four 0s then four 1s for an 8-bit pattern, then repeats.

10CS33

Page 28

Explain Johnson Counter with neat diagram and timing diagram

(Dec’08) & Dec’12

, overcomes some of the

is a shift register fed back

for a given division ratio. If

is fed back to the input instead of the true output, a

counter is which


nd effect upon the behavior of the otherwise

around a ring counter divides the input clock by a factor


stage Johnson counter

s before the first clock. This is often done at

s from ( QA QB QC) to

(the complement of Q) is shifted back into QA. Thus,

s. Where a ring counter recirculated a single 1, the

bit pattern, then repeats.

Logic Design

Dept. of CSE, SJBIT

4. Write verilog code for module shftreg (s1,s0,Pin,lfin,rtin,A,CLK,Clr);

input s1,s0; //Select inputs

input lfin, rtin; //Serial inputs

input CLK,Clr; //Clock and Clear

input [3:0] Pin; //Parallel input

output [3:0] A; //Register output

reg [3:0] A;

always @ (posedge CLK or negedge Clr)

if (~Clr) A = 4'b0000;

else

case ({s1,s0})

2'b00: A = A; //No change

2'b01: A = {rtin,A[3:1]}; //Shift right

2'b10: A = {A[2:0],lfin}; //Shift left

//Parallel load input

2'b11: A = Pin;

endcase

endmodule

Write verilog code for Shift Register. (jun’12) & Dec’12module shftreg (s1,s0,Pin,lfin,rtin,A,CLK,Clr);

input s1,s0; //Select inputs

n, rtin; //Serial inputs

input CLK,Clr; //Clock and Clear

input [3:0] Pin; //Parallel input

output [3:0] A; //Register output

always @ (posedge CLK or negedge Clr)

//No change

2'b01: A = {rtin,A[3:1]}; //Shift right

2'b10: A = {A[2:0],lfin}; //Shift left

10CS33

Page 29

& Dec’12

Logic Design 10CS33


Unit-6: Counters

1. Design a 3 bit synchronous counter with the help of D flip flop.

(Jan/10)

2. Design Mod 4 ring counter. (July’11)

� The output of LSB FF is connected as D input to MSB FF.

� This is commonly called as Ring Counter or Circular Counter.

� The data is shifted to right with each clock pulse.

� This counter has four different states.

� This can be extended to any no. of bits.

Logic Design 10CS33


3. Design Mod 8 Johnson Counter. (Jan’12)

� The complement output of LSB FF is connected as D input to MSB FF.

� This is commonly called as Johnson Counter.

� The data is shifted to right with each clock pulse.

� This counter has eight different states.

� This can be extended to any no. of bits.

4. Difference between Asynchronous and Synchronous Counter.

(Dec’11)

Asynchronous Counter Synchronous Counter

1. Clock input is applied to LSB FF. The output

of first FF is connected as clock to next FF.

1. Clock input is common to all FF.

2. All Flip-Flops are toggle FF. 2. Any FF can be used.

3. Speed depends on no. of FF used for n bit .

3. Speed is independent of no. of FF used.

4. No extra Logic Gates are required. 4. Logic Gates are required based on

design.

5. Cost is less. 5. Cost is more.

5. Draw logic circuit diagram for 3-bit synchronous up-down counter with clear

input, start input and ‘done’ output. The counter should produce ‘done’ output

Logic Design 10CS33


after completion of counter in either direction. Dec’12

Ans. 3-bit synchronous up-down counter:

5. Draw the logic circuits and the excitation tables for the T, JK flip-flops.

.

6. What is the difference between level and edge triggering? Explain the

working of master slave J-K flip flop. (Jan’12) & (Dec’12)

Logic Design 10CS33


Master slave JK flip-flop : The master slave flip-flop may be designed using R-S, D and JK flip-flops.

Following figure shows the functional block diagram of master slave JK flip- flop:

In figure m is used for Master and S is used for Slave

Working:

Case 1: When positive clock pulse goes on leading edge is applied, the CLKm is 1 and CLKs is 0, then

data transferred to Qm is held upto CLK = 1

Logic Design 10CS33


Case 2: When the clock pulse goes negative, trailing edge is applied, the CLKm = 0 and CLKs = 1, then

Qm and will be transferred to Q = and at that duration the inputs at J and K should not change

This is overcome by the use of data lockout.

Internal structures of master slave J-K flip-flop, Truth table is as shown in fig

Logic Design 10CS33


Unit-7: Design of Sequential Circuits

1. Difference between Mealy Model and Moore Model of Synchronous

Sequential Circuit. (Jun’10) Mealy Model : In Mealy Model the next state is function of external inputs and present state.

The output is also function of external inputs and present state. The memory state changes with

master clock.

Q+ = f(X,Q) Z = g(X,Q)

Moore Model : In Moore Model the next state is function of external inputs and present state.

But the output is function of present state. It is not dependent on external inputs. The no. of FFs

required to implement circuit is more compared with Mealy Model,

Q+ = f(X,Q) Z = g(Q)

2. Explain about all the notation of state machine. • Input Variables : External input variables to sequential machine as inputs.

• Output Variables : All variables that exit from the sequential machine are output

variables.

• State : State of sequential machine is defined by the content of memory, when memory is

realized by using FFs.

• Present State : The status of all state variable i.e. content of FF for given instant of time t

is called as present state.

• Next State : The state of memory at t+1 is called as Next state.

• State Diagram : State diagram is graphical representation of state variables represented by

circle. The connection between two states represented by lives with arrows and also

indicates the excitation input and related outputs.

• Output Variables : All variables that exit from the sequential machine are output

variables.

Q3. Analyse the following circuit. (Jun’12)

Logic Design

Dept. of CSE, SJBIT

The Excitation and Output Function

By substituting the FF inputs in characteristic equation, the next state of FF is obtained in

of PS of FF and external input.

The characteristic equation of JK FF is

The Excitation Table

PS

Q2 Q1

(y2 y1)

Excitation input

J2 K2 J1

K1

x=0, 1 x=0, 1

0 0 0 1 0 1

0 1 0 1 0 1

1 0 0 1 1

1 1 0 1 1

State Table

PS

x = 0

Q2

(y2)

Q1

(y1)

state Q2+ Q1+

0 0 A 0 0

0 1 B 0 0

1 0 C 0 1

1 1 D 0 1

12122

1212

, , , KyJxKxJ

yxyyyxZ

====

++=

The Excitation and Output Function

By substituting the FF inputs in characteristic equation, the next state of FF is obtained in

The characteristic equation of JK FF is

Excitation input

J2 K2 J1

Output Z

x=0, x=1

1 1

0 0

0 1 1

0 2 0

NS O/p Z

x = 0 x = 1

Q1+ state Q2+ Q1+ state X=0 X=1

0 A 1 0 C 1 1

0 A 1 0 C 0 0

1 B 1 1 D 1 1

1 B 1 1 D 1 0

2y=

QKQJQ +=+

22222

11111

QKQJQ

QKQJQ

=+=

=+=+

+

12

222

221221

,0

, ,

,

andyyzxWhen

yxZxKxJ

QyKQyJ

+==

+===

====

10CS33

Page 36

By substituting the FF inputs in characteristic equation, the next state of FF is obtained in terms

2

x

Q

=

=

1

112

,1 yzxWhenand

yxyy

==

+

Logic Design

Dept. of CSE, SJBIT

State Diagram of Mealy Network

Q4. Analyse the following Moore network.

A

D

C

0/1

0/0

1/0

1/1

0/1

1/1 1/0

Q1+ = Q2 = y2

Q2+ = x

21

221

21

12221

Q & 0,1

& ,0

,

DDxif

DQDxif

QQZ

QQxDQxD

===

==

+=

==

State Diagram of Mealy Network

Analyse the following Moore network.

B

0/0

0/1

1

12

,1

,0

yzxif

yyzxif

==

+==

A, B, C, D are

Present states.

21

12

211

Q

Q

Q

Q

QQx

=

+

10CS33

Page 37

(Dec’2010)

Logic Design 10CS33


State Table / Transition Table

State Diagram of Moore Network

4.For the given state diagram, draw the state reduction diagram.

(Jul’09) &Dec’12

State Diagram:

PS NS O/p Z

x = 0 x = 1

Q1 Q2 State Q1+ Q2+ State Q1+ Q2+ state

0 0 A 0 0 A 0 1 B 0

0 1 B 1 1 D 0 0 A 1

1 0 C 0 0 A 0 0 A 1

1 1 D 1 0 C 0 0 A 1

D 1

0

B 1

C 1

A 0 1

0

0

0

0 1

1

A, B, C, D are

Present states.

Logic Design 10CS33


Ans. State table is as shown:

For modified reduced state diagram:

Logic Design 10CS33


Unit -8: D/A conversion and A/D conversion

1. Give performance parameters of DAC or D/A converters. (Dec’10)

Ans. 1. Resolution : Resolution can be defined in two ways

(a) A DAC that can provide number of different analog output values is called resolution.

For a DAC having n-bits

Resolution .

(b) A DAC is which the ratio of change in output voltage resulting from a change of LSB (i.e. 1 least

significant bit) at the digital inputs is known as resolution.

Resolution for n-bit DAC is given by:

Input-output equation can also be obtained for DAC, if resolution is given

Where, Vo = Resolution x D

Vo = Output voltage

D = Decimal vã1ue of the digital input.

2. Accuracy: It is defined as the difference between the actual analog output and the expected analog

output when a given digital input is applied. It is expressed in percentage. In ideal case, the accuracy of

DAC should be, at worst, of its LSB.

3. Conversion Time or Setting Time: It is the time required for conversion of analog signal into its

digital equivalent. It is dependent on amplifiers output and switches response time.

4. Stability: When all the parameters such as gain, linearity error, monotonicity and offset must be

specified over the power supply ranges and full temperature then these parameters represent the stability

of the converter.

5. Monotonicity: If a converter does not miss any step backward during its entire range stepped by a

counter then it is said to have a counter having good monotonicity.

2. An 4 bit DIA converter has an output range of 0 to 1.5 V. Define its

resolution. (Jan’08) Ans. Given

n = 4 = number of bits

Logic Design 10CS33


Full scale output

1. Resolution:

Thus the output voltage can have 16 different values including zero.

2. Resolution:

Thus, an input change of 1 LSB changes the output by 100 mV.

Following fig. shows the D1A converter with op-amp. Calculate the output if the input digital signal

is 1110. Assume 1 binary = +5V.

Ans. Binary data:

B3 B2 B1 B0 1110

Let I1, I2 and I3 be the currents flowing through the respective resistors The value of currents are:

As, the op-amp has a very high input impedance. Thus, the currents I0 to I3 flow through 1K ohm

resistance.

3. Comment on the parameters which serve to describe the quality of

performance of a D/A converter. (Jun’12)

Logic Design 10CS33


Ans. There are basic three parameters which describe the quality of performance of D/A converter.

1. Resolution : It is the smallest possible change in the analog output voltage. Resolution should be as

high as possible.

2. Accuracy: It indicates how close the analog output voltage is to its theoretical value it is the deviation

of actual output from the theoretical value.

3. Linearity : The relation between the digital input and analog output should be linear.

4. With the help of a neat diagram explain parallel A/D converter.

(Jan’11) &Dec’12 Ans. Parallel A/D is used is much more due to its high speed. The only disadvantage is that its hardware

(no. of comparators) increase with the no. of bits. Va is analog, voltage and VR is reference’ voltage.

A 3-bit parallel-comparator AID converter is shown in fig. Va is the analog voltage is be converted into

digital form. The voltage corresponding to full scale is V from which the reference voltages VR1, VR2….

(See Fig.) are generated using the resistor network. The voltage Va is

compared simultaneously with the reference voltages by using comparators A 7-bit output obtained from

the comparators which is stored in latches This 7-bit digital signal is convert to a 3-bit output by using a

Logic Design 10CS33


decoder circuit The comparator outputs and the 3-bit digit output for each interval of the analog voltage

are given in Table (A)

The principle of parallel-comparator AID conversion is the simplest in concept and fasts Its main

disadvantages are rapid increase in the number of comparators with the number bits [

comparators are required for an N-bit converter] and the corresponding complications of the decoder

circuit

Table (A) Comparator outputs and digital output of parallel-comparator AID converter

5. Explain the operation of successive approximation type of ADC

(Dec’08) & Dec’12 Ans. Successive approximation is one of the most widely used popular method due its efficiency The

block diagram of SAR ADC s as shown:

Working: Initially, let us set the MSB bit of SAR register i.e. d1 = 1. It is applied to 4-bit D to A

converter i.e. as 1000. The D/A converter will generate its analog value and send to control logic The

output of control logic is VR. Now at the comparator, there are two inputs VR (Reference voltage) and

VA (Input analog).

If VR > VA ◊ output of comparator is low and bit d1 is reset correspondingly.

If VR <VA ◊ output of comparator is high and bit d1 remains high.

The same procedure is repeated for all bits i e for d2, d3,…. dn, and output may be taken in serial or

parallel manner.

Advantage: The conversion time is fixed as it does not depend upon amplitude of analog input.

Logic Design 10CS33


6. An 8-bit successive approximation converter (SAC) has a resolution of 15

mV What will its, digital output be for an analog input of 2.65 V ? Dec’12

Ans. Analog input = 2.65 V

Resolution = 15 mV

Now 176 would produce 2.64 V and 177 would produce 2.65 V. Hence VA = 2.65V The digital result

will be (176)10 = (10110000)2

7. Define linearity, settling time, sensitivity and accuracy of A/D and D/A

converters. Ans. For D/A converters

i. Linearity: The linearity of the converter specifies the accuracy with which the ideal performance is

followed Output of DIA converter must be each step up (down) in the digital input so as to cause an

increase (decrease) in the analog output The linearity should be at least equal to or better then

(ii) Setting Time: Whenever a digital input is applied to D/A converter, sometimes output sets to a value

within some specific limit of the final value The limit range is

LSB or less. This parameter tells the speed of D/A converter and t can be calculated by use o

switches, amplifier, resistors etc. in the device.

i. Accuracy: It is a measure of the difference between actual output and expected output. It is given as a

percentage of the maximum output voltage. If the maximum output voltage i.e. full scale deflection is 5V

and accuracy is then, the maximum error is x 5 = 0.0005 V or 5mV. Ideally the accuracy

should be better than 0.5 of LSB.

In an 8-bit converter LSB is or 0.39% of full scale. The accuracy should be better than

0.2%.

(iv) Sensitivity : Due to change in temperature the output of D/A converter should not change. But

practically the value of resistances and operational amplifier parameters change with variation in

temperature as analog output is a function of temperature. For AID converters

(i) Linearity: Linearity is basically a ‘best straight line’. Linearity of a converter directly determines

the relative accuracy of the converter. It is the difference of errors betweens the nominal and actual ratios

to the full scale analog value corresponding to a

Logic Design 10CS33


given digital input and independent of full scale calibration. The linearity error should be less

than

(ii) Conversion Time or Setting Time : It is the -time refers to the time requires for a complete

measurement by analog to digital converter.

OR

It is the time required for conversion of analog signal into its digital equivalent. It is dependent on the

amplifiers output and switches response time.

(iii) Accuracy : The accuracy of a given ADC i.e. analog to digital converter determines the number of

bits which can be usefully provided.

The accuracy of an ADC consists of quantization error system noise etc. Typical values are 0.02% of the

full scale reading.

(iv) Sensitivity : Due to change in temperature the output of AID converter should not change. But the

value of resistances and operational amplifier change with change in temperature.

8. Write note on the following Binary ladder D/A. converter. (Jun’09)

Ans Binary ladder D/A converter In a binary ladder D/A converter only two valued resistance R and 2R

are used as shown in diagram

Logic Design 10CS33


The OP amp is an inverting amplifier By solving resistance N/W in parallel and series, finally voltage at

node B is.

9. Explain the operation of dual-slope A/D converter. (Jan’09)

Ans. The dual slop A/D converter provide very much accuracy and so mostly used.

An analog input voltage is applied to Ramp Generator. The output of Ramp Generator app1ied to

comparator. The output of comparator is given to ‘AND’ gate. The second output ‘AND’ gate is clock

pulse. When input is high for AND gate clock pulse will be given to m-r. Counter is initially reset by

control logic. Now counter counts up and binary output in form is provided. When counter stops, switch

control again control the whole function.

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