CAD for IC Design :

QUADRATIC PLACEMENT

Introduction

• Output of High-level synthesis -> Boolean network model-> Technology Mapping => Netlist

• A Placer makes sure the gates are placed such that the router is able to connect all gates and meet timing requirements.

• Parameter to optimize is the estimated wirelength of the connected gates.

• Placer solves for gate locations to optimize the estimated wirelength.

Analytical placers

• Simulated Annealing Placement Algorithm – Not efficient for > Half million gates.

• All modern placers are analytical.

• Optimization problem needed in terms of Mathematical equations.

• Minima of the equation => Solution.

• Therefore, new wirelength model needed.

Quadratic Wirelength Model

Quadratic Wirelength = (x1-x2)2 + (y1-y2)2= (1-3)2 + (4-1)2 = 13

The squared distance between the connected gates.

Quadratic Wirelength Model For k-nets, replace one net with k(k-1)/2 2-point nets.

Quadratic Wirelength Model

• Need to assign weights to the new nets to compensate the wirelengths.

• Each new net given weight of 1/(k-1).

Quadratic Wirelength Model

K=4 (1/3)((1-3)2+(4-3)2) + (1/3)((1-3)2+(4-1)2) + (1/3)((1-4)2+(4-5)2) + (1/3)((3-4)2+(3-5)2) + (1/3)((3-3)2+(3-1)2) + (1/3)((3-4)2+(1-5)2) = Wirelength

Assumptions

• Gates are dimensionless points.

• Two or more gates can be placed at the same point.

• Solves the equations quickly and effectively.

• This assumption is repaired using a technique discussed in the end.

Example

2 Gates at (x1,y1) and (x2,y2), 3 nets with weights 1,2 and 4, 2 pads – fixed pins

Example

Quadratic Wirelength = Sum of the 3 wirelengths

Example

Q(x) = 4(x2-1)2 + 2(x2-x1)2 + 1(x1-0)2 and Q(y) = 4(y2-0.5)2 + 2(y2-y1)2 +1(y1-0)2 Minimize by taking Partial Derivative & equate to zero => 0 - 4(x2-x1) + 2x1 = 0 => 6x1 - 4x2 = 0 and 8(x2-1) + 4(x2-x1) + 0 = 0 => 12x2 – 4x1 - 8 = 0

Example

6x1 - 4x2 = 0 and 12x2 – 4x1 - 8 = 0 Similarly, 4y1 – 4y2 - 8 = 0 and -4y1 + 12y2 - 4 = 0 Solving these linear equations,

Example

Recursive Partitioning

Recursive Partitioning

Reference

• Prof. Rob A. Rutenbar , Lecture Slides “VLSI CAD : Logic to Layout ” – Coursera.