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Quad, 10-Bit, 40/65 MSPSSerial LVDS 1.8 V ADC
Data Sheet AD9219
Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved.
FEATURES 4 ADCs integrated into 1 package 94 mW ADC power per channel at 65 MSPS SNR = 60 dB (to Nyquist) ENOB = 9.7 bits SFDR = 78 dBc (to Nyquist) Excellent linearity
DNL = ±0.2 LSB (typical) INL = ±0.3 LSB (typical)
Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs 315 MHz full-power analog bandwidth 2 V p-p input voltage range 1.8 V supply operation Serial port control
Full-chip and individual-channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Programmable clock and data alignment Programmable output resolution Standby mode
APPLICATIONS Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment
GENERAL DESCRIPTION
The AD9219 is a quad, 10-bit, 40/65 MSPS analog-to-digital con-verter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 65 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.
FUNCTIONAL BLOCK DIAGRAM
SERIALLVDS
REFSELECT
+–
AD9219
AGND
VIN – A
VIN + A
VIN – B
VIN + B
VIN – D
VIN + D
VIN – C
VIN + C
SENSE
VREF
AVDD DRVDD
10
10
10
10
PDWN
REFTREFB
D – AD + A
D – BD + B
D – DD + D
D – CD + C
FCO–
FCO+
DCO+DCO–
CLK+
DRGND
CLK–
SERIAL PORTINTERFACE
CSB SCLK/DTPSDIO/ODMRBIAS
SERIALLVDS
SERIALLVDS
SERIALLVDS
PIPELINEADC
PIPELINEADC
PIPELINEADC
PIPELINEADC
DATA RATEMULTIPLIER
0.5V
0572
6-00
1
Figure 1.
The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.
The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).
The AD9219 is available in an RoHS compliant, 48-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Small Footprint. Four ADCs are contained in a small, space-saving package.
2. Low power of 94 mW/channel at 65 MSPS. 3. Ease of Use. A data clock output (DCO) is provided that
operates at frequencies of up to 390 MHz and supports double data rate (DDR) operation.
4. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements.
5. Pin-Compatible Family. This includes the AD9287 (8-bit), AD9228 (12-bit), and AD9259 (14-bit).
AD9219* Product Page Quick LinksLast Content Update: 11/01/2016
Comparable PartsView a parametric search of comparable parts
Evaluation Kits• AD9219 Evaluation Board
DocumentationApplication Notes• AN-1142: Techniques for High Speed ADC PCB Layout• AN-282: Fundamentals of Sampled Data Systems• AN-345: Grounding for Low-and-High-Frequency Circuits• AN-501: Aperture Uncertainty and ADC System
Performance• AN-586: LVDS Outputs for High Speed A/D Converters• AN-715: A First Approach to IBIS Models: What They Are
and How They Are Generated• AN-737: How ADIsimADC Models an ADC• AN-741: Little Known Characteristics of Phase Noise• AN-756: Sampled Systems and the Effects of Clock Phase
Noise and Jitter• AN-812: MicroController-Based Serial Port Interface (SPI)
Boot Circuit• AN-827: A Resonant Approach to Interfacing Amplifiers to
Switched-Capacitor ADCs• AN-835: Understanding High Speed ADC Testing and
Evaluation• AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual• AN-935: Designing an ADC Transformer-Coupled Front
EndData Sheet• AD9219: Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V
ADC Data Sheet
Tools and Simulations• Visual Analog• AD9219 IBIS Model
Reference MaterialsTechnical Articles• Matching An ADC To A Transformer• MS-2210: Designing Power Supplies for High Speed ADC
Design Resources• AD9219 Material Declaration• PCN-PDN Information• Quality And Reliability• Symbols and Footprints
DiscussionsView all AD9219 EngineerZone Discussions
Sample and BuyVisit the product page to see pricing options
Technical SupportSubmit a technical question or find your regional support number
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. This content may be frequently modified.
AD9219 Data Sheet
Rev. E | Page 2 of 56
TABLE OF CONTENTS Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 4
AC Specifications .......................................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
Timing Diagrams .............................................................................. 8
Absolute Maximum Ratings .......................................................... 10
Thermal Impedance ................................................................... 10
ESD Caution ................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Equivalent Circuits ......................................................................... 13
Typical Performance Characteristics ........................................... 15
Theory of Operation ...................................................................... 20
Analog Input Considerations ................................................... 20
Clock Input Considerations ...................................................... 23
Serial Port Interface (SPI) .............................................................. 31
Hardware Interface ..................................................................... 31
Memory Map .................................................................................. 33
Reading the Memory Map Table .............................................. 33
Reserved Locations .................................................................... 33
Default Values ............................................................................. 33
Logic Levels ................................................................................. 33
Evaluation Board ............................................................................ 37
Power Supplies ............................................................................ 37
Input Signals................................................................................ 37
Output Signals ............................................................................ 37
Default Operation and Jumper Selection Settings ................. 38
Alternative Analog Input Drive Configuration...................... 39
Outline Dimensions ....................................................................... 53
Ordering Guide .......................................................................... 53
REVISION HISTORY 12/11—Rev. D to Rev. E Added Exposed Pad Notation to Figure 5 ................................... 11 Changes to Output Signals Section and Figure 71 ..................... 37 Change to Default Operation and Jumper Selection Settings Section .............................................................................................. 38 Change to Figure 74 ....................................................................... 41 Changed LFCSP_WQ to LFCSP_VQ Throughout .................... 53 Added Endnote 2 in Ordering Guide .......................................... 53 5/10—Rev. C to Rev. D Updated Outline Dimensions ....................................................... 52 Changes to Ordering Guide .......................................................... 52 4/10—Rev. B to Rev. C Changes to Table 16 ........................................................................ 33 Updated Outline Dimensions ....................................................... 52 7/07—Rev. A to Rev. B Changes to Figure 2 and Figure 4 ................................................... 7 Changes to Table 17 ........................................................................ 50
5/07—Rev. 0 to Rev. A Changes to Features .......................................................................... 1 Changes to Logic Output (SDIO/ODM) Section .......................... 5 Added Endnote 3 to Table 3 ............................................................. 5 Changes to Pipeline Latency ............................................................ 6 Changes to Figure 2 to Figure 4 ....................................................... 7 Changes to Figure 10 ...................................................................... 12 Changes to Figure 15, Figure 23 to Figure 26 Captions ............ 14 Changes to Figure 16, Figure 37, Figure 39, and Figure 40....... 14 Added Figure 46 and Figure 47 .................................................... 20 Change to Figure 50 ....................................................................... 21 Changes to Figure 51 ...................................................................... 21 Changes to Clock Duty Cycle Considerations Section ............. 22 Changes to Power Dissipation and Power-Down Mode Section .......................................................... 23 Changes to Figure 58 ...................................................................... 23 Changes to Figure 61 to Figure 63 Captions ............................... 25 Change to Table 8 ........................................................................... 25 Changes to Digital Outputs and Timing Section ....................... 26 Changes to Table 9 Endnote .......................................................... 26 Added Table 10 ............................................................................... 27 Deleted Figure 62 and Figure 63 .................................................. 27
Data Sheet AD9219
Rev. E | Page 3 of 56
Changes to RBIAS Pin Section ...................................................... 28 Changes to Figure 67 ...................................................................... 29 Changes to Hardware Interface Section ....................................... 30 Added Figure 68 .............................................................................. 31 Changes to Table 15 ........................................................................ 31 Changes to Reading the Memory Map Table Section ................ 32 Changes to Output Signals Section ............................................... 36 Changes to Figure 71 ...................................................................... 36 Changes to Default Operation and
Jumper Selection Settings Section ................................................ 37 Changes to Alternative Analog Input Drive Configuration Section .............................................................................................. 38 Changes to Figure 74 ...................................................................... 40 Changes to Table 17 ........................................................................ 48 Changes to Ordering Guide ........................................................... 52 4/06—Revision 0: Initial Version
AD9219 Data Sheet
Rev. E | Page 4 of 56
SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 1. AD9219-40 AD9219-65 Parameter1 Temperature Min Typ Max Min Typ Max Unit RESOLUTION 10 10 Bits ACCURACY
No Missing Codes Full Guaranteed Guaranteed Offset Error Full ±1 ±8 ±1 ±8 mV Offset Matching Full ±2 ±8 ±2 ±8 mV Gain Error Full ±0.4 ±1.2 ±2 ±3.5 % FS Gain Matching Full ±0.3 ±0.7 ±0.3 ±0.7 % FS Differential Nonlinearity (DNL) Full ±0.1 ±0.4 ±0.15 ±0.4 LSB Integral Nonlinearity (INL) Full ±0.15 ±0.4 ±0.3 ±0.75 LSB
TEMPERATURE DRIFT Offset Error Full ±2 ±2 ppm/°C Gain Error Full ±17 ±17 ppm/°C Reference Voltage (1 V Mode) Full ±21 ±21 ppm/°C
REFERENCE Output Voltage Error (VREF = 1 V) Full ±2 ±30 ±2 ±30 mV Load Regulation at 1.0 mA (VREF = 1 V) Full 3 3 mV Input Resistance Full 6 6 kΩ
ANALOG INPUTS Differential Input Voltage (VREF = 1 V) Full 2 2 V p-p Common-Mode Voltage Full AVDD/2 AVDD/2 V Differential Input Capacitance Full 7 7 pF Analog Bandwidth, Full Power Full 315 315 MHz
POWER SUPPLY AVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V IAVDD Full 130 142 177 190 mA IDRVDD Full 30 32 33 37 mA Total Power Dissipation (Including Output Drivers) Full 295 313 378 408 mW Power-Down Dissipation Full 2 5.8 2 5.8 mW Standby Dissipation2 Full 72 72 mW
CROSSTALK Full −100 −100 dB CROSSTALK (Overrange Condition)3 Full −100 −100 dB 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details of how these tests were completed. 2 Can be controlled via the SPI. 3 Overrange condition is specific with 6 dB of the full-scale input range.
Data Sheet AD9219
Rev. E | Page 5 of 56
AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 2. AD9219-40 AD9219-65 Parameter1 Temperature Min Typ Max Min Typ Max Unit SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz Full 61.2 60.2 dB fIN = 19.7 MHz Full 60.0 60.5 60.2 dB fIN = 35 MHz Full 61.0 59.0 60.2 dB fIN = 70 MHz Full 60.9 60.1 dB
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fIN = 2.4 MHz Full 61.1 60.1 dB fIN = 19.7 MHz Full 59.8 60.3 60.1 dB fIN = 35 MHz Full 60.9 58.8 60.0 dB fIN = 70 MHz Full 60.8 59.8 dB
EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz Full 9.87 9.71 Bits fIN = 19.7 MHz Full 9.67 9.76 9.71 Bits fIN = 35 MHz Full 9.84 9.51 9.71 Bits fIN = 70 MHz Full 9.82 9.69 Bits
SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz Full 84 78 dBc fIN = 19.7 MHz Full 71 82 78 dBc fIN = 35 MHz Full 80 68 77 dBc fIN = 70 MHz Full 79 72 dBc
WORST HARMONIC (Second or Third) fIN = 2.4 MHz Full −84 −80 dBc fIN = 19.7 MHz Full −82 −71 −80 dBc fIN = 35 MHz Full −80 −77 −68 dBc fIN = 70 MHz Full −79 −72 dBc
WORST OTHER (Excluding Second or Third) fIN = 2.4 MHz Full −90 −78 dBc fIN = 19.7 MHz Full −90 −77 −78 dBc fIN = 35 MHz Full −90 −80 −70 dBc fIN = 70 MHz Full −88 −80 dBc
TWO-TONE INTERMODULATION DISTORTION (IMD)— AIN1 and AIN2 = −7.0 dBFS
fIN1 = 15 MHz, fIN2 = 16 MHz 25°C 81.5 78.1 dBc fIN1 = 70 MHz, fIN2 = 71 MHz 25°C 79.5 74.5 dBc
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details of how these tests were completed.
AD9219 Data Sheet
Rev. E | Page 6 of 56
DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 3. AD9219-40 AD9219-65 Parameter1 Temperature Min Typ Max Min Typ Max Unit CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL Differential Input Voltage2 Full 250 250 mV p-p Input Common-Mode Voltage Full 1.2 1.2 V Input Resistance (Differential) 25°C 20 20 kΩ Input Capacitance 25°C 1.5 1.5 pF
LOGIC INPUTS (PDWN, SCLK/DTP) Logic 1 Voltage Full 1.2 3.6 1.2 3.6 V Logic 0 Voltage Full 0 0.3 0.3 V Input Resistance 25°C 30 30 kΩ Input Capacitance 25°C 0.5 0.5 pF
LOGIC INPUT (CSB) Logic 1 Voltage Full 1.2 3.6 1.2 3.6 V Logic 0 Voltage Full 0 0.3 0.3 V Input Resistance 25°C 70 70 kΩ Input Capacitance 25°C 0.5 0.5 pF
LOGIC INPUT (SDIO/ODM) Logic 1 Voltage Full 1.2 DRVDD + 0.3 1.2 DRVDD + 0.3 V Logic 0 Voltage Full 0 0.3 0 0.3 V Input Resistance 25°C 30 30 kΩ Input Capacitance 25°C 2 2 pF
LOGIC OUTPUT (SDIO/ODM)3 Logic 1 Voltage (IOH = 800 μA) Full 1.79 1.79 V Logic 0 Voltage (IOL = 50 μA) Full 0.05 0.05 V
DIGITAL OUTPUTS (D + x, D − x), (ANSI-644) Logic Compliance LVDS LVDS Differential Output Voltage (VOD) Full 247 454 247 454 mV Output Offset Voltage (VOS) Full 1.125 1.375 1.125 1.375 V Output Coding (Default) Offset binary Offset binary
DIGITAL OUTPUTS (D + x, D − x), (Low Power, Reduced Signal Option)
Logic Compliance LVDS LVDS Differential Output Voltage (VOD) Full 150 250 150 250 mV Output Offset Voltage (VOS) Full 1.10 1.30 1.10 1.30 V Output Coding (Default) Offset binary Offset binary
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details of how these tests were completed. 2 This is specified for LVDS and LVPECL only. 3 This is specified for 13 SDIO pins sharing the same connection.
Data Sheet AD9219
Rev. E | Page 7 of 56
SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4. AD9219-40 AD9219-65
Parameter1, 2 Temp Min Typ Max Min Typ Max Unit
CLOCK3 Maximum Clock Rate Full 40 65 MSPS Minimum Clock Rate Full 10 10 MSPS Clock Pulse Width High (tEH) Full 12.5 7.7 ns Clock Pulse Width Low (tEL) Full 12.5 7.7 ns
OUTPUT PARAMETERS3
Propagation Delay (tPD) Full 2.0 2.5 3.5 2.0 2.5 3.5 ns Rise Time (tR) (20% to 80%) Full 300 300 ps Fall Time (tF) (20% to 80%) Full 300 300 ps FCO Propagation Delay (tFCO) Full 2.0 2.5 3.5 2.0 2.5 3.5 ns DCO Propagation Delay (tCPD)4 Full tFCO +
(tSAMPLE/20) tFCO +
(tSAMPLE/20) ns
DCO to Data Delay (tDATA)4 Full (tSAMPLE/20) − 300 (tSAMPLE/20) (tSAMPLE/20) + 300 (tSAMPLE/20) − 300 (tSAMPLE/20) (tSAMPLE/20) + 300 ps
DCO to FCO Delay (tFRAME)4 Full (tSAMPLE/20) − 300 (tSAMPLE/20) (tSAMPLE/20) + 300 (tSAMPLE/20) − 300 (tSAMPLE/20) (tSAMPLE/20) + 300 ps
Data to Data Skew (tDATA-MAX − tDATA-MIN)
Full ±50 ±150 ±50 ±150 ps
Wake-Up Time (Standby) 25°C 600 600 ns Wake-Up Time (Power-Down) 25°C 375 375 μs Pipeline Latency Full 8 8 CLK
cycles
APERTURE Aperture Delay (tA) 25°C 500 500 ps Aperture Uncertainty (Jitter) 25°C <1 <1 ps rms Out-of-Range Recovery Time 25°C 1 2 CLK
cycles 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details of how these tests were completed. 2 Measured on standard FR-4 material. 3 Can be adjusted via the SPI. 4 tSAMPLE/20 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
AD9219 Data Sheet
Rev. E | Page 8 of 56
TIMING DIAGRAMS
DCO+
DCO–
CLK+
FCO+
FCO–
D – x
D + x
CLK–
VIN ± x
MSBN – 9
N – 1
N
D8N – 9
D7N – 9
D5N – 9
tDATA
tFRAMEtFCO
tPD
D4N – 9
D6N – 9
D8N – 8
D7N – 8
D5N – 8
D6N – 8
D3N – 9
D1N – 9
MSBN – 8
D0N – 9
D2N – 9
tCPD
tEH
tA
tEL
0572
6-04
0
Figure 2. 10-Bit Data Serial Stream, MSB First (Default)
DCO–
DCO+
D – x
D + x
FCO–
FCO+
VIN ± x
CLK–
CLK+
MSBN – 9
D10N – 9
D9N – 9
D8N – 9
D7N – 9
D6N – 9
D5N – 9
D4N – 9
D3N – 9
D2N – 9
D1N – 9
D0N – 9
D10N – 8
MSBN – 8
0572
6-03
9
N – 1
N
tDATA
tFRAMEtFCO
tPD
tCPD
tEH
tA
tEL
Figure 3. 12-Bit Data Serial Stream, MSB First
Data Sheet AD9219
Rev. E | Page 9 of 56
DCO–
DCO+
D – x
D + x
FCO–
FCO+
VIN ± x
CLK–
CLK+
LSBN – 9
D0N – 9
D1N – 9
D2N – 9
D3N – 9
D4N – 9
D5N – 9
D6N – 9
D7N – 9
D8N – 9
LSBN – 8
D0N – 8
D2N – 8
D1N – 8
N – 1
tA
N
tDATA
tFRAMEtFCO
tPD
tCPD
tEH tEL
0572
6-04
1
Figure 4. 10-Bit Stream, LSB First
AD9219 Data Sheet
Rev. E | Page 10 of 56
ABSOLUTE MAXIMUM RATINGS Table 5.
Parameter With Respect To Rating
ELECTRICAL AVDD AGND −0.3 V to +2.0 V DRVDD DRGND −0.3 V to +2.0 V AGND DRGND −0.3 V to +0.3 V AVDD DRVDD −2.0 V to +2.0 V Digital Outputs
(D + x, D − x, DCO+, DCO−, FCO+, FCO−)
DRGND −0.3 V to +2.0 V
CLK+, CLK− AGND −0.3 V to +3.9 V VIN + x, VIN − x AGND −0.3 V to +2.0 V SDIO/ODM AGND −0.3 V to +2.0 V PDWN, SCLK/DTP, CSB AGND −0.3 V to +3.9 V REFT, REFB, RBIAS AGND −0.3 V to +2.0 V VREF, SENSE AGND −0.3 V to +2.0 V
ENVIRONMENTAL Operating Temperature
Range (Ambient) −40°C to +85°C
Maximum Junction Temperature
150°C
Lead Temperature (Soldering, 10 sec)
300°C
Storage Temperature Range (Ambient)
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL IMPEDANCE
Table 6. Air Flow Velocity (m/sec) θJA
1 θJB θJC Unit 0.0 24 °C/W 1.0 21 12.6 1.2 °C/W 2.5 19 °C/W 1 θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad
soldered to PCB.
ESD CAUTION
Data Sheet AD9219
Rev. E | Page 11 of 56
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VIN + A
VIN – A
AVDD
VIN + D
VIN – D
DRVDD
DRGND
CLK+
CLK–
AVDD
DRVDD
DRGND
AVDD
AVDD
CSB
SCLK/DTP
SDIO/ODM
PDWN
AVDD
AVDD
AVDD
AVDD
AVDDAVDD
D +
A
D –
A
D +
B
D –
B
D +
C
D –
C
D +
D
D –
D
DC
O+
DC
O–
FC
O+
FC
O–
VIN
+ B
VIN
– B
VIN
+ C
VIN
– C
AV
DD
RE
FT
RE
FB
VR
EF
SE
NS
E
AV
DD
AV
DD
RB
IAS
11
12
10
9
8
7
6
5
4
3
2
1
25
24
26
27
28
29
30
31
32
33
34
35
36
2221 232019181716151413
373839404142434445464748
PIN 1INDICATOR
EXPOSED PADDLE, PIN 0(BOTTOM OF PACKAGE)
AD9219TOP VIEW
0572
6-00
3
NOTES1. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.
Figure 5. 48-Lead LFCSP Pin Configuration, Top View
Table 7. Pin Function Descriptions Pin No. Mnemonic Description 0 AGND Analog Ground (Exposed Paddle) 1, 2, 5, 6, 9, 10, 27, 32, 35, 36, 39, 45, 46
AVDD 1.8 V Analog Supply
11, 26 DRGND Digital Output Driver Ground 12, 25 DRVDD 1.8 V Digital Output Driver Supply 3 VIN − D ADC D Analog Input Complement 4 VIN + D ADC D Analog Input True 7 CLK− Input Clock Complement 8 CLK+ Input Clock True 13 D − D ADC D Digital Output Complement 14 D + D ADC D Digital Output True 15 D − C ADC C Digital Output Complement 16 D + C ADC C Digital Output True 17 D − B ADC B Digital Output Complement 18 D + B ADC B Digital Output True 19 D − A ADC A Digital Output Complement 20 D + A ADC A Digital Output True 21 FCO− Frame Clock Output Complement 22 FCO+ Frame Clock Output True 23 DCO− Data Clock Output Complement 24 DCO+ Data Clock Output True 28 SCLK/DTP Serial Clock/Digital Test Pattern 29 SDIO/ODM Serial Data IO/Output Driver Mode
AD9219 Data Sheet
Rev. E | Page 12 of 56
Pin No. Mnemonic Description 30 CSB Chip Select Bar 31 PDWN Power-Down 33 VIN + A ADC A Analog Input True 34 VIN − A ADC A Analog Input Complement 37 VIN − B ADC B Analog Input Complement 38 VIN + B ADC B Analog Input True 40 RBIAS External resistor sets the internal ADC core bias current 41 SENSE Reference Mode Selection 42 VREF Voltage Reference Input/Output 43 REFB Differential Reference (Negative) 44 REFT Differential Reference (Positive) 47 VIN + C ADC C Analog Input True 48 VIN − C ADC C Analog Input Complement
Data Sheet AD9219
Rev. E | Page 13 of 56
EQUIVALENT CIRCUITS
VIN ± x
0572
6-03
0
Figure 6. Equivalent Analog Input Circuit
10Ω
10kΩ
10kΩ
CLK–10Ω
1.25V
CLK+
0572
6-03
2
Figure 7. Equivalent Clock Input Circuit
SDIO/ODM350Ω
30kΩ
0572
6-03
5
Figure 8. Equivalent SDIO/ODM Input Circuit
DRVDD
DRGND
D– D+
V
V
V
V
0572
6-00
5
Figure 9. Equivalent Digital Output Circuit
SCLK/DTPAND PDWN
30kΩ
1kΩ
0572
6-03
3
Figure 10. Equivalent SCLK/DTP and PDWN Input Circuit
100ΩRBIAS
0572
6-03
1
Figure 11. Equivalent RBIAS Circuit
AD9219 Data Sheet
Rev. E | Page 14 of 56
CSB
70kΩ1kΩ
AVDD
0572
6-03
4
Figure 12. Equivalent CSB Input Circuit
SENSE1kΩ
0572
6-03
6
Figure 13. Equivalent SENSE Circuit
VREF
6kΩ
0572
6-03
7
Figure 14. Equivalent VREF Circuit
Data Sheet AD9219
Rev. E | Page 15 of 56
TYPICAL PERFORMANCE CHARACTERISTICS 0
–40
–20
–60
–80
–100
–1200 2 4 6 8 10 12 14 16 18 20
0572
6-05
6
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
AIN = –0.5dBFSSNR = 61.22dB
ENOB = 9.88 BITSSFDR = 85.20dBc
Figure 15. Single-Tone 32k FFT with fIN = 2.4 MHz, fSAMPLE = 40 MSPS
0
–40
–20
–60
–80
–100
–1200 2 4 6 8 10 12 14 16 18 20
0572
6-07
6
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
AIN = –0.5dBFSSNR = 59.87dB
ENOB = 9.65 BITSSFDR = 81.68dBc
Figure 16. Single-Tone 32k FFT with fIN = 35 MHz, fSAMPLE = 40 MSPS
0
–40
–20
–60
–80
–100
–1200 305 20 251510
0572
6-05
7
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
AIN = –0.5dBFSSNR = 59.93dB
ENOB = 9.66 BITSSFDR = 77.58dBc
Figure 17. Single-Tone 32k FFT with fIN = 2.3 MHz, fSAMPLE = 65 MSPS
0
–40
–20
–60
–80
–100
–1200 305 20 251510
0572
6-05
8
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
AIN = –0.5dBFSSNR = 59.81dB
ENOB = 9.64 BITSSFDR = 70.02dBc
Figure 18. Single-Tone 32k FFT with fIN = 70 MHz, fSAMPLE = 65 MSPS
0
–40
–20
–60
–80
–100
–1200 305 20 251510
0572
6-05
9
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
AIN = –0.5dBFSSNR = 59.68dB
ENOB = 9.62 BITSSFDR = 70.86dBc
Figure 19. Single-Tone 32k FFT with fIN = 120 MHz, fSAMPLE = 65 MSPS
0
–40
–20
–60
–80
–100
–1200 305 20 251510
0572
6-05
3
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
AIN = –0.5dBFSSNR = 59.93dBENOB = 9.66 BITSSFDR = 63.51dBc
Figure 20. Single-Tone 32k FFT with fIN = 170 MHz, fSAMPLE = 65 MSPS
AD9219 Data Sheet
Rev. E | Page 16 of 56
0
–40
–20
–60
–80
–100
–1200 305 20 251510
0572
6-05
4
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
AIN = –0.5dBFSSNR = 56.72dB
ENOB = 9.13 BITSSFDR = 66.41dBc
Figure 21. Single-Tone 32k FFT with fIN = 190 MHz, fSAMPLE = 65 MSPS
0
–40
–20
–60
–80
–100
–1200 305 20 251510
0572
6-05
5
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
AIN = –0.5dBFSSNR = 58.57dB
ENOB = 9.44 BITSSFDR = 57.95dBc
Figure 22. Single-Tone 32k FFT with fIN = 250 MHz, fSAMPLE = 65 MSPS
90
70
75
85
80
65
60
55
5010 4015 30 352520
0572
6-06
0
SN
R/S
FD
R (
dB
)
ENCODE (MSPS)
2V p-p, SNR
2V p-p, SFDR
Figure 23. SNR/SFDR vs. Encode, fIN = 10.3 MHz, fSAMPLE = 40 MSPS
90
70
75
85
80
65
60
55
5010 4015 30 352520
0572
6-06
3
SN
R/S
FD
R (
dB
)
ENCODE (MSPS)
2V p-p, SNR
2V p-p, SFDR
Figure 24. SNR/SFDR vs. Encode, fIN = 35 MHz, fSAMPLE = 40 MSPS
90
70
75
85
80
65
60
55
5010 6040 503020
0572
6-06
1
SN
R/S
FD
R (
dB
)
ENCODE (MSPS)
2V p-p, SNR
2V p-p, SFDR
Figure 25. SNR/SFDR vs. Encode, fIN = 10.3 MHz, fSAMPLE = 65 MSPS
90
70
75
85
80
65
60
55
5010 50 603020 40
0572
6-06
5
SN
R/S
FD
R (
dB
)
ENCODE (MSPS)
2V p-p, SNR
2V p-p, SFDR
Figure 26. SNR/SFDR vs. Encode, fIN = 35 MHz, fSAMPLE = 65 MSPS
Data Sheet AD9219
Rev. E | Page 17 of 56
–60 –10 0–40–50 –30 –20
0572
6-06
2
SN
R/S
FD
R (
dB
)
ANALOG INPUT LEVEL (dBFS)
fIN = 10.3MHzfSAMPLE = 40MSPS
2V p-p, SFDR
2V p-p, SNR
70dB REFERENCE
100
70
90
80
60
0
50
40
30
20
10
Figure 27. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, fSAMPLE = 40 MSPS
–60 –10 0–40–50 –30 –20
0572
6-06
6
SN
R/S
FD
R (
dB
)
ANALOG INPUT LEVEL (dBFS)
fIN = 35MHzfSAMPLE = 40MSPS
2V p-p, SFDR
2V p-p, SNR
70dB REFERENCE
100
70
90
80
60
0
50
40
30
20
10
Figure 28. SNR/SFDR vs. Analog Input Level, fIN = 35 MHz, fSAMPLE = 40 MSPS
100
70
90
80
60
0
50
40
30
20
10
–60 –10 0–40–50 –30 –20
0572
6-06
4
SN
R/S
FD
R (
dB
)
ANALOG INPUT LEVEL (dBFS)
fIN = 10.3MHzfSAMPLE = 65MSPS
2V p-p, SFDR
2V p-p, SNR
70dB REFERENCE
Figure 29. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, fSAMPLE = 65 MSPS
–60 –10 0–40–50 –30 –20
0572
6-06
7
SN
R/S
FD
R (
dB
)
ANALOG INPUT LEVEL (dBFS)
fIN = 35MHzfSAMPLE = 65MSPS
2V p-p, SFDR
2V p-p, SNR
70dB REFERENCE
100
70
90
80
60
0
50
40
30
20
10
Figure 30. SNR/SFDR vs. Analog Input Level, fIN = 35 MHz, fSAMPLE = 65 MSPS
0
–40
–20
–60
–80
–100
–1200 2 4 6 8 10 12 14 16 18 20
0572
6-04
8
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
AIN1 AND AIN2 = –7dBFSSFDR = 82.54dBcIMD2 = 88.33dBcIMD3 = 81.77dBc
Figure 31. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz, fSAMPLE = 40 MSPS
0
–40
–20
–60
–80
–100
–1200 2 4 6 8 10 12 14 16 18 20
0572
6-04
9
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
AIN1 AND AIN2 = –7dBFSSFDR = 79.13dBcIMD2 = 79.56dBcIMD3 = 79.66dBc
Figure 32. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz, fSAMPLE = 40 MSPS
AD9219 Data Sheet
Rev. E | Page 18 of 56
0
–40
–20
–60
–80
–100
–1200 305 20 251510
0572
6-05
0
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
AIN1 AND AIN2 = –7dBFSSFDR = 78.53dBcIMD2 = 78.61dBcIMD3 = 78.17dBc
Figure 33. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz, fSAMPLE = 65 MSPS
0
–40
–20
–60
–80
–100
–1200 305 20 251510
0572
6-05
2
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
AIN1 AND AIN2 = –7dBFSSFDR = 74.90dBcIMD2 = 83.52dBcIMD3 = 74.56dBc
Figure 34. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz, fSAMPLE = 65 MSPS
1 100010 100
0572
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8
SN
R/S
FD
R (
dB
)
ANALOG INPUT FREQUENCY (MHz)
80
70
75
65
50
60
55
2V p-p, SNR
2V p-p, SFDR
Figure 35. SNR/SFDR vs. Analog Input Frequency, fSAMPLE = 65 MSPS
0572
6-06
9
SIN
AD
/SF
DR
(d
B)
TEMPERATURE (°C)
2V p-p, SINAD
2V p-p, SFDR
90
70
75
85
80
65
60
55
504020–20 0 8060–40
Figure 36. SINAD/SFDR vs. Temperature, fIN = 10.3 MHz, fSAMPLE = 65 MSPS
1.0
–1.00 1000800600400200
CODE
INL
(L
SB
)
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
0572
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0
Figure 37. INL, fIN = 2.4 MHz, fSAMPLE = 65 MSPS
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0 200 400 600 800 1000
DN
L (
LS
B)
CODES
0572
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Figure 38. DNL, fIN = 2.4 MHz, fSAMPLE = 65 MSPS
Data Sheet AD9219
Rev. E | Page 19 of 56
–45.0
–46.0
–45.5
–46.5
–47.0
–47.5
–48.010 15 20 25 35 4530 40 50
CM
RR
(d
B)
FREQUENCY (MHz)
0572
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2
Figure 39. CMRR vs. Frequency, fSAMPLE = 65 MSPS
NU
MB
ER
OF
HIT
S (
Mil
lio
ns)
0.2
0.4
0.6
0.8
1.0
1.2
0N – 3 N – 2 N + 3N + 2N + 1NN – 1
CODE
0 LSB rms
0572
6-08
0
Figure 40. Input-Referred Noise Histogram, fSAMPLE = 65 MSPS
0
–40
–20
–60
–80
–100
–1200 305 20 251510
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1
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
NPR = 51.72dBNOTCH = 18.0MHz
NOTCH WIDTH = 3.0MHz
Figure 41. Noise Power Ratio (NPR), fSAMPLE = 65 MSPS
FU
ND
AM
EN
TA
L L
EV
EL
(d
B)
0572
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4
–10
0
–3
–2
–1
–4
–5
–6
–7
–8
–9
0 50 100 150 200 250 300 350 400 450 500
FREQUENCY (MHz)
–3dB CUTOFF = 315MHz
Figure 42. Full-Power Bandwidth vs. Frequency, fSAMPLE = 65 MSPS
AD9219 Data Sheet
Rev. E | Page 20 of 56
THEORY OF OPERATION The AD9219 architecture consists of a pipelined ADC divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The quantized outputs from each stage are combined into a final 10-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and an interstage residue amplifier (for example, a multiplying digital-to-analog converter (MDAC)). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC.
The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The data is then serialized and aligned to the frame and data clocks.
ANALOG INPUT CONSIDERATIONS The analog input to the AD9219 is a differential switched-capacitor circuit designed for processing differential input signals. This circuit can support a wide common-mode range while maintaining excellent performance. By using an input common-mode voltage of midsupply, users can minimize signal-dependent errors and achieve optimum performance.
S S
HCPAR
CSAMPLE
CSAMPLE
CPAR
VIN – x
H
S S
HVIN + x
H
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6
Figure 43. Switched-Capacitor Input Circuit
The clock signal alternately switches the input circuit between sample mode and hold mode (see Figure 43). When the input circuit is switched to sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. In addition, low-Q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and therefore achieve the maximum bandwidth of the ADC. Such use of low-Q inductors or ferrite beads is required when driving the converter front end at high IF frequencies. Either a shunt capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input to limit unwanted broadband noise. See the AN-742 Application Note, the AN-827 Application Note, and the Analog Dialogue article “Transformer-Coupled Front-End for Wideband A/D Converters” (Volume 39, April 2005) for more information at www.analog.com. In general, the precise values depend on the application.
The analog inputs of the AD9219 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 44 to Figure 47.
Data Sheet AD9219
Rev. E | Page 21 of 56
40
45
50
55
60
65
70
75
80
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
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2
SN
R/S
FD
R (
dB
)
ANALOG INPUT COMMON-MODE VOLTAGE (V)
SFDR (dBc)
SNR (dB)
Figure 44. SNR/SFDR vs. Common-Mode Voltage, fIN = 2.4 MHz, fSAMPLE = 65 MSPS
40
45
50
55
60
65
70
75
80
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
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6-07
3
SN
R/S
FD
R (
dB
)
ANALOG INPUT COMMON-MODE VOLTAGE (V)
SFDR (dBc)
SNR (dB)
Figure 45. SNR/SFDR vs. Common-Mode Voltage, fIN = 30 MHz, fSAMPLE = 65 MSPS
90
500.2 1.6
ANALOG INPUT COMMON-MODE VOLTAGE (V)
SN
R/S
FD
R (
dB
)
85
80
75
70
65
60
55
0.4 0.6 0.8 1.0 1.2 1.4
SNR (dB)
SFDR (dBc)
0572
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2
Figure 46. SNR/SFDR vs. Common-Mode Voltage, fIN = 2.4 MHz, fSAMPLE = 40 MSPS
90
500.2 1.6
ANALOG INPUT COMMON-MODE VOLTAGE (V)
SN
R/S
FD
R (
dB
)
85
80
75
70
65
60
55
0.4 0.6 0.8 1.0 1.2 1.4
SNR (dB)
SFDR (dBc)
0572
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1
Figure 47. SNR/SFDR vs. Common-Mode Voltage, fIN = 30 MHz, fSAMPLE = 40 MSPS
AD9219 Data Sheet
Rev. E | Page 22 of 56
For best dynamic performance, the source impedances driving VIN + x and VIN − x should be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference buffer creates the positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common-mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as
REFT = 1/2 (AVDD + VREF) REFB = 1/2 (AVDD − VREF) Span = 2 × (REFT − REFB) = 2 × VREF
It can be seen from these equations that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage.
Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD9219, the largest input span available is 2 V p-p.
Differential Input Configurations
There are several ways to drive the AD9219 either actively or passively; however, optimum performance is achieved by driving the analog input differentially. For example, using the AD8332 differential driver to drive the AD9219 provides excellent perfor-mance and a flexible interface to the ADC (see Figure 51) for baseband applications. This configuration is commonly used for medical ultrasound systems.
For applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration (see Figure 48 and Figure 49), because the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9219.
Regardless of the configuration, the value of the shunt capacitor, C, is dependent on the input frequency and may need to be reduced or removed.
2Vp-p
R
R
*CDIFF
C
*CDIFF IS OPTIONAL
49.9Ω
0.1μF
1kΩ
1kΩ
AGNDAVDD
ADT1-1WT1:1 Z RATIO
VIN – x
ADCAD9219
VIN + x
C
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Figure 48. Differential Transformer-Coupled Configuration
for Baseband Applications
ADCAD9219
2Vp-p
2.2pF 1kΩ
0.1μF
1kΩ
1kΩ
AVDD
ADT1-1WT1:1 Z RATIO16nH 16nH0.1μF
16nH
33Ω
33Ω
499Ω65Ω
VIN + x
VIN – x
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7
Figure 49. Differential Transformer-Coupled Configuration
for IF Applications
Single-Ended Input Configuration
A single-ended input may provide adequate performance in cost-sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input common-mode swing. If the application requires a single-ended input configuration, ensure that the source impedances on each input are well matched in order to achieve the best possible performance. A full-scale input of 2 V p-p can be applied to the ADC’s VIN + x pin while the VIN − x pin is terminated. Figure 50 details a typical single-ended input configuration.
2V p-p
R
R
49.9Ω 0.1µF
0.1µF
AVDD
1kΩ 25Ω
1kΩ
1kΩ
AVDD
VIN – x
ADCAD9219
VIN + x
*CDIFF
C
*CDIFF IS OPTIONAL
C05
726-
009
Figure 50. Single-Ended Input Configuration
AD8332 1kΩ
187Ω
187Ω
0.1μF
0.1μF
0.1μF
1V p-p0.1μF
LNA
120nH
VGA
VOH
VIP
INH
22pF
LMD
VIN
LOP
LON
VOL
18nF 274Ω
VIN – x
ADCAD9219
VIN + x
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LPF
+68pF
33Ω
33Ω
AVDD
AVDD
680nH
680nH
10kΩ
10kΩ
10kΩ
10kΩ
Figure 51. Differential Input Configuration Using the AD8332 with Two-Pole, 16 MHz Low-Pass Filter
Data Sheet AD9219
Rev. E | Page 23 of 56
CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9219 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled to the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally and require no additional biasing.
Figure 52 shows a preferred method for clocking the AD9219. The low jitter clock source is converted from a single-ended signal to a differential signal using an RF transformer. The back-to-back Schottky diodes across the secondary transformer limit clock excursions into the AD9219 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9219, and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance.
0.1µF
0.1µF
0.1µF0.1µF
SCHOTTKYDIODES:HSM2812
CLK+
50Ω 100Ω
CLK–
CLK+ADC
AD9219
Mini-Circuits®
ADT1-1WT, 1:1Z
XFMR
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4
Figure 52. Transformer-Coupled Differential Clock
Another option is to ac-couple a differential PECL signal to the sample clock input pins as shown in Figure 53. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515 family of clock drivers offers excellent jitter performance.
100Ω
0.1µF
0.1µF0.1µF
0.1µF
240Ω240Ω50Ω* 50Ω*
CLK
CLK
*50Ω RESISTORS ARE OPTIONAL
CLK–
CLK+
ADCAD9219
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AD9510/AD9511/AD9512/AD9513/AD9514/AD9515
PECL DRIVER
CLK+
CLK–
Figure 53. Differential PECL Sample Clock
AD9510/AD9511/AD9512/AD9513/AD9514/AD9515
100Ω
0.1µF
0.1µF0.1µF
0.1µF
50Ω* 50Ω*
CLK
CLK
*50Ω RESISTORS ARE OPTIONAL
CLK–
CLK+
ADCAD9219
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LVDS DRIVER
CLK+
CLK–
Figure 54. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be driven directly from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 55). Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages of up to 3.3 V and therefore offers several selections for the drive logic voltage.
AD9510/AD9511/AD9512/AD9513/AD9514/AD9515
0.1µF
0.1µF
0.1µF
39kΩ
50Ω*OPTIONAL
100Ω
0.1µFCLK
*50Ω RESISTOR IS OPTIONAL
CLK–
CLK+
ADCAD9219
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CLK
CMOS DRIVER
CLK+
Figure 55. Single-Ended 1.8 V CMOS Sample Clock
AD9510/AD9511/AD9512/AD9513/AD9514/AD9515
0.1µF
0.1µF
0.1µF
50Ω*
CLK
*50Ω RESISTOR IS OPTIONAL
0.1µFCLK–
CLK+
ADCAD9219
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CLKOPTIONAL
100ΩCMOS DRIVER
CLK+
Figure 56. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9219 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9219. When the DCS is on, noise and distortion perfor-mance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See the Memory Map section for more details on using this feature.
Jitter in the rising edge of the input is an important concern, and it is not reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates of less than 20 MHz nominal. The loop has a time constant associated with it that must be considered in applications where the clock rate can change dynamically. This requires a wait time of 1.5 μs to 5 μs after a dynamic clock frequency increase (or decrease) before the DCS loop is relocked to the input signal. During the period that the loop is not locked, the DCS loop is bypassed and the internal device timing is dependent on the duty cycle of the input clock signal. In such applications, it may be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS circuit is recommended to maximize ac performance.
AD9219 Data Sheet
Rev. E | Page 24 of 56
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by
SNR Degradation = 20 × log 10(1/2 × π × fA × tJ)
In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter. IF undersampling applications are particularly sensitive to jitter (see Figure 57).
The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9219. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators are the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock during the last step.
Refer to the AN-501 Application Note and to the AN-756 Application Note for more in-depth information about jitter performance as it relates to ADCs at www.analog.com.
1 10 100 1000
16 BITS
14 BITS
12 BITS
30
40
50
60
70
80
90
100
110
120
130
0.125 ps0.25 ps0.5 ps1.0 ps2.0 ps
ANALOG INPUT FREQUENCY (MHz)
10 BITS
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RMS CLOCK JITTER REQUIREMENT
SN
R (
dB
)
Figure 57. Ideal SNR vs. Input Frequency and Jitter
Power Dissipation and Power-Down Mode
As shown in Figure 58 and Figure 59, the power dissipated by the AD9219 is proportional to its sample rate. The digital power dissipation does not vary significantly because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers.
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CU
RR
EN
T (
mA
)
PO
WE
R (
mW
)
ENCODE (MSPS)
AVDD CURRENT
TOTAL POWER
DRVDD CURRENT
180
200
220
240
260
280
300
320
340
360
0
20
40
60
80
100
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140
15 20 25 30 35 4010
Figure 58. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 40 MSPS
0
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CU
RR
EN
T (
mA
)
PO
WE
R (
mW
)
ENCODE (MSPS)
AVDD CURRENT
TOTAL POWER
DRVDD CURRENT
20
40
60
80
100
120
140
160
180
200
10 20 30 40 50 60250
270
290
310
330
350
370
390
Figure 59. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 65 MSPS
Data Sheet AD9219
Rev. E | Page 25 of 56
By asserting the PDWN pin high, the AD9219 is placed into power-down mode. In this state, the ADC typically dissipates 3 mW. During power-down, the LVDS output drivers are placed into a high impedance state. If any of the SPI features are changed before the power-down feature is enabled, the chip continues to function after PDWN is pulled low without requiring a reset. The AD9219 returns to normal operating mode when the PDWN pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant.
In power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, PLL, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering power-down mode and must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode: shorter cycles result in proportionally shorter wake-up times. With the recommended 0.1 μF and 2.2 μF decoupling capacitors on REFT and REFB, approximately 1 sec is required to fully discharge the reference buffer decoupling capacitors and approximately 375 μs is required to restore full operation.
There are several other power-down options available when using the SPI. The user can individually power down each channel or put the entire device into standby mode. The latter option allows the user to keep the internal PLL powered when fast wake-up times (~600 ns) are required. See the Memory Map section for more details on using these features.
Digital Outputs and Timing
The AD9219 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option (similar to the IEEE 1596.3 standard) via the SDIO/ODM pin or SPI. The LVDS standard can further reduce the overall power dissipation of the device by approximately 15 mW. See the SDIO/ODM Pin section or Table 16 in the Memory Map section for more information. The LVDS driver current is derived on-chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver.
The AD9219 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 Ω termination resistor
placed as close to the receiver as possible. If there is no far-end receiver termination or there is poor differential trace routing, timing errors may result. To avoid such timing errors, it is recommended that the trace length be less than 24 inches and that the differential output traces be close together and at equal lengths. An example of the FCO and data stream with proper trace length and position is shown in Figure 60.
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CH1 500mV/DIV = DCOCH2 500mV/DIV = DATACH3 500mV/DIV = FCO
2.5ns/DIV
Figure 60. LVDS Output Timing Example in ANSI-644 Mode (Default)
An example of the LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths less than 24 inches on standard FR-4 material is shown in Figure 61. Figure 62 shows an example of trace lengths exceeding 24 inches on standard FR-4 material. Notice that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. It is the user’s respon-sibility to determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. Additional SPI options allow the user to further increase the internal termination (increasing the current) of all four outputs in order to drive longer trace lengths (see Figure 63). Even though this produces sharper rise and fall times on the data edges and is less prone to bit errors, the power dissipation of the DRVDD supply increases when this option is used. In addition, notice in Figure 63 that the histogram is improved compared with that shown in Figure 62. See the Memory Map section for more details.
AD9219 Data Sheet
Rev. E | Page 26 of 56
100
50
0–100ps 0ps 100ps
TIE
JIT
TE
R H
IST
OG
RA
M (
Hit
s)
500
–500
0
–1ns –0.5ns 0ns 0.5ns 1ns
EY
E D
IAG
RA
M V
OL
TA
GE
(V
)
EYE: ALL BITS ULS: 10000/15600
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Figure 61. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Less than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only
200
–200
0
–1ns –0.5ns 0ns 0.5ns 1ns
EY
E D
IAG
RA
M V
OL
TA
GE
(V
)
EYE: ALL BITS ULS: 9600/15600
100
50
0–150ps –100ps –50ps 0ps 50ps 100ps 150ps
TIE
JIT
TE
R H
IST
OG
RA
M (
Hit
s)
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Figure 62. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
Greater than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only
100
50
0–150ps –100ps –50ps 0ps 50ps 100ps 150ps
TIE
JIT
TE
R H
IST
OG
RA
M (
Hit
s)
200
400
–200
–400
0
–1ns –0.5ns 0ns 0.5ns 1ns
EY
E D
IAG
RA
M V
OL
TA
GE
(V
)
EYE: ALL BITS ULS: 9599/15599
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2
Figure 63. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Internal
Termination on and Trace Lengths Greater than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only
The format of the output data is offset binary by default. An example of the output coding format can be found in Table 8. To change the output data format to twos complement, see the Memory Map section.
Table 8. Digital Output Coding
Code (VIN + x) − (VIN − x), Input Span = 2 V p-p (V)
Digital Output Offset Binary (D9 ... D0)
1023 +1.00 1111 1111 11 512 0.00 1000 0000 00 511 −0.001953 0111 1111 11 0 −1.00 0000 0000 00
Data from each ADC is serialized and provided on a separate channel. The data rate for each serial stream is equal to 10 bits times the sample clock rate, with a maximum of 650 Mbps (10 bits × 65 MSPS = 650 Mbps). The lowest typical conversion rate is 10 MSPS. However, if lower sample rates are required for a specific application, the PLL can be set up via the SPI to allow encode rates as low as 5 MSPS. See the Memory Map section for details on enabling this feature.
Data Sheet AD9219
Rev. E | Page 27 of 56
Two output clocks are provided to assist in capturing data from the AD9219. The DCO is used to clock the output data and is equal to five times the sample clock (CLK) rate. Data is clocked out of the AD9219 and must be captured on the rising and falling edges of the DCO that supports double data rate (DDR)
capturing. The FCO is used to signal the start of a new output byte and is equal to the sample clock rate. See the timing diagram shown in Figure 2 for more information.
Table 9. Flexible Output Test Modes Output Test Mode Bit Sequence Pattern Name Digital Output Word 1 Digital Output Word 2
Subject to Data Format Select
0000 Off (default) N/A N/A N/A 0001 Midscale short 1000 0000 (8-bit)
10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit)
Same Yes
0010 +Full-scale short 1111 1111 (8-bit) 11 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 11 1111 1111 1111 (14-bit)
Same Yes
0011 −Full-scale short 0000 0000 (8-bit) 00 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 00 0000 0000 0000 (14-bit)
Same Yes
0100 Checkerboard 1010 1010 (8-bit) 10 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 10 1010 1010 1010 (14-bit)
0101 0101 (8-bit) 01 0101 0101 (10-bit) 0101 0101 0101 (12-bit) 01 0101 0101 0101 (14-bit)
No
0101 PN sequence long1 N/A N/A Yes 0110 PN sequence short1 N/A N/A Yes 0111 One-/zero-word toggle 1111 1111 (8-bit)
11 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 11 1111 1111 1111 (14-bit)
0000 0000 (8-bit) 00 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 00 0000 0000 0000 (14-bit)
No
1000 User input Register 0x19 to Register 0x1A Register 0x1B to Register 0x1C No 1001 1-/0-bit toggle 1010 1010 (8-bit)
10 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 10 1010 1010 1010 (14-bit)
N/A No
1010 1× sync 0000 1111 (8-bit) 00 0001 1111 (10-bit) 0000 0011 1111 (12-bit) 00 0000 0111 1111 (14-bit)
N/A No
1011 One bit high 1000 0000 (8-bit) 10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit)
N/A No
1100 Mixed frequency 1010 0011 (8-bit) 10 0110 0011 (10-bit) 1010 0011 0011 (12-bit) 10 1000 0110 0111 (14-bit)
N/A No
1 All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver.
AD9219 Data Sheet
Rev. E | Page 28 of 56
When the SPI is used, the DCO phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO+ and DCO− timing, as shown in Figure 2, is 90° relative to the output data edge.
An 8-, 12-, or 14-bit serial stream can also be initiated from the SPI. This allows the user to implement and test compatibility with lower and higher resolution systems. When changing the resolution to a 12-bit serial stream, the data stream is lengthened. See Figure 3 for the 12-bit example. However, when using the 12-bit option, the data stream stuffs two 0s at the end of the 12-bit serial data.
When the SPI is used, all of the data outputs can also be inverted from their nominal state. This is not to be confused with inverting the serial stream to an LSB-first mode. In default mode, as shown in Figure 2, the MSB is first in the data output serial stream. However, this can be inverted so that the LSB is first in the data output serial stream (see Figure 4).
There are 12 digital output test pattern options available that can be initiated through the SPI. This is a useful feature when validating receiver capture and timing. Refer to Table 9 for the output bit sequencing options available. Some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. Note that some patterns do not adhere to the data format select option. In addition, custom user-defined test patterns can be assigned in the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver.
The PN sequence short pattern produces a pseudorandom bit sequence that repeats itself every 29 − 1 or 511 bits. A description of the PN sequence and how it is generated can be found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The only difference is that the starting value must be a specific value instead of all 1s (see Table 10 for the initial values).
The PN sequence long pattern produces a pseudorandom bit sequence that repeats itself every 223 − 1 or 8,388,607 bits. A description of the PN sequence and how it is generated can be found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The only differences are that the starting value must be a specific value instead of all 1s (see Table 10 for the initial values) and the AD9219 inverts the bit stream with relation to the ITU standard.
Table 10. PN Sequence
Sequence Initial Value
First Three Output Samples (MSB First)
PN Sequence Short 0x0df 0x37e, 0x135, 0x0cc PN Sequence Long 0x0a6e02 0x359, 0x07f, 0x170
Consult the Memory Map section for information on how to change these additional digital output timing features through the SPI.
SDIO/ODM Pin
The SDIO/ODM pin is for use in applications that do not require SPI mode operation. This pin can enable a low power, reduced signal option (similar to the IEEE 1596.3 reduced range link output standard) if it and the CSB pin are tied to AVDD during device power-up. This option should only be used when the digital output trace lengths are less than 2 inches from the LVDS receiver. When this option is used, the FCO, DCO, and outputs function normally, but the LVDS signal swing of all channels is reduced from 350 mV p-p to 200 mV p-p, allowing the user to further reduce the power on the DRVDD supply.
For applications where this pin is not used, it should be tied low. In this case, the device pin can be left open, and the 30 kΩ internal pull-down resistor pulls this pin low. This pin is only 1.8 V tolerant. If applications require this pin to be driven from a 3.3 V logic level, insert a 1 kΩ resistor in series with this pin to limit the current.
Table 11. Output Driver Mode Pin Settings
Selected ODM ODM Voltage Resulting Output Standard
Resulting FCO and DCO
Normal Operation
10 kΩ to AGND ANSI-644 (default)
ANSI-644 (default)
ODM AVDD Low power, reduced signal option
Low power, reduced signal option
Data Sheet AD9219
Rev. E | Page 29 of 56
SCLK/DTP Pin
The SCLK/DTP pin is for use in applications that do not require SPI mode operation. This pin can enable a single digital test pattern if it and the CSB pin are held high during device power-up. When SCLK/DTP is tied to AVDD, the ADC channel outputs shift out the following pattern: 1000 0000 0000. The FCO and DCO function normally while all channels shift out the repeatable test pattern. This pattern allows the user to perform timing alignment adjustments among the FCO, DCO, and output data. For normal operation, this pin should be tied to AGND through a 10 kΩ resistor. This pin is both 1.8 V and 3.3 V tolerant.
Table 12. Digital Test Pattern Pin Settings
Selected DTP DTP Voltage Resulting D + x and D − x
Resulting FCO and DCO
Normal Operation
10 kΩ to AGND Normal operation
Normal operation
DTP AVDD 1000 0000 0000 Normal operation
Additional and custom test patterns can also be observed when commanded from the SPI port. Consult the Memory Map section for information about the options available.
CSB Pin
The CSB pin should be tied to AVDD for applications that do not require SPI mode operation. By tying CSB high, all SCLK and SDIO information is ignored. This pin is both 1.8 V and 3.3 V tolerant.
RBIAS Pin
To set the internal core bias current of the ADC, place a resistor (nominally equal to 10.0 kΩ) to ground at the RBIAS pin. The resistor current is derived on-chip and sets the AVDD current of the ADC to a nominal 232 mA at 65 MSPS. Therefore, it is imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance.
Voltage Reference
A stable, accurate 0.5 V voltage reference is built into the AD9219. This is gained up internally by a factor of 2, setting VREF to 1.0 V, which results in a full-scale differential input span of 2 V p-p. The VREF is set internally by default; however, the VREF pin can be driven externally with a 1.0 V reference to improve accuracy.
When applying the decoupling capacitors to the VREF, REFT, and REFB pins, use ceramic low ESR capacitors. These capacitors should be close to the ADC pins and on the same layer of the PCB as the AD9219. The recommended capacitor values and configurations for the AD9219 reference pin are shown in Figure 64.
Table 13. Reference Settings
Selected Mode SENSE Voltage Resulting VREF (V)
Resulting Differential Span (V p-p)
External Reference
AVDD N/A 2 × external reference
Internal, 2 V p-p FSR
AGND to 0.2 V 1.0 2.0
AD9219 Data Sheet
Rev. E | Page 30 of 56
Internal Reference Operation
A comparator within the AD9219 detects the potential at the SENSE pin and configures the reference. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 64), setting VREF to 1 V.
The REFT and REFB pins establish the input span of the ADC core from the reference configuration. The analog input full-scale range of the ADC equals twice the voltage of the reference pin for either an internal or an external reference configuration.
If the reference of the AD9219 is used to drive multiple converters to improve gain matching, the loading of the refer-ence by the other converters must be considered. Figure 66 depicts how the internal reference voltage is affected by loading.
1µF 0.1µF
VREF
SENSE
0.5V
REFT
0.1µF
0.1µF 2.2µF
0.1µF
REFB
SELECTLOGIC
ADCCORE
+
VIN – x
VIN + x05
726-
010
Figure 64. Internal Reference Configuration
1µF 0.1µF
VREF
0.5V
REFT
0.1µF
0.1µF 2.2µF
0.1µF
REFB
SELECTLOGIC
ADCCORE
+
+
VIN – x
VIN + x
SENSE
R2
R1
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Figure 65. External Reference Operation
External Reference Operation
The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve thermal drift charac-teristics. Figure 67 shows the typical drift characteristics of the internal reference in 1 V mode.
When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. The external reference is loaded with an equivalent 6 kΩ load. An internal reference buffer generates the positive and negative full-scale references, REFT and REFB, for the ADC core. Therefore, the external reference must be limited to a nominal 1.0 V.
0 1.00.5 2.01.5 3.02.5 3.5
VR
EF E
RR
OR
(%
)
CURRENT LOAD (mA)
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–30
–5
–10
–15
–20
–25
5
0
Figure 66. VREF Accuracy vs. Load
0.02
–0.18–40 806040200–20
TEMPERATURE (°C)
VR
EF E
RR
OR
(%
)
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.12
–0.14
–0.16
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Figure 67. Typical VREF Drift
Data Sheet AD9219
Rev. E | Page 31 of 56
SERIAL PORT INTERFACE (SPI) The AD9219 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided in the ADC. This may provide the user with additional flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, as documented in the Memory Map section. Detailed operational information can be found in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, at www.analog.com.
There are three pins that define the SPI: SCLK, SDIO, and CSB (see Table 14). The SCLK pin is used to synchronize the read and write data presented to the ADC. The SDIO pin is a dual-purpose pin that allows data to be sent to and read from the internal ADC memory map registers. The CSB pin is an active low control that enables or disables the read and write cycles.
Table 14. Serial Port Pins Pin Function SCLK Serial Clock. The serial shift clock input. SCLK is used to
synchronize serial interface reads and writes. SDIO Serial Data Input/Output. A dual-purpose pin. The typical
role for this pin is as an input or output, depending on the instruction sent and the relative position in the timing frame.
CSB Chip Select Bar (Active Low). This control gates the read and write cycles.
The falling edge of the CSB in conjunction with the rising edge of the SCLK determines the start of the framing sequence. During an instruction phase, a 16-bit instruction is transmitted followed by one or more data bytes, which is determined by Bit Field W0 and Bit Field W1. An example of the serial timing and its definitions can be found in Figure 69 and Table 15. During normal operation, CSB is used to signal to the device that SPI commands are to be received and processed. When CSB is brought low, the device processes SCLK and SDIO to obtain instructions. Normally, CSB remains low until the communication cycle is complete. However, if connected to a slow device, CSB can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. CSB can be stalled when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until CSB is taken high to end the communication cycle. This allows complete memory transfers without requiring additional instruc-tions. Regardless of the mode, if CSB is taken high in the middle of a byte transfer, the SPI state machine is reset and the device waits for a new instruction.
In addition to the operation modes, the SPI port configuration influences how the AD9219 operates. For applications that do not require a control port, the CSB line can be tied and held high. This places the remainder of the SPI pins into their secondary modes, as defined in the SDIO/ODM Pin and SCLK/DTP Pin sections. CSB can also be tied low to enable 2-wire mode. When CSB is tied low, SCLK and SDIO are the only pins required for communication. Although the device is synchronized during power-up, the user should ensure that the serial port remains synchronized with the CSB line when using this mode. When operating in 2-wire mode, it is recommended to use a 1-, 2-, or 3-byte transfer exclusively. Without an active CSB line, streaming mode can be entered but not exited.
In addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the SDIO pin to change from an input to an output at the appropriate point in the serial frame.
Data can be sent in MSB- or LSB-first mode. MSB-first mode is the default at power-up and can be changed by adjusting the configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
HARDWARE INTERFACE The pins described in Table 14 compose the physical interface between the user’s programming device and the serial port of the AD9219. The SCLK and CSB pins function as inputs when using the SPI. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback.
If multiple SDIO pins share a common connection, care should be taken to ensure that proper VOH levels are met. Assuming the same load for each AD9219, Figure 68 shows the number of SDIO pins that can be connected together and the resulting VOH level. This interface is flexible enough to be controlled by either serial PROMS or PIC microcontrollers, providing the user with an alternative method, other than a full SPI controller, to program the ADC (see the AN-812 Application Note at www.analog.com).
AD9219 Data Sheet
Rev. E | Page 32 of 56
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NUMBER OF SDIO PINS CONNECTED TOGETHER
VO
H(V
)
1.715
1.720
1.725
1.730
1.735
1.740
1.745
1.750
1.755
1.760
1.765
1.770
1.775
1.780
1.785
1.790
1.795
1.800
0 302010 40 50 60 70 80 90 100
Figure 68. SDIO Pin Loading
If the user chooses not to use the SPI, these dual-function pins serve their secondary functions when the CSB is strapped to AVDD during device power-up. See the Theory of Operation section for details on which pin-strappable functions are supported on the SPI pins.
For users who wish to operate the ADC without using the SPI, remove any connections from the CSB, SCLK/DTP, and SDIO/ODM pins. By disconnecting these pins from the control bus, the ADC can function in its most basic operation. Each of these pins has an internal termination that floats to its respective level.
DON’T CARE
DON’T CAREDON’T CARE
DON’T CARE
SDIO
SCLK
CSB
tS tDH
tHI tCLK
tLO
tDS tH
R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0
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Figure 69. Serial Timing Details
Table 15. Serial Timing Definitions Parameter Timing (Minimum, ns) Description tDS 5 Setup time between the data and the rising edge of SCLK tDH 2 Hold time between the data and the rising edge of SCLK tCLK 40 Period of the clock tS 5 Setup time between CSB and SCLK tH 2 Hold time between CSB and SCLK tHI 16 Minimum period that SCLK should be in a logic high state tLO 16 Minimum period that SCLK should be in a logic low state tEN_SDIO 10 Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 69) tDIS_SDIO 10 Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 69)
Data Sheet AD9219
Rev. E | Page 33 of 56
MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map register table (Table 16) has eight address locations. The memory map is divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the device index and transfer register map (Address 0x05 and Address 0xFF), and the ADC functions register map (Address 0x08 to Address 0x22).
The leftmost column of the memory map indicates the register address number, and the default value is shown in the second rightmost column. The (MSB) Bit 7 column is the start of the default hexadecimal value given. For example, Address 0x09, the clock register, has a default value of 0x01, meaning that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. This setting is the default for the duty cycle stabilizer in the on condition. By writing a 0 to Bit 6 of this address followed by a 0x01 in Register 0xFF (transfer bit), the duty cycle stabilizer turns off. It is important to follow each writing sequence with a transfer bit to update the SPI registers. For more information on this and other functions, consult the AN-877 Application Note, Interfacing to High Speed ADCs via SPI at www.analog.com.
RESERVED LOCATIONS Undefined memory locations should not be written to except when writing the default values suggested in this data sheet. Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up.
DEFAULT VALUES When the AD9219 comes out of a reset, critical registers are preloaded with default values. These values are indicated in Table 16, where an X refers to an undefined feature.
LOGIC LEVELS An explanation of various registers follows: “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Similarly, “clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.”
AD9219 Data Sheet
Rev. E | Page 34 of 56
Table 16. Memory Map Register
Addr. (Hex) Register Name
(MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
(LSB) Bit 0
Default Value (Hex)
Default Notes/ Comments
Chip Configuration Registers
00 chip_port_config 0 LSB first 1 = on 0 = off (default)
Soft reset 1 = on 0 = off (default)
1 1 Soft reset 1 = on 0 = off (default)
LSB first 1 = on 0 = off (default)
0 0x18 The nibbles should be mirrored so that LSB- or MSB-first mode is set cor-rectly regardless of shift mode.
01 chip_id 8-bit Chip ID Bits [7:0] (AD9219 = 0x03), (default)
0x02 Default is unique chip ID, different for each device. This is a read-only register.
02 chip_grade X Child ID [6:4] (identify device variants of Chip ID) 000 = 65 MSPS 001 = 40 MSPS
X X X X Read only
Child ID used to differentiate graded devices.
Device Index and Transfer Registers
05 device_index_A X X Clock Channel DCO 1 = on 0 = off (default)
Clock Channel FCO 1 = on 0 = off (default)
Data Channel D 1 = on (default)0 = off
Data Channel C 1 = on (default)0 = off
Data Channel B 1 = on (default)0 = off
Data Channel A 1 = on (default) 0 = off
0x0F Bits are set to determine which on-chip device receives the next write command.
FF device_update X X X X X X X SW transfer 1 = on 0 = off (default)
0x00 Synchronously transfers data from the master shift register to the slave.
ADC Functions
08 modes X X X X X Internal power-down mode 000 = chip run (default) 001 = full power-down 010 = standby 011 = reset
0x00 Determines various generic modes of chip operation.
09 clock X X X X X X X Duty cycle stabilizer 1 = on (default) 0 = off
0x01 Turns the internal duty cycle stabilizer on and off.
0D test_io User test mode 00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once
Reset PN long gen1 = on 0 = off (default)
Reset PN short gen 1 = on 0 = off (default)
Output test mode—see Table 9 in the DigitalOutputs and Timing section. 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = −FS short 0100 = checkerboard output 0101 = PN 23 sequence 0110 = PN 9 sequence 0111 = one-/zero-word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency (format determined by output_mode)
0x00 When this reg-ister is set, the test data is placed on the output pins in place of normal data.
Data Sheet AD9219
Rev. E | Page 35 of 56
Addr. (Hex) Register Name
(MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
(LSB) Bit 0
Default Value (Hex)
Default Notes/ Comments
14 output_mode X 0 = LVDS ANSI-644 (default) 1 = LVDS low power (IEEE1596.3 similar)
X X X Output invert 1 = on 0 = off (default)
00 = offset binary (default) 01 = twos complement
0x00 Configures the outputs and the format of the data.
15 output_adjust X X Output driver termination 00 = none (default) 01 = 200 Ω 10 = 100 Ω 11 = 100 Ω
X X X X 0x00 Determines LVDS or other output properties. Primarily func-tions to set the LVDS span and common-mode levels in place of an external resistor.
16 output_phase X X X X 0011 = output clock phase adjust (0000 through 1010) 0000 = 0° relative to data edge 0001 = 60° relative to data edge 0010 = 120° relative to data edge 0011 = 180° relative to data edge (default) 0101 = 300° relative to data edge 0110 = 360° relative to data edge 1000 = 480° relative to data edge 1001 = 540° relative to data edge 1010 = 600° relative to data edge 1011 to 1111 = 660° relative to data edge
0x03 On devices that utilize global clock divide, determines which phase of the divider output is used to supply the output clock. Internal latching is unaffected.
19 user_patt1_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 1 LSB.
1A user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 1 MSB.
1B user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined pattern, 2 LSB.
1C user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined pattern, 2 MSB.
21 serial_control LSB first 1 = on 0 = off (default)
X X X <10 MSPS, low encode rate mode 1 = on 0 = off (default)
000 = 10 bits (default, normal bit stream) 001 = 8 bits 010 = 10 bits 011 = 12 bits 100 = 14 bits
0x00 Serial stream control. Default causes MSB first and the native bit stream (global).
22 serial_ch_stat X X X X X X Channel output reset 1 = on 0 = off (default)
Channel power-down 1 = on 0 = off (default)
0x00 Used to power down individual sections of a converter (local).
AD9219 Data Sheet
Rev. E | Page 36 of 56
Power and Ground Recommendations
When connecting power to the AD9219, it is recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one supply is available, it should be routed to the AVDD first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the DRVDD. The user can employ several different decoupling capacitors to cover both high and low frequencies. These should be located close to the point of entry at the PC board level and close to the parts, with minimal trace lengths.
A single PC board ground plane should be sufficient when using the AD9219. With proper decoupling and smart parti-tioning of the PC board’s analog, digital, and clock sections, optimum performance can be easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is required that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance of the AD9219. An exposed continuous copper plane on the PCB should mate to the AD9219 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be solder-filled or plugged.
To maximize the coverage and adhesion between the ADC and PCB, partition the continuous copper plane by overlaying a silkscreen on the PCB into several uniform sections. This provides several tie points between the ADC and PCB during the reflow process, whereas using one continuous plane with no partitions only guarantees one tie point. See Figure 70 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com.
SILKSCREEN PARTITIONPIN 1 INDICATOR
0572
6-01
3
Figure 70. Typical PCB Layout
Data Sheet AD9219
Rev. E | Page 37 of 56
EVALUATION BOARD The AD9219 evaluation board provides all of the support cir-cuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially using a transformer (default) or an AD8332 driver. The ADC can also be driven in a single-ended fashion. Separate power pins are provided to isolate the DUT from the drive circuitry of the AD8332. Each input configuration can be selected by changing the connection of various jumpers (see Figure 73 to Figure 77). Figure 71 shows the typical bench characterization setup used to evaluate the ac performance of the AD9219. It is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the converter. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance.
See Figure 73 to Figure 81 for the complete schematics and layout diagrams demonstrating the routing and grounding techniques that should be applied at the system level.
POWER SUPPLIES This evaluation board has a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Connect the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz. The other end of the supply is a 2.1 mm inner diameter jack that connects to the PCB at P503. Once on the PC board, the 6 V supply is fused and conditioned before connecting to three low dropout linear regulators that supply the proper bias to each of the various sections on the board.
When operating the evaluation board in a nondefault condition, L504 to L507 can be removed to disconnect the switching power supply. This enables the user to bias each section of the board individually. Use P501 to connect a different supply for
each section. At least one 1.8 V supply is needed for AVDD_DUT and DRVDD_DUT; however, it is recommended that separate supplies be used for analog and digital signals and that each supply have a current capability of 1 A. To operate the evaluation board using the VGA option, a separate 5.0 V analog supply (AVDD_5 V) is needed. To operate the evaluation board using the SPI and alternate clock options, a separate 3.3 V analog supply (AVDD_3.3 V) is needed in addition to the other supplies.
INPUT SIGNALS When connecting the clock and analog sources to the evaluation board, use clean signal generators with low phase noise, such as Rohde & Schwarz SMHU or HP8644 signal generators or the equivalent, as well as a 1 m, shielded, RG-58, 50 Ω coaxial cable. Enter the desired frequency and amplitude from the ADC speci-fications tables. Typically, most Analog Devices evaluation boards can accept approximately 2.8 V p-p or 13 dBm sine wave input for the clock. When connecting the analog input source, it is recommended to use a multipole, narrow-band, band-pass filter with 50 Ω terminations. Good choices of such band-pass filters are available from TTE, Allen Avionics, and K&L Microwave, Inc. The filter should be connected directly to the evaluation board if possible.
OUTPUT SIGNALS The default setup uses the Analog Devices HSC-ADC-FIFO5-INTZ to interface with the Analog Devices standard dual-channel FIFO data capture board (HCS-ADC-EVALCZ). Two of the eight channels can be evaluated at the same time. For more information on the channel settings and optional settings of these boards, visit www.analog.com/FIFO.
ROHDE & SCHWARZ,SMHU,
2V p-p SIGNALSYNTHESIZER
ROHDE & SCHWARZ,SMHU,
2V p-p SIGNALSYNTHESIZER
BAND-PASSFILTER
XFMRINPUT
CLK
CH A TO CH D10-BIT
SERIALLVDS
USBCONNECTION
AD9219EVALUATION BOARD
HSC-ADC-EVALCZFIFO DATACAPTURE
BOARD
PCRUNNING
ADCANALYZER
AND SPIUSER
SOFTWARE
1.8V– +– +
AV
DD
_DU
T
AV
DD
_3.3
V
DR
VD
D_D
UT
GN
D
GN
D
– +5.0V
GN
D
AV
DD
_5V
1.8V
6V DC2A MAX
WALL OUTLET100V TO 240V AC47Hz TO 63Hz
SWITCHINGPOWERSUPPLY
– +
GN
D
3.3V– +
VC
C
GN
D
3.3V
SPI SPISPI
0572
6-01
4
INTERPOSERBOARD
SPI Figure 71. Evaluation Board Connection
AD9219 Data Sheet
Rev. E | Page 38 of 56
DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9219 Rev. A evaluation board.
POWER: Connect the switching power supply that is provided in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P503.
AIN: The evaluation board is set up for a transformer-coupled analog input with an optimum 50 Ω impedance match of 200 MHz of bandwidth (see Figure 72). For more bandwidth response, the differential capacitor across the analog inputs can be changed or removed. The common mode of the analog inputs is developed from the center tap of the transformer or AVDD_DUT/2.
0
AM
PL
ITU
DE
(d
BF
S)
FREQUENCY (MHz)
0572
6-08
5
0
–16
–14
–12
–10
–8
–6
–4
–2
50 100 150 200 250 300 350 400 450 500
–3dB CUTOFF = 200MHz
Figure 72. Evaluation Board Full-Power Bandwidth
VREF: VREF is set to 1.0 V by tying the SENSE pin to ground, R237. This causes the ADC to operate in 2.0 V p-p full-scale range. A separate external reference option using the ADR510 is also included on the evaluation board.Populate R231 and R235 and remove C214. Proper use of the VREF options is noted in the Voltage Reference section.
RBIAS: RBIAS has a default setting of 10 kΩ (R201) to ground and is used to set the ADC core bias current.
CLOCK: The default clock input circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T201) that adds a very low amount of jitter to the clock path. The clock input is 50 Ω terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs.
A differential LVPECL clock can also be used to clock the ADC input using the AD9515 (U202). Populate R225 and R227 with 0 Ω resistors and remove R217 and R218 to disconnect the default clock path inputs. In addition, populate C207 and C208 with a 0.1 μF capacitor and remove C210 and C211 to disconnect the default clock path outputs. The AD9515 has many pin-strappable options that are set to a default mode of operation. Consult the AD9515 data sheet for more information about these and other options.
In addition, an on-board oscillator is available on the OSC201 and can act as the primary clock source. The setup is quick and involves installing R212 with a 0 Ω resistor and setting the enable jumper (J205) to the on position. If the user wishes to employ a different oscillator, two oscillator footprint options are available (OSC201) to check the ADC performance.
PDWN: To enable the power-down feature, short J201 to AVDD on the PDWN pin.
SCLK/DTP: To enable one of the two digital test patterns on the digital outputs of the ADC, use J204. If J204 is tied to AVDD during device power-up, Test Pattern 10 0000 0000 is enabled. See the SCLK/DTP Pin section for details.
SDIO/ODM: To enable the low power, reduced signal option (similar to the IEEE 1595.3 reduced range link LVDS output standard), use J203. If J203 is tied to AVDD during device power-up, it enables the LVDS outputs in a low power, reduced signal option from the default ANSI-644 standard. This option changes the signal swing from 350 mV p-p to 200 mV p-p, reducing the power of the DRVDD supply. See the SDIO/ODM Pin section for more details.
CSB: To enable processing of the SPI information on the SDIO and SCLK pins, tie J202 low in the always enable mode. To ignore the SDIO and SCLK information, tie J202 to AVDD.
Non-SPI Mode: For users who wish to operate the DUT without using SPI, remove Jumpers J302, J303, and J304. This disconnects the CSB, SCLK/DTP, and SDIO/ODM pins from the control bus, allowing the DUT to operate in its simplest mode. Each of these pins has internal termination and will float to its respective level.
D + x, D − x: If an alternative data capture method to the setup shown in Figure 73 is used, optional receiver terminations, R206 to R211, can be installed next to the high speed back-plane connector.
Data Sheet AD9219
Rev. E | Page 39 of 56
ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION The following is a brief description of the alternative analog input drive configuration using the AD8332 dual VGA. If this drive option is in use, some components may need to be populated, in which case all the necessary components are listed in Table 17. For more details on the AD8332 dual VGA, including how it works and its optional pin settings, consult the AD8332 data sheet.
To configure the analog input to drive the VGA instead of the default transformer option, the following components need to be removed and/or changed.
Remove R102, R115, R128, R141, R161, R162, R163, R164, T101, T102, T103, and T104 in the default analog input path.
Populate R101, R114, R127, and R140 with 0 Ω resistors in the analog input path.
Populate R105, R113, R118, R124, R131, R137, R151, and R160 with 0 Ω resistors in the analog input path to connect the AD8332.
Populate R152, R153, R154, R155, R156, R157, R158, R159, C103, C105, C110, C112, C117, C119, C124, and C126 with 10 kΩ resistors to provide an input common-mode level to the ADC analog inputs.
Remove R305, R306, R313, R314, R405, R406, R412, and R424 to configure the AD8332.
In this configuration, L301 to L308 and L401 to L408 are populated with 0 Ω resistors to allow signal connection and use of a filter if additional requirements are necessary.
AD9219 Data Sheet
Rev. E | Page 40 of 56
CHANNEL AP101
AIN
AIN
VGA INPUT CONNECTION
VGA INPUT CONNECTION
VGA INPUT CONNECTION
VGA INPUT CONNECTION
1
2
3
6
5
4
T101
CM1
CM1 FB10310Ω
FB10210Ω
FB10110Ω
C1042.2pF
VIN_A
VIN_A
P102DNP
CM1
INH1
CH_A
AVDD_DUT
CH_A
R1040Ω
AVDD_DUT
AVDD_DUT
C106DNPC107
0.1µF
C103DNP
C105DNP
C1010.1µF
C1020.1µF
E101
R161499Ω
R152DNP
R113DNP
R105DNP
R11033Ω
R107DNP
R106DNP
R1121kΩ
R1111kΩ
R10833Ω
R101DNP
R10264.9Ω
R1030Ω
R1091kΩ
CHANNEL BP103
AIN 1
2
3
6
5
4
T102
CM2
CM2 FB10610Ω
FB10510Ω
FB10410Ω
C1112.2pF
VIN_B
VIN_B
P104DNP
CM2
INH2 CH_B
AVDD_DUT
CH_B
R1160Ω
AVDD_DUT
AVDD_DUT
C113DNPC114
0.1µF
C110DNP
C112DNP
C1080.1µF
C1090.1µF
E102
R162499Ω
R153DNP
R124DNP
R118DNP
R12233Ω
R120DNP
R119DNP
R1261kΩ
R1251kΩ
R12133Ω
R114DNP
R11564.9Ω
R1170Ω
R1231kΩ
CHANNEL CP105
AIN
1
2
3
6
5
4
T103
CM3
CM3 FB10910Ω
FB10810Ω
FB10710Ω
C1182.2pF
VIN_C
VIN_C
P106DNP
CM3
INH3
CH_C
AVDD_DUT
CH_C
R1300Ω
AVDD_DUT
AVDD_DUT
C120DNPC121
0.1µF
C117DNP
C119DNP
C1150.1µF
C1160.1µF
E103
R163499Ω
R154DNP
R137DNP
R131DNP
R13633Ω
R133DNP
R132DNP
R1391kΩ
R1381kΩ
R13433Ω
R127DNP
R12864.9Ω
R1290Ω
R1351kΩ
CHANNEL DP107
AIN 1
2
3
6
5
4
T104
CM4
CM4 FB11210Ω
FB11110Ω
R1430Ω
C1252.2pF
VIN_D
VIN_D
P108DNP
CM4
INH4 CH_D
AVDD_DUT
CH_D
FB11010Ω
AVDD_DUT
AVDD_DUT
C127DNPC128
0.1µF
C124DNP
C126DNP
R159DNP
C1220.1µF
C1230.1µF
E104
R164499Ω
R155DNP
R160DNP
R151DNP
R14733Ω
R145DNP
R144DNP
R1501kΩ
R1491kΩ
R14633Ω
R140DNP
R14164.9Ω
R1420Ω
R1481kΩ
R156DNP
R157DNP
0572
6-01
5
AIN
AIN
AIN
R158DNP
DNP: DO NOT POPULATE Figure 73. Evaluation Board Schematic, DUT Analog Inputs
Data Sheet AD9219
Rev. E | Page 41 of 56
05726-016
CS
B
C21
70.
1µF
C22
00.
1µF
C22
10.
1µF
C21
80.
1µF
C21
90.
1µF
C22
30.
1µF
C22
20.
1µF
AV
DD
_3.3
V
CL
K
CL
KB
GND
GN
D_P
AD
OU
T0
OU
T0B
OU
T1
OU
T1B
RSET
S0
S1
S10
S2
S3
S4
S5
S6
S7
S8
S9
SY
NC
B VREF
VS
SIG
NA
L=
DN
C;2
7,28
INP
UT
EN
CO
DE
EN
C
EN
CD
NP
CL
OC
K C
IRC
UIT
OP
TIO
NA
L C
LO
CK
DR
IVE
CIR
CU
IT
DIS
AB
LE
EN
AB
LE
OP
TIO
NA
L C
LO
CK
OS
CIL
LA
TO
R
C22
40.
1µF
R21
410
kΩ
R21
510
kΩ
14
78
1 3 5
12 10
OS
C20
1
VF
AC
3H-L
C20
70.
1µF
DN
P
C20
80.
1µF
DN
P
C20
90.
1µF
DN
P
C21
50.
1µF
DN
P
C21
10.
1µF
C21
00.
1µF
E20
2
1E
201
P20
1
P20
3
AV
DD
_3.3
V
12
6
7
25
8
16
9
15
10
14
11
13
181923 22
32
1
31
33
U20
2
SIG
NA
L=
AV
DD
_3.3
V;4
,17,
20,2
1,24
,26,
29,3
0A
D95
15
3
2
1
CR
201
HS
MS
2812
R22
0D
NP
R24
024
3Ω
R24
310
0Ω
R24
124
3ΩR24
210
0Ω
6543 2 1T
201
1
2
3
J205
C20
50.
1µF
C21
60.
1µF
R21
349
.9kΩ
R21
60Ω
R22
110
kΩ
R21
20Ω D
NP
R21
9D
NP
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
OP
T_C
LK
OP
T_C
LK
CL
K
AV
DD
_3.3
V
OP
T_C
LK
OP
T_C
LK
CL
K
CL
K
LV
PE
CL
OU
TP
UT
LV
DS
OU
TP
UT
CL
K
AV
DD
_3.3
V
11
E20
3
AV
DD
_3.3
V
VC
C
GN
DO
UT
OE
OE
'
GN
D'
VC
C'
OU
T'
R24
4D
NP
R24
50Ω
S4
S0
S5
S3
S2
S1
AV
DD
_3.3
V
AV
DD
_3.3
V
AV
DD
_3.3
V
AV
DD
_3.3
V
AV
DD
_3.3
V
AV
DD
_3.3
V
R24
6D
NP
R24
70Ω
R24
8D
NP
R24
90Ω
R25
0D
NP
R25
10Ω
R25
2D
NP
R25
30Ω
R25
4D
NP
R25
50Ω
R25
6D
NP
R25
70Ω
S10S6
S9
S8
S7
AV
DD
_3.3
V
AV
DD
_3.3
V
AV
DD
_3.3
V
AV
DD
_3.3
V
AV
DD
_3.3
V
R25
8D
NP
R25
90Ω
R26
0D
NP
R26
10Ω
R26
2D
NP
R26
30Ω
R26
4D
NP
R26
50Ω
A1
A2
A3
A4
A5
A6
A7
A8
A9
GN
DA
B1
GN
DA
B10
GN
DA
B2
GN
DA
B3
GN
DA
B4
GN
DA
B5
GN
DA
B6
GN
DA
B7
GN
DA
B8
GN
DA
B9
GN
DC
D1
GN
DC
D10
GN
DC
D2
GN
DC
D3
GN
DC
D4
GN
DC
D5
GN
DC
D6
GN
DC
D7
GN
DC
D8
GN
DC
D9
HE
AD
ER
646
916
9-1
R20
5–R
211
OP
TIO
NA
L O
UT
PU
TT
ER
MIN
AT
ION
S
DIG
ITA
L O
UT
PU
TS
CS
B3_
_CH
B
SD
I_C
HB
SD
O_C
HA
CS
B2_
CH
A
CS
B1_
CH
A
SD
I_C
HA
SC
LK
_CH
A
R20
6D
NP
R21
1D
NP
R21
0D
NP
R20
9D
NP
R20
8D
NP
P20
2
R20
7D
NP
SC
LK
_CH
B
DC
OC
10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C10
50 49 48 47 46 45 44 43 42 41 20 19 18 17 16 15 14 13 12
D10 D
9
D8
D7
D6
D5
D4
D3
D2
D1
B10 B
9
B8
B7
B6
B5
B4
B3
B2
B1
11
CH
D
CH
C
CH
B
CH
A
FC
O
DC
O
CH
D
CH
C
CH
B
CH
A
FC
O
SD
O_C
HB
CS
B4_
CH
B
4060 19
2122
45
25
6
26
8
3132333435363738 291030
2
23
3
242851525354555657583959
7
27
OD
M E
NA
BL
E
CL
K
AV
DD
CL
K+
CL
K–
D + A
D + B
D + C
D + D
D – A
D – B
D – C
D – D
DCO+
DCO–
DR
VD
D
DR
GN
D
FCO+
FCO–
PD
WN
RBIAS
REFB
REFT
SC
LK
/DT
P
SD
IO/O
DM
SENSE
VIN
+ A
VIN + B
VIN + C
VIN
+ D
VIN
– A
VIN – B
VIN – C
VIN
– D
VREF
AV
DD
AV
DD
AV
DD
AV
DD
AV
DD
AVDD
AV
DD
AV
DD
AV
DD
AV
DD
AVDD
AVDD
DR
GN
D
DR
VD
D
RE
FE
RE
NC
ED
EC
OU
PL
ING
C20
40.
1µF
C20
30.
1µF
C20
22.
2µF
C20
10.
1µF
R20510kΩ
R203100kΩ
R204100kΩ
3
2
1J2
01
1 8730
20
18
16
14
19
17
15
13
24
23
11 12
22
21
102
25262732353639
45
46
5 6 9
31
40
43
44
2829
41
33
38
47
4
3437
48
3
42
U20
1
AD
9219
LF
CS
P
R20
210
0kΩ
CS
B_D
UT
1
2
3J2
02
SD
IO_O
DM
1
2
3J2
03
SC
LK
_DT
P3
2
1J2
04
DR
VD
D_D
UT
DR
VD
D_D
UT
R20
110
kΩ AVDD_DUT
CHA
CHB
CHC
CHD
CHA
CHB
CHC
DCODCO
FCO
FCO
AV
DD
_DU
T
AV
DD
_DU
T
AV
DD
_DU
T
AVDD_DUTAVDD_DUT
VSENSE_DUT
VIN
_A
VIN_B
VIN_C
VIN
_AVIN_B
VREF_DUT
AV
DD
_DU
T
AV
DD
_DU
T
CL
K
CHD
AV
DD
_DU
T
AV
DD
_DU
T
AV
DD
_DU
T
AV
DD
_DU
T
AV
DD
_DU
T
VIN
_D
VIN_C
VIN
_D
GN
DG
ND
AV
DD
_DU
T
PW
DN
EN
AB
LE
AL
WA
YS
EN
AB
LE
SP
I
DT
P E
NA
BL
E
U20
3
CW
VR
EF
= 1
V
VR
EF
= E
XT
ER
NA
L
VR
EF
= 0
.5V
RE
MO
VE
C21
4 W
HE
N U
SIN
G E
XT
ER
NA
L V
RE
F
VR
EF
= 0
.5V
(1+
R23
2/R
233)
VR
EF
SE
LE
CT
RE
FE
RE
NC
E C
IRC
UIT
C21
20.
1µF
R22
94.
99kΩ
C21
41µ
FC
213
0.1µ
F
R23
010
kΩ
R23
1D
NP
DN
P
VS
EN
SE
_DU
T
R22
847
0kΩ
DN
P
DN
P
R23
4D
NP
R23
5D
NP
R23
6D
NP
R23
70Ω
DN
P
AV
DD
_DU
T
VR
EF
_DU
T AVDD_DUT
TR
IM/N
C
V–
V+
AD
R51
01V
R23
2D
NP
R23
3D
NP
R21
70Ω R21
80Ω
R22
50Ω DN
PR
226
49.9Ω
DN
P
R22
70Ω DN
PR
238
DN
PR
239
10kΩ
C20
60.
1µF
R22
30Ω
R22
40Ω
R22
24.
02kΩ
2 3 5N
C =
NO
CO
NN
EC
T
R266100kΩ - DNP
R267100kΩ - DNP
CL
IP S
INE
OU
T (
DE
FA
UL
T)
DN
P:
DO
NO
T P
OP
UL
AT
E
OP
TIO
NA
LE
XT
RE
F
Figure 74. Evaluation Board Schematic, DUT, VREF, Clock Inputs, and Digital Output Interface
AD9219 Data Sheet
Rev. E | Page 42 of 56
CW
PO
WE
R D
OW
N E
NA
BL
E(0
-1V
= D
ISA
BL
E P
OW
ER
)
EXTERNAL VARIABLE GAIN DRIVE
VARIABLE GAIN CIRCUIT(0-1.0V DC)
R31910kΩ
12
JP301
GND
VG
R32039kΩ
VG
AVDD_5V
HIL
O P
INH
I G
AIN
RA
NG
E =
2.2
5V-5
.0V
LO
GA
IN R
AN
GE
= 0
-1.0
V
R31510kΩ
L310120nH
C3220.018µF
C3170.018µF
R316274Ω R317
274Ω
C3120.1µF
C3250.1µF
C3130.1µF
C3140.1µF
L309120nH
C31822pF
C3210.1µF
C3200.1µF
C3160.1µF
R31810kΩ
C32322pF
C3190.1µF
C3240.1µF
INH4 INH3
AV
DD
_5V
AV
DD
_5V
C32610µF
C31510µF
OP
TIO
NA
L V
GA
DR
IVE
CIR
CU
IT F
OR
CH
AN
NE
L C
AN
D C
HA
NN
EL
D
C3110.1µF
R31210kΩ
R31310kΩDNP
C303DNP
L3040Ω
R303DNP
L3080Ω
24 172023 1822 1921
R304DNP
L3060Ω
L3050Ω
L3020Ω
L3030Ω
L3070Ω
C3080.1µF
C3070.1µF
C3060.1µF
C3050.1µF
R310187Ω
R309187Ω
R308187Ω
R307187Ω
C302DNPL301
0Ω
C301DNP
R305374Ω
R306374Ω
CH
_C
CH
_D
CH
_D
CH
_C
AV
DD
_5V
AV
DD
_5V
AV
DD
_5V
C304DNP
R301DNP
R302DNP
3110
2625
1427
3 64 51 832
9
1516 VG
281329123011
2 7COM1 COM2
ENBLENBV
GAINHILO
INH
1
INH
2
LM
D1
LM
D2
LO
N1
LO
N2LOP1 LOP2
MODEN
C
RCLMP
VCM1 VCM2VIN1 VIN2VIP1 VIP2
VO
H1
VO
H2
VO
L1
VO
L2
VP
S1
VP
S2
VP
SV
AD8332
CO
MM
CO
MM
R31110kΩDNP
R31410kΩDNP
C3100.1µF
C3091000pF
RC
LA
MP
PIN
HIL
O P
IN =
LO
= ±
50m
VH
ILO
PIN
= H
= ±
75m
V
0572
6-01
7
MO
DE
PIN
PO
SIT
IVE
GA
IN S
LO
PE
= 0
-1.0
VN
EG
AT
IVE
GA
IN S
LO
PE
= 2
.25V
-5.0
V
U301
POPULATE L301-L308 WITH 0ΩRESISTORS OR DESIGN YOUROWN FILTER.
DNP: DO NOT POPULATE Figure 75. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface Circuit
Data Sheet AD9219
Rev. E | Page 43 of 56
MODE PINPOSITIVE GAIN SLOPE = 0-1.0VNEGATIVE GAIN SLOPE = 2.25V-5.0V
HILO PINHI GAIN RANGE = 2.25V-5.0VLO GAIN RANGE = 0-1.0V R
414
10kΩ
L41
012
0nH
R41
527
4Ω
C41
00.
1µF
C42
50.
1µF
C42
30.
1µF
C42
40.
1µF
L40
912
0nH
C41
822
pF
C41
70.
1µF
C41
60.
1µF
C41
40.
1µF
R41
710
kΩ
C42
122
pF
C41
90.
1µF
C42
20.
1µF
INH
2IN
H1
AVDD_5V
AVDD_5V
C42
610
µF
C41
310
µF
OPTIONAL VGA DRIVE CIRCUIT FOR CHANNEL A AND CHANNEL B
C40
90.
1µFR
411
10kΩ
R41
210
kΩD
NP
C40
3D
NP
L40
40Ω
R40
3D
NP
L40
80Ω
24
17
20
23
18
22
19
21
R40
4D
NP
L40
60Ω
L40
50Ω
L40
20Ω
L40
30Ω
L40
70Ω
C40
80.
1µF
C40
70.
1µF
C40
60.
1µF
C40
50.
1µF
R41
018
7ΩR
409
187Ω
R40
818
7ΩR
407
187Ω
C40
2D
NP
L40
10Ω
C40
1D
NP
R40
537
4Ω
R40
637
4Ω
CH_A
CH_B
CH_B
CH_A
AVDD_5V
AVDD_5V
AVDD_5V
C40
4D
NP
R40
1D
NP
R40
2D
NP
3110
2625
1427
3
6
45
1
8
3291516
VG
2813
2912
3011
2
7
CO
M1
CO
M2
EN
BL
EN
BV
GA
INH
ILO
INH1
INH2
LMD1
LMD2
LON1
LON2
LO
P1
LO
P2
MO
DE
NC
RC
LM
P
VC
M1
VC
M2
VIN
1V
IN2
VIP
1V
IP2
VOH1
VOH2
VOL1
VOL2
VPS1
VPS2
VPSV
AD
8332
U40
1
COMM
COMM
R41
310
kΩD
NP
R42
410
kΩD
NP
C41
20.
1µF
RCLAMP PINHILO PIN = LO = ±50mVHILO PIN = H = ±75mV
0572
6-01
8
POWER DOWN ENABLE(0–1V = DISABLE POWER)
R416274Ω
POPULATEL401-L408WITH0ΩRESISTORSORDESIGNYOUROWNFILTER.
Y1
VC
C Y2
A2
GN
D
A1
SP
I C
IRC
UIT
RY
FR
OM
FIF
O
SD
IO_O
DM
AV
DD
_DU
T
R43
11kΩ
R43
21kΩ
R43
31kΩ
AV
DD
_3.3
V
1 2 3456
NC
7WZ
07
U40
3
R42
510
kΩ
AV
DD
_DU
T
RE
SE
T/R
EP
RO
GR
AM
1 23 4
S40
1
+3.
3V =
NO
RM
AL
OP
ER
AT
ION
= A
VD
D_3
.3V
+5V
= P
RO
GR
AM
MIN
G =
AV
DD
_5V
AV
DD
_5V
AV
DD
_3.3
V J402
C42
70.
1µF
R4184.75kΩ
PIC
12F
629
R41
926
1Ω
431 2
568 7
U40
2
CR
401
GP
0G
P1
GP
2
GP
4G
P5
VD
DV
SS
MC
LR
/G
P3
RE
MO
VE
WH
EN
US
ING
OR
PR
OG
RA
MM
ING
PIC
(U
402)
R4270Ω
R4200Ω
R4280Ω
R4260Ω
SDO_CHA
SDI_CHA
SCLK_CHA
CSB1_CHA
C42
90.
1µF
SC
LK
_DT
P
CS
B_D
UT
AV
DD
_DU
T
Y1
VC
C Y2
A2
GN
D
A1
1 2 3456
U40
4R
430
10kΩ
R42
910
kΩ
NC
7WZ
16
C42
80.
1µF
PIC PROGRAMMING HEADER
MCLR/GP3
GP0
GP1
PICVCC
MCLR/GP3
GP0
GP1
PICVCC
97
5
3
1
108
6
4
2
J401E40
1
R42
10-
DN
P
R42
30-
DN
P
R42
20-
DN
P
OPTIONAL
DN
P:
DO
NO
T P
OP
UL
AT
E
C4200.018µF
C41
50.
018µ
F
C41
110
00p
F
Figure 76. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface Circuit (Continued)
AD9219 Data Sheet
Rev. E | Page 44 of 56
MO
UN
TIN
G H
OL
ES
CO
NN
EC
TE
D T
O G
RO
UN
D
H2
H3
H1
H4
P1
P2
P3
P4
P5
P6
P7
P8
OP
TIO
NA
L P
OW
ER
IN
PU
T
+5.
0V
+1.
8V
+1.
8V
+3.
3V
1 2 3 4 5 6 7 8
P50
1
3.3V
_AV
DD
5V_A
VD
D
L50
210
µH
DU
T_A
VD
D
DU
T_D
RV
DD
C50
90.
1µF
C50
810
µF
L50
310
µH
L50
110
µH
DR
VD
D_D
UT
AV
DD
_DU
T
0.1µ
FC
505
0.1µ
FC
507
C50
30.
1µF
AV
DD
_5V
10µ
FC
504
C50
210
µF
10µ
FC
506
AV
DD
_3.3
V10
µH
L50
8
DE
CO
UP
LIN
G C
AP
AC
ITO
RS
AV
DD
_3.3
V
0.1µ
FC
524
0.1µ
FC
525
C52
10.
1µF
C53
10.
1µF
C53
00.
1µF
C52
90.
1µF
C52
20.
1µF
C52
80.
1µF
C52
70.
1µF
C52
60.
1µF
0.1µ
FC
517
0.1µ
FC
516
C51
80.
1µF
C52
00.
1µF
C51
90.
1µF
C52
30.
1µF
DR
VD
D_D
UT
AV
DD
_DU
T
AV
DD
_5V
SM
DC
110F
PO
WE
R S
UP
PL
Y I
NP
UT
6V,
2V M
AX
IMU
M
1
3
2
P50
3
C50
110
µF
F50
1
D50
23A S
HO
T_R
EC
TD
O-2
14A
B
D50
1S
2A_R
EC
T2A D
O-2
14A
A
21
34
FE
R50
1
CH
OK
E_C
OIL
CR
501
R50
126
1Ω
PW
R_I
N
+
GND
INP
UT
OU
TP
UT
1
GND
INP
UT
OU
TP
UT
1
OU
TP
UT
4
OU
TP
UT
4
GND
INP
UT
GND
INP
UT
DN
P:
DO
NO
T P
OP
UL
AT
E
423
1
AD
P33
39A
KC
-5
U50
4
423
1
AD
P33
39A
KC
-3.3
U50
2
1
32 4
U50
1 AD
P33
39A
KC
-1.8
1
32 4
U50
3 AD
P33
39A
KC
-1.8
L50
510
µH
10µ
HL
504
C51
51µ
F
C51
31µ
FC
512
1µF
C51
41µ
F
PW
R_I
N
PW
R_I
N
DU
T_A
VD
D
DU
T_D
RV
DD
5V_A
VD
D
3.3V
_AV
DD
PW
R_I
N
PW
R_I
N C53
21µ
F
C53
41µ
FC
535
1µF
C53
31µ
F
L50
710
µH
L50
610
µH
OU
TP
UT
1
OU
TP
UT
1
OU
TP
UT
4
OU
TP
UT
4
05726-019
Figure 77. Evaluation Board Schematic, Power Supply Inputs
Data Sheet AD9219
Rev. E | Page 45 of 56
0572
6-02
0
Figure 78. Evaluation Board Layout, Primary Side
AD9219 Data Sheet
Rev. E | Page 46 of 56
0572
6-02
1
Figure 79. Evaluation Board Layout, Ground Plane
Data Sheet AD9219
Rev. E | Page 47 of 56
0572
6-02
2
Figure 80. Evaluation Board Layout, Power Plane
AD9219 Data Sheet
Rev. E | Page 48 of 56
0572
6-02
3
Figure 81. Evaluation Board Layout, Secondary Side (Mirrored Image)
Data Sheet AD9219
Rev. E | Page 49 of 56
Table 17. Evaluation Board Bill of Materials (BOM)1
Item Qty. Reference Designator Device Package Value Manufacturer Manufacturer’s Part Number
1 1 AD9219LFCSP_REVA PCB PCB PCB 2 75 C101, C102, C107, C108,
C109, C114, C115, C116, C121, C122, C123, C128, C201, C203, C204, C205, C206, C210, C211, C212, C213, C216, C217, C218, C219, C220, C221, C222, C223, C224, C310, C311, C312, C313, C314, C316, C319, C320, C321, C324, C325, C409, C410, C412, C414, C416, C417, C419, C422, C423, C424, C425, C427, C428, C429, C503, C505, C507, C509, C516, C517, C518, C519, C520, C521, C522, C523, C524, C525, C526, C527, C528, C529, C530, C531
Capacitor 402 0.1 μF, ceramic, X5R, 10 V, 10% tol
Murata GRM155R71C104KA88D
3 4 C104, C111, C118, C125 Capacitor 402 2.2 pF, ceramic, COG, 0.25 pF tol, 50 V
Murata GRM1555C1H2R2GZ01B
4 4 C315, C326, C413, C426 Capacitor 805 10 μF, 6.3 V ±10% ceramic, X5R
Murata GRM219R60J106KE19D
5 1 C202 Capacitor 603 2.2 μF, ceramic, X5R, 6.3 V, 10% tol
Murata GRM188C70J225KE20D
6 2 C309, C411 Capacitor 402 1000 pF, ceramic, X7R, 25 V, 10% tol
Murata GRM155R71H102KA01D
7 4 C317, C322, C415, C420 Capacitor 402 0.018 μF, ceramic, X7R, 16 V, 10% tol
AVX 0402YC183KAT2A
8 4 C318, C323, C418, C421 Capacitor 402 22 pF, ceramic, NPO, 5% tol, 50 V
Murata GRM1555C1H220JZ01D
9 1 C501 Capacitor 1206 10 μF, tantalum, 16 V, 20% tol
Rohm TCA1C106M8R
10 9 C214, C512, C513, C514, C515, C532, C533, C534, C535
Capacitor 603 1 μF, ceramic, X5R, 6.3 V, 10% tol
Murata GRM188R61C105KA93D
11 8 C305, C306, C307, C308, C405, C406, C407, C408
Capacitor 805 0.1 μF, ceramic, X7R, 50 V, 10% tol
Murata GRM21BR71H104KA01L
12 4 C502, C504, C506, C508 Capacitor 603 10 μF, ceramic, X5R, 6.3 V, 20% tol
Murata GRM188R60J106M
13 1 CR201 Diode SOT-23 30 V, 20 mA, dual Schottky
Agilent Technologies
HSMS2812-TRIG
14 2 CR401, CR501 LED 603 Green, 4 V, 5 m candela
Panasonic LNJ314G8TRA
15 1 D502 Diode DO-214AB 3 A, 30 V, SMC Micro Commercial Co.
SK33-TP
16 1 D501 Diode DO-214AA 2 A, 50 V, SMC Micro Commercial Co.
S2A-TP
17 1 F501 Fuse 1210 6.0 V, 2.2 A trip-current resettable fuse
Tyco/Raychem NANOSMDC110F-2
18 1 FER501 Choke coil 2020 10 μH, 5 A, 50 V, 190 Ω @ 100 MHz
Murata DLW5BSN191SQ2L
AD9219 Data Sheet
Rev. E | Page 50 of 56
Item Qty. Reference Designator Device Package Value Manufacturer Manufacturer’s Part Number
19 12 FB101, FB102, FB103, FB104, FB105, FB106, FB107, FB108, FB109, FB110, FB111, FB112
Ferrite bead 603 10 Ω, test freq 100 MHz, 25% tol, 500 mA
Murata BLM18BA100SN1B
20 1 JP301 Connector 2-pin 100 mil header jumper, 2-pin
Samtec TSW-102-07-G-S
21 2 J205, J402 Connector 3-pin 100 mil header jumper, 3-pin
Samtec TSW-103-07-G-S
22 1 J201 to J204 Connector 12-pin 100 mil header male, 4 × 3 triple row straight
Samtec TSW-104-08-G-T
23 1 J401 Connector 10-pin 100 mil header, male, 2 × 5 double row straight
Samtec TSW-105-08-G-D
24 8 L501, L502, L503, L504, L505, L506, L507, L508
Ferrite bead 1210 10 μH, bead core 3.2 × 2.5 × 1.6 SMD, 2 A
Murata BLM31PG500SN1L
25 4 L309, L310, L409, L410 Inductor 402 120 nH, test freq 100 MHz, 5% tol, 150 mA
Murata LQG15HNR12J02B
26 16 L301, L302, L303, L304, L305, L306, L307, L308, L401, L402, L403, L404, L405, L406, L407, L408
Resistor 805 0 Ω, 1/8 W, 5% tol NIC Components
NRC10ZOTRF
27 1 OSC201 Oscillator SMT Clock oscillator, 65.00 MHz, 3.3 V
Valpey Fisher VFAC3H-L-65MHz
28 5 P101, P103, P105, P107, P201
Connector SMA Side-mount SMA for 0.063" board thickness
Johnson Components
142-0710-851
29 1 P202 Connector Header 1469169-1, right angle 2-pair, 25 mm, header assembly
Tyco 6469169-1
30 1 P503 Connector 0.1", PCMT SC1153, power supply connector
Switchcraft RAPC722X
31 15 R201, R205, R214, R215, R221, R239, R312, R315, R318, R411, R414, R417, R425, R429, R430
Resistor 402 10 kΩ, 1/16 W, 5% tol
NIC Components
NRC04J103TRF
32 14 R103, R117, R129, R142, R216, R217, R218, R223, R224, R237, R420, R426, R427, R428
Resistor 402 0 Ω, 1/16 W, 5% tol
NIC Components
NRC04Z0TRF
33 4 R102, R115, R128, R141 Resistor 402 64.9 Ω, 1/16 W, 1% tol
NIC Components
NRC04F64R9TRF
34 4 R104, R116, R130, R143 Resistor 603 0 Ω, 1/10 W, 5% tol
NIC Components
NRC06Z0TRF
35 15 R109, R111, R112, R123, R125, R126, R135, R138, R139, R148, R149, R150, R431, R432, R433
Resistor 402 1 kΩ, 1/16 W, 1% tol
NIC Components
NRC04F1001TRF
36 8 R108, R110, R121, R122, R134, R136, R146, R147
Resistor 402 33 Ω, 1/16 W, 5% tol
NIC Components
NRC04J330TRF
Data Sheet AD9219
Rev. E | Page 51 of 56
Item Qty. Reference Designator Device Package Value Manufacturer Manufacturer’s Part Number
37 4 R161, R162, R163, R164 Resistor 402 499 Ω, 1/16 W, 1% tol
NIC Components
NRC04F4990TRF
38 3 R202, R203, R204 Resistor 402 100 kΩ, 1/16 W, 1% tol
NIC Components
NRC04F1003TRF
39 1 R222 Resistor 402 4.02 kΩ, 1/16 W, 1% tol
NIC Components
NRC04F4121TRF
40 1 R213 Resistor 402 49.9 Ω, 1/16 W, 0.5% tol
Susumu RR0510R-49R9-D
41 1 R229 Resistor 402 4.99 kΩ, 1/16 W, 5% tol
NIC Components
NRC04F4991TRF
42 2 R230, R319 Potentiometer 3-lead 10 kΩ, cermet trimmer potentiometer, 18-turn top adjust, 10%, 1/2 W
BC Components
CT94EW103
43 1 R228 Resistor 402 470 kΩ, 1/16 W, 5% tol
NIC Components
NRC04J474TRF
44 1 R320 Resistor 402 39 kΩ, 1/16 W, 5% tol
NIC Components
NRC04J393TRF
45 8 R307, R308, R309, R310, R407, R408, R409, R410
Resistor 402 187 Ω, 1/16 W, 1% tol
NIC Components
NRC04F1870TRF
46 4 R305, R306, R405, R406 Resistor 402 374 Ω, 1/16 W, 1% tol
NIC Components
NRC04F3740TRF
47 4 R316, R317, R415, R416 Resistor 402 274 Ω, 1/16 W, 1% tol
NIC Components
NRC04F2740TRF
48 11 R245, R247, R249, R251, R253, R255, R257, R259, R261, R263, R265
Resistor 201 0 Ω, 1/20 W, 5% tol Panasonic ERJ-1GE0R00C
49 1 R418 Resistor 402 4.75 kΩ, 1/16 W, 1% tol
NIC Components
NRC04J472TRF
50 1 R419 Resistor 402 261 Ω, 1/16 W, 1% tol
NIC Components
NRC04F2610TRF
51 1 R501 Resistor 603 261 Ω, 1/16 W, 1% tol
NIC Components
NRC06F2610TRF
52 2 R240, R241 Resistor 402 243 Ω, 1/16 W, 1% tol
NIC Components
NRC04F2430TRF
53 2 R242, R243 Resistor 402 100 Ω, 1/16 W, 1% tol
NIC Components
NRC04F1000TRF
54 1 S401 Switch SMD Light touch, 100GE, 5 mm
Panasonic EVQ-PLDA15
55 5 T101, T102, T103, T104, T201
Transformer CD542 ADT1-1WT, 1:1 impedance ratio transformer
Mini-Circuits ADT1-1WT+
56 2 U501, U503 IC SOT-223 ADP3339AKC-1.8, 1.5 A, 1.8 V LDO regulator
Analog Devices ADP3339AKCZ-1.8
57 2 U301, U401 IC LFCSP, CP-32
AD8332ACP, ultralow noise precision dual VGA
Analog Devices AD8332ACPZ
58 1 U504 IC SOT-223 ADP3339AKC-5 Analog Devices ADP3339AKCZ-5
AD9219 Data Sheet
Rev. E | Page 52 of 56
Item Qty. Reference Designator Device Package Value Manufacturer Manufacturer’s Part Number
59 1 U502 IC SOT-223 ADP3339AKC-3.3 Analog Devices ADP3339AKCZ-3.3 60 1 U201 IC LFCSP,
CP-48-1 AD9219BCPZ-65, quad, 10-bit, 65 MSPS serial LVDS 1.8 V ADC
Analog Devices AD9219BCPZ-65
61 1 U203 IC SOT-23 ADR510ARTZ, 1.0 V, precision low noise shunt voltage reference
Analog Devices ADR510ARTZ
62 1 U202 IC LFCSP CP-32-2
AD9515BCPZ Analog Devices AD9515BCPZ
63 1 U403 IC SC70, MAA06A
NC7WZ07 Fairchild NC7WZ07P6X_NL
64 1 U404 IC SC70, MAA06A
NC7WZ16 Fairchild NC7WZ16P6X_NL
65 1 U402 IC 8-SOIC Flash prog mem 1k × 14, RAM size 64 × 8, 20 MHz speed, PIC12F controller series
Microchip PIC12F629-I/SN
1 This BOM is RoHS compliant.
Data Sheet AD9219
Rev. E | Page 53 of 56
OUTLINE DIMENSIONS
*COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2WITH EXCEPTION TO EXPOSED PAD DIMENSION.
FOR PROPER CONNECTION OFTHE EXPOSED PAD, REFER TOTHE PIN CONFIGURATION ANDFUNCTION DESCRIPTIONSSECTION OF THIS DATA SHEET.
148
1213
3736
2425
*5.555.50 SQ5.45
0.500.400.30
0.300.230.18
0.80 MAX0.65 TYP
5.50 REF
COPLANARITY0.08
EXPOSEDPAD
(BOTTOM VIEW)
0.20 REF
1.000.850.80 0.05 MAX
0.02 NOM
SEATINGPLANE
12° MAX
TOP VIEW
0.60 MAX
0.60 MAX
PIN 1INDICATOR 0.50
REF
PIN 1INDICATOR
0.22 MIN
7.107.00 SQ6.90
6.856.75 SQ6.65
02-2
3-20
10-C
Figure 82. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad (CP-48-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Notes Temperature Range Package Description
Package Option
AD9219ABCPZ-40 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-8 AD9219ABCPZRL7-40 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7” Tape and Reel CP-48-8 AD9219ABCPZ-65 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-8 AD9219ABCPZRL7-65 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7” Tape and Reel CP-48-8 AD9219-65EBZ 2 Evaluation Board 1 Z = RoHS Compliant Part. 2 Interposer board (HSC-ADC-FIFO5-INTZ) is required to connect to HSC-ADC-EVALCZ data capture board.
AD9219 Data Sheet
Rev. E | Page 54 of 56
NOTES
Data Sheet AD9219
Rev. E | Page 55 of 56
NOTES
AD9219 Data Sheet
Rev. E | Page 56 of 56
NOTES
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