l Q QProx™ QT60168, QT6024816, 24 KEY QMATRIX™ ICs

APPLICATIONSAutomotive panels

Machine toolsATM machinesTouch-screens

Appliance controlsOutdoor keypads

Security keypanelsIndustrial keyboards

These digital charge-transfer (“QT”) QMatrix™ ICs are designed to detect human touch on up to 16 or 24 keys when used with ascanned, passive X-Y matrix. They will project touch keys through almost any dielectric, e.g. glass, plastic, stone, ceramic, and evenwood, up to thicknesses of 5 cm or more. The touch areas are defined as simple 2-part interdigitated electrodes of conductive material,like copper or screened silver or carbon deposited on the rear of a control panel. Key sizes, shapes and placement are almost entirelyarbitrary; sizes and shapes of keys can be mixed within a single panel of keys and can vary by a factor of 20:1 in surface area. Thesensitivity of each key can be set individually via simple functions over the serial port by a host microcontroller. Key setups are storedin an onboard eeprom and do not need to be reloaded with each powerup.

These devices are designed specifically for appliances, electronic kiosks, security panels, portable instruments, machine tools, orsimilar products that are subject to environmental influences or even vandalism. They permit the construction of 100% sealed,watertight control panels that are immune to humidity, temperature, dirt accumulation, or the physical deterioration of the panel surfacefrom abrasion, chemicals, or abuse. To this end they contain Quantum-pioneered adaptive auto self-calibration, drift compensation, anddigital filtering algorithms that make the sensing function robust and survivable.

These devices feature continuous FMEA self-test and reporting diagnostics, to allow their use in critical consumer applianceapplications, for example ovens and cooktops.

Common PCB materials or flex circuits can be used as the circuit substrate; the overlying panel can be made of any non-conductingmaterial. External circuitry consists of only a few passive parts. Control and data transfer is via an SPI port.

These devices makes use of an important new variant of charge-transfer sensing, transverse charge-transfer, in a matrix format thatminimizes the number of required scan lines. Unlike older methods, it does not require one IC per key.

L Q Copyright © 2004 QRG LtdQT60248-AS R4.02/0405

Second generation charge-transfer QMatrix technologyKeys individually adjustable for sensitivity, responsetime, and many other critical parametersPanel thicknesses to 50mm through any dielectric16 and 24 touch key versions100% autocal for life - no adjustments requiredSPI slave interfaceAdjacent key suppression featureSynchronous noise suppression featureSpread-spectrum modulation - high noise immunityMix and match key sizes & shapes in one panelLow overhead communications protocolFMEA compliant design featuresNegligible external component countExtremely low cost per key+3 to +5V single supply operation32-pin lead-free TQFP package

X2 X1 X0

/RS

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2AY

1AY

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2B

X7

VR

EF

S_S

YN

CS

MP

DR

DY

/SS

MO

SI

MIS

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VSSVDDVSSVDD

X5X6 SCK

VDDSYNCVDDVSSn/cY0BY1B1

2345678 17

18192021222324

32 31 30 29 28 27 26 25

9 10 11 1615141312

QT60248QT60168

TQFP-32

YesQT60248-ASG24-400C to +1050CYesQT60168-ASG16-400C to +1050C

Lead-FreePart Number# KeysTA

AVAILABLE OPTIONS

134.8 Report Error Flags for All Keys - 0x0b . . . . . . . . . . . . . .13Table 4.1 Bits for key reporting and numbering . . . . . . . . . . . .134.7 Report Detections for All Keys - 0x07 . . . . . . . . . . . . . .134.6 Report 1st Key - 0x06 . . . . . . . . . . . . . . . . . . . . . .124.5 General Status - 0x05 . . . . . . . . . . . . . . . . . . . . . .124.4 Force Reset - 0x04 . . . . . . . . . . . . . . . . . . . . . . .124.3 Cal All - 0x03 . . . . . . . . . . . . . . . . . . . . . . . . . .124.2 Enter Setups Mode - 0x01 . . . . . . . . . . . . . . . . . . . .114.1 Null Command - 0x00 . . . . . . . . . . . . . . . . . . . . . .114 Control Commands . . . . . . . . . . . . . . . . . . . . . . .113.3 Command Error Handling . . . . . . . . . . . . . . . . . . . .103.2 SPI Communications . . . . . . . . . . . . . . . . . . . . . .103.1 DRDY Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Serial Communications . . . . . . . . . . . . . . . . . . . . .9Figure 2.7 Wiring Diagram . . . . . . . . . . . . . . . . . . . . . .8Table 2.2 - Pin Listing . . . . . . . . . . . . . . . . . . . . . . .82.17 Wiring . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72.16 FMEA Tests . . . . . . . . . . . . . . . . . . . . . . . . . .72.15 Detection Integrators . . . . . . . . . . . . . . . . . . . . . .72.14 Spread Spectrum Acquisitions . . . . . . . . . . . . . . . . .62.13 Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . .6Table 2-1 Basic Timings . . . . . . . . . . . . . . . . . . . . . .62.12 Startup / Calibration Times . . . . . . . . . . . . . . . . . . .62.11 Power Supply Considerations . . . . . . . . . . . . . . . . .62.10.2 PCB Cleanliness . . . . . . . . . . . . . . . . . . . . . . .62.10.1 LED Traces and Other Switching Signals . . . . . . . . . . . .62.10 PCB Layout, Construction . . . . . . . . . . . . . . . . . . .52.9 Key Design . . . . . . . . . . . . . . . . . . . . . . . . . . .52.8 Matrix Series Resistors . . . . . . . . . . . . . . . . . . . . .42.7 Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . .42.6 Sample Resistors . . . . . . . . . . . . . . . . . . . . . . . .42.5 Sample Capacitors; Saturation . . . . . . . . . . . . . . . . .42.4 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . .32.3 Response Time . . . . . . . . . . . . . . . . . . . . . . . . .32.2 Disabling Keys; Burst Paring . . . . . . . . . . . . . . . . . . .32.1 Matrix Scan Sequence . . . . . . . . . . . . . . . . . . . . . .32 Hardware & Functional . . . . . . . . . . . . . . . . . . . . .31.2 Enabling / Disabling Keys . . . . . . . . . . . . . . . . . . . .31.1 Part differences . . . . . . . . . . . . . . . . . . . . . . . . .31 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

277.3 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . .277.2 1-Sided Key Layout . . . . . . . . . . . . . . . . . . . . . . .267.1 8-Bit CRC Algorithm . . . . . . . . . . . . . . . . . . . . . . .267 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256.6 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246.5 Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . .246.4 Timing Specifications . . . . . . . . . . . . . . . . . . . . . .246.3 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . .246.2 Recommended operating conditions . . . . . . . . . . . . . . .246.1 Absolute Maximum Electrical Specifications . . . . . . . . . . .246 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .23Table 5.3 Setups Block Summary . . . . . . . . . . . . . . . . . .22Table 5.2 Key Mapping . . . . . . . . . . . . . . . . . . . . . . .22Table 5.1 Setups Block . . . . . . . . . . . . . . . . . . . . . . .215.13 Host CRC - HCRC . . . . . . . . . . . . . . . . . . . . . . .215.12 Lower Signal Limit - LSL . . . . . . . . . . . . . . . . . . . .205.11 Burst Spacing - BS . . . . . . . . . . . . . . . . . . . . . . .205.10 Mains Sync - MSYNC . . . . . . . . . . . . . . . . . . . . .205.9 Oscilloscope Sync - SSYNC . . . . . . . . . . . . . . . . . . .205.8 Adjacent Key Suppression - AKS . . . . . . . . . . . . . . . .205.7 Burst Length - BL . . . . . . . . . . . . . . . . . . . . . . . .195.6 Positive Recalibration Delay - PRD . . . . . . . . . . . . . . .195.5 Negative Recal Delay - NRD . . . . . . . . . . . . . . . . . . .195.4 Detect Integrators - NDIL, FDIL . . . . . . . . . . . . . . . . .185.3 Drift Compensation - NDRIFT, PDRIFT . . . . . . . . . . . . .185.2 Positive Threshold - PTHR . . . . . . . . . . . . . . . . . . .185.1 Negative Threshold - NTHR . . . . . . . . . . . . . . . . . . .185 Setups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Table 4.2 Command Summary . . . . . . . . . . . . . . . . . . . .144.18 Command Sequencing . . . . . . . . . . . . . . . . . . . . .144.17 Cal Key ‘k’ - 0xck . . . . . . . . . . . . . . . . . . . . . . . .144.16 Status for Key ‘k’ - 0x8k . . . . . . . . . . . . . . . . . . . .144.15 Data Set for One Key - 0x4k . . . . . . . . . . . . . . . . . .134.14 Internal Code - 0x12 . . . . . . . . . . . . . . . . . . . . . .134.13 Internal Code - 0x10 . . . . . . . . . . . . . . . . . . . . . .134.12 Return Last Command - 0x0f . . . . . . . . . . . . . . . . . .134.11 Eeprom CRC - 0x0e . . . . . . . . . . . . . . . . . . . . . .134.10 Dump Setups Block - 0x0d . . . . . . . . . . . . . . . . . . .134.9 Report FMEA Status - 0x0c . . . . . . . . . . . . . . . . . . .

lQ 2 QT60248-AS R4.02/0405

Contents

1 OverviewQMatrix devices are digital burst mode charge-transfer (QT)sensors designed specifically for matrix geometry touchcontrols; they include all signal processing functions necessaryto provide stable sensing under a wide variety of changingconditions. Only a few external parts are required for operation.The entire circuit can be built within a few square centimeters ofsingle-sided PCB area. CEM-1 and FR1 punched, single-sidedmaterials can be used for possible lowest cost. The PCB’s rearcan be mounted flush on the back of a glass or plastic panelusing a conventional adhesive, such as 3M VHB 2-sidedadhesive acrylic film.

QMatrix parts employ transverse charge-transfer ('QT') sensing,a technology that senses changes in electrical charge forcedacross an electrode by a pulse edge (Figure 1-1). QMatrixdevices allow for a wide range of key sizes and shapes to bemixed together in a single touch panel.

The devices use an SPI interface to allow key data to beextracted and to permit individual key parameter setup. Theinterface protocol uses simple single byte commands andresponds with single byte responses in most cases. Thecommand structure is designed to minimize the amount of datatraffic while maximizing the amount of information conveyed.

In addition to normal operating and setup functions the devicecan also report back actual signal strengths and error codes.

QmBtn software for the PC can be used to program theoperation of the IC as well as read back key status and signallevels in real time.

The QT60168 and QT60248 are electrically identical with theexception of the number of keys which may be sensed.

1.1 Part differencesVersions of the device are capable of a maximum of 16 or 24keys (QT60168, QT60248 respectively).

These devices are identical in all respects, except that each iscapable of only the number of keys specified. These keys canbe located anywhere within the electrical grid of 8 X and 3 Yscan lines.

Unused keys are always pared from the burst sequence inorder to optimize speed. Similarly, in a given part a lessernumber of enabled keys will cause any unused acquisition bursttimeslots to be pared from the sampling sequence to optimizeacquire speed. Thus, if only 14 keys are actually enabled, only14 timeslots are used for scanning.

1.2 Enabling / Disabling KeysThe NDIL parameter is used to enable and disable keys in thematrix. Setting NDIL = 0 for a key disables it (Section 5.4). Atno time can the number of enabled keys exceed the maximumspecified for the device in the case of the QT60168.

On the QT60168, only the first 2 Y lines (Y0, Y1) areoperational by default. On the QT60168, to use keys located online Y2, one or more of the pre-enabled keys must be disabledsimultaneously while enabling the desired new keys. This canbe done in one Setups block load operation.

2 Hardware & Functional2.1 Matrix Scan SequenceThe circuit operates by scanning each key sequentially, key bykey. Key scanning begins with location X=0 / Y=0 (key #0). Xaxis keys are known as rows while Y axis keys are referred toas columns. Keys are scanned sequentially by row, for examplethe sequence X0Y0 X1Y0 .... X7Y0, X0Y1, X1Y1... etc. Keys arealso numbered from 0..24. Key 0 is located at X0Y0. A table ofkey numbering is located on page 22.

Each key is sampled in a burst of acquisition pulses whoselength is determined by the Setups parameter BL (page 20),which can be set on a per-key basis. A burst is completedentirely before the next key is sampled; at the end of each burstthe resulting signal is converted to digital form and processed.The burst length directly impacts key gain; each key can have aunique burst length in order to allow tailoring of key sensitivityon a key by key basis.

2.2 Disabling Keys; Burst ParingKeys that are disabled by setting NDIL =0 (Section 5.4, page19) have their bursts pared from the scan sequence to savetime. This has the consequence of affecting the scan rate of theentire matrix as well as the time required for initial matrixcalibration.

Reducing the number of enabled keys also reduces the timerequired to calibrate an individual key once the matrix is initiallycalibrated after power-up or reset, since the total cycle time isproportional to the number of enabled keys.

Keys that are disabled report as follows:

Signal = 0Reference = 0Low-signal error flag (provided LSL >0)Calibrating flag for key set only just after device reset or

after a CAL command, for one scan cycle onlyFailed calibration error for key always setDetect flag for key never set

See also Section 4.16 notes.

2.3 Response TimeThe response time of the device depends on the scan rate ofthe keys (Section 5.11), the number of keys enabled (Section5.4), the detect integrator settings (Section 5.4), the serialpolling rate by the host microcontroller, and the time required todo FMEA tests at the end of each scan (~5ms).

lQ 3 QT60248-AS R4.02/0405

Figure 1-1 Field flow between X and Y elements

overlying panel

Xelement

Yelement

For example:

NKE = Number of keys enabled = 20FDIL = Fast detect integrator limit = 5BS = Burst spacing = 0.5msFMEA = FMEA test time = 5msNDIL = Norm detect integrator Limit = 2HPR = Host polling rate = 10ms

The worst case response time is computed as:

Tr = ((((NKE + FDIL) * BS) + FMEA) * NDIL) + HPR

For the above example values:

Tr = ((((20 + 5) * 0.5ms) + 5ms) * 2) + 10ms = 45ms

2.4 OscillatorThe oscillator is internal to the device. There is no facility forexternal clocking.

2.5 Sample Capacitors; SaturationThe charge sampler capacitors on the Y pins should be thevalues shown. They should be X7R or NP0 ceramics or PPSfilm. The value of these capacitors is not critical but 4.7nF isrecommended for most cases.

Cs voltage saturation is shown in Figure 2-1. This nonlinearityis caused by excessively negative voltage on Cs inducingconduction in the pin protection diodes. This badly saturatedsignal destroys key gain and introduces a strong thermalcoefficient which can cause 'phantom' detection. The cause ofthis is usually from the burst length being too long, the Cs valuebeing too small, or the X-Y coupling being too large. Solutionsinclude loosening up the interdigitation of key structures,separating X and Y lines on the PCB more, increasing Cs, anddecreasing the burst length.

Increasing Cs will make the part slower; decreasing burstlength will make it less sensitive. A better PCB layout and alooser key structure (up to a point) have no negative effects.

Cs voltages should be observed on an oscilloscope with thematrix layer bonded to the panel material; if the Rs side of anyCs ramps more negative than -0.25 volts during any burst (notcounting overshoot spikes which are probe artifacts), there is apotential saturation problem.

Figure 2-2 shows a defective waveform similar to that of 2-1,but in this case the distortion is caused by excessive straycapacitance coupling from the Y line to AC ground, for examplefrom running too near and too far alongside a ground trace,ground plane, or other traces. The excess coupling causes thecharge-transfer effect to dissipate a significant portion of thereceived charge from a key into the stray capacitance. Thisphenomenon is more subtle; it can be best detected byincreasing BL to a high count and watching what the waveformdoes as it descends towards and below -0.25V. The waveformwill appear deceptively straight, but it will slowly start to flatteneven before the -0.25V level is reached.

A correct waveform is shown in Figure 2-3. Note that thebottom edge of the bottom trace is substantially straight(ignoring the downward spikes).

Unlike other QT circuits, the Cs capacitor values on QT60xx8devices have no effect on conversion gain. However they doaffect conversion time.

Unused Y lines should be left open.

2.6 Sample ResistorsThere are 3 sample resistors (Rs) used to perform single-slopeADC conversion of the acquired charge on each Cs capacitor.These resistors directly control acquisition gain: larger values ofRs will proportionately increase signal gain. Values of Rs canrange from 380K ohms to 1M ohms. 470K ohms is areasonable value for most purposes.

Unused Y lines do not require an Rs resistor.

2.7 Signal LevelsQuantum’s QmBtn™ software makes it is easy to observe theabsolute level of signal received by the sensor on each key.The signal values should normally be in the range from 250 to750 counts with properly designed key shapes and values ofRs. However, long adjacent runs of X and Y lines can alsoartificially boost the signal values, and induce signal saturation:this is to be avoided. The X-to-Y coupling should come mostlyfrom intra-key electrode coupling, not from stray X-to-Y tracecoupling.

QmBtn software is available free of charge on Quantum’swebsite.

The signal swing from the smallest finger touch shouldpreferably exceed 10 counts, with 15 being a reasonable target.The signal threshold setting (NTHR) should be set to a valueguaranteed to be less than the signal swing caused by thesmallest touch.

lQ 4 QT60248-AS R4.02/0405

Figure 2-1 VCs - Non-Linear During Burst(Burst too long, or Cs too small, or X-Y capacitance too large)

Figure 2-2 VCs - Poor Gain, Non-Linear During Burst(Excess capacitance from Y line to Gnd)

Figure 2-3 Vcs - Correct

Increasing the burst length (BL) parameter will increase thesignal strengths as will increasing the sampling resistor (Rs)values.

2.8 Matrix Series ResistorsThe X and Y matrix scan lines should use series resistors(referred to as Rx and Ry respectively) for improved EMIperformance.

X drive lines require them in most cases to reduce edge ratesand thus reduce RF emissions. Typical values range from 1K to20K ohms.

Y lines need them to reduce EMC susceptibility problems and insome extreme cases, ESD. Typical Y values range around 1Kohms. Y resistors act to reduce noise susceptibility problems byforming a natural low-pass filter with the Cs capacitors.

It is essential that the Rx and Ry resistors and Cs capacitors beplaced very close to the chip. Placing these parts more than afew millimeters away opens the circuit up for high frequencyinterference problems (above 20MHz) as the trace lengthsbetween the components and the chip start to act as RFantennae.

The upper limits of Rx and Ry are reached when the signallevel and hence key sensitivity are clearly reduced. The limits ofRx and Ry will depending on key geometry and straycapacitance, and thus an oscilloscope is required to determineoptimum values of both.

The upper limit of Rx can vary depending on key geometry andstray capacitance, and some experimentation and anoscilloscope are required to determine optimum values.

Dwell time is the duration in which charge coupled from X to Yis captured. Increasing Rx values will cause the leading edge ofthe X pulses to increasingly roll off, causing the loss of capturedcharge (and hence loss of signal strength) from the keys(Figure 2-4). The dwell time of these parts is fixed at 375ns. Ifthe X pulses have not settled within 375ns, key gain will bereduced; if this happens, either the stray capacitance on the Xline(s) should be reduced (by a layout change, for example byreducing X line exposure to nearby ground planes or traces), or,the Rx resistor needs to be reduced in value (or a combinationof both approaches).

One way to determine X line settling time is to monitor the fieldsusing a patch of metal foil or a small coin over the key (Figure2-5). Only one key along a particular X line needs to beobserved, as each of the keys along that X line will be identical.The 250ns dwell time should be exceed the observed 95%settling of the X-pulse by 25% or more.

In almost all case, Ry should be set equal to Rx, which willensure that the charge on the Y line is fully captured into the Cscapacitor.

2.9 Key DesignCircuits can be constructed out of a variety of materialsincluding flex circuits, FR4, and even inexpensive single-sidedCEM-1.

The actual internal pattern style is not as important as is theneed to achieve regular X and Y widths and spacings ofsufficient size to cover the desired graphical key area or a littlebit more; ~3mm oversize is acceptable in most cases, since thekey’s electric fields drop off near the edges anyway. The overallkey size can range from 10mm x 10mm up to 100mm x 100mmbut these are not hard limits. The keys can be any shapeincluding round, rectangular, square, etc. The internal pattern

lQ 5 QT60248-AS R4.02/0405

Figure 2-4 X-Drive Pulse Roll-off and Dwell Time

Figure 2-5 Probing X-Drive Waveforms With a Coin

X drive Lost charge due toinadequate settlingbefore end of dwell time

Y gate

Dwell time

Figure 2-6 Recommended Key Structure ‘T’ should ideally be similar to the complete thickness the fields need topenetrate to the touch surface. Smaller dimensions will also work but will giveless signal strength. If in doubt, make the pattern coarser.

can be as simple as a single bar of Y within a solid perimeter ofX, or (preferably) interdigitated as shown in Figure 2-6.

For better surface moisture suppression, the outer perimeter ofX should be as wide as possible, and there should be noground planes near the keys. The variable ‘T’ in this drawingrepresents the total thickness of all materials that the keys mustpenetrate.

See Figure 2-6 and page 27 for examples of key layouts.

See Section 2.16 for guidance about potential FMEA problemswith small key shapes.

2.10 PCB Layout, Construction It is best to place the chip near the touch keys on the samePCB so as to reduce X and Y trace lengths, thereby reducingthe chances for EMC problems. Long connection traces act asRF antennae. The Y (receive) lines are much more susceptibleto noise pickup than the X (drive) lines.

Even more importantly, all signal related discrete parts (R’s andC’s) should be very close to the body of the chip. Wiringbetween the chip and the various R’s and C’s should be asshort and direct as possible to suppress noise pickup.

Ground planes and traces should NOTbe used around the keys and the Y linesfrom the keys. Ground areas, traces, andother adjacent signal conductors that actas AC ground (such as Vdd and LED

drive lines etc) will absorb the received key signalsand reduce signal-to-noise ratio (SNR) and thus willbe counterproductive. Ground planes around keys willalso make water film effects worse.

Ground planes, if used, should be placed under or around theQT chip itself and the associated R’s and C’s in the circuit,under or around the power supply, and back to a connector, butnowhere else.

See page 27 for an example of a 1-sided PCB layout.

2.10.1 LED Traces and Other Switching SignalsDigital switching signals near the Y lines will induce transientsinto the acquired signals, deteriorating the SNR perfomance ofthe device. Such signals should be routed away from the Ylines, or the design should be such that these lines are notswitched during the course of signal acquisition (bursts).

LED terminals which are multiplexed or switched into a floatingstate and which are within or physically very near a keystructure (even if on another nearby PCB) should be bypassedto either Vss or Vdd with at least a 10nF capacitor of any type,to suppress capacitive coupling effects which can induce falsesignal shifts. Led terminals which are constantly connected toVss or Vdd do not need further bypassing.

2.10.2 PCB CleanlinessAll capacitive sensors should be treated as highly sensitivecircuits which can be influenced by stray conductive leakagepaths. QT devices have a basic resolution in the femtofaradrange; in this region, there is no such thing as ‘no clean flux’.Flux absorbs moisture and becomes conductive between

solder joints, causing signal drift and resultant false detectionsor transient losses of sensitivity or instability. Conformalcoatings will trap in existing amounts of moisture which will thenbecome highly temperature sensitive.

The designer should specify ultrasonic cleaning as part of themanufacturing process, and in cases where a high level ofhumidity is anticipated, the use of conformal coatings aftercleaning to keep out moisture.

2.11 Power Supply ConsiderationsAs these devices use the power supply itself as an analogreference, the power should be very clean and come from aseparate regulator. A standard inexpensive LDO type regulatorshould be used that is not also used to power other loads suchas LEDs, relays, or other high current devices. Load shifts onthe output of the LDO can cause Vdd to fluctuate enough tocause false detection or sensitivity shifts.

A single ceramic 0.1uF bypass capacitor should be placed veryclose to supply pins 3, 4, 5 and 6 of the IC. Pins 18, 20, and 21do not require bypassing.

Vdd can range from +3 to +5 nominal. The device enters resetbelow 2.8V via an internal LVD circuit. See Section 2.13.

2.12 Startup / Calibration TimesThe devices require initialization times as follows:

Normal cold start to ability to communicate:

4ms - Normal initialization from any type of reset

22ms - Initialization from reset where the Setups werepreviously modified.

Calibration time per key vs. burst spacings for 16 and 24enabled keys:

1,0407283.009596732.758786182.507975632.257155072.006344521.755533971.504723421.253902861.003092310.752281760.50

Cal Time, ms,24 keys

Cal Time, ms,16 keys

Burst Spacing, ms

Table 2-1 Basic Timings

To the above, add the initialization time from above (4ms or22ms) to get the total elapsed time from reset, to the ability toreport key detections over the serial interface. Disabled keysare subtracted from the burst sequence and thus the cal time isshortened. The scan time should be measured on anoscilloscope.

Keys that cannot calibrate for some reason require 5 full calcycles before they report as errors. The device can report backduring the calibration interval that the key(s) affected are still incalibration via status function bits. Errors can be observed aftera cal cycle using the 0x8k command (see Section 4.16).

2.13 Reset InputThe /RST pin can be used to reset the device to simulate apower down cycle, in order to bring the part up into a known

lQ 6 QT60248-AS R4.02/0405

state should communications with the part be lost. The pin isactive low, and a low pulse lasting at least 10µs must beapplied to this pin to cause a reset.

To provide for proper operation during power transitions thedevices have an internal LVD set to 2.7 volts.

The reset pin has an internal 30K ~ 80K resistor. A 2.2µFcapacitor plus a diode to Vdd can be connected to this pin as atraditional reset circuit, but this is not required.

A Force Reset command, 0x04 is also provided whichgenerates an equivalent hardware reset.

If an external hardware reset is not used, the reset pin may beconnected to Vdd or left floating.

2.14 Spread Spectrum AcquisitionsQT60xx8 devices use spread-spectrum burst modulation. Thishas the effect of drastically reducing the possibility of EMIeffects on the sensor keys, while simultaneously spreading RFemissions. This feature is hard-wired into the device andcannot be disabled or modified.

Spread spectrum is configured as a frequency chirp over awide range of frequencies for robust operation.

2.15 Detection IntegratorsSee also Section 5.4, page 19.

The devices feature a detection integration mechanism, whichacts to confirm a detection in a robust fashion. The basic idea isto increment a per-key counter each time the key has crossedits threshold. When this counter reaches a preset limit the keyis finally declared to be touched. Example: If the limit value is10, then the device has to detect a threshold crossing 10 timesin succession without interruption, before the key is declared tobe touched. If on any sample the signal is not seen to cross thethreshold level, the counter is cleared and the process has tostart over from the beginning.

The QT60xx8 uses a two-tier confirmation mechanism havingtwo such counters for each key. These can be thought of as‘inner loop’ and ‘outer loop’ confirmation counters.

The ‘inner’ counter is referred to as the ‘fast-DI’; this acts toattempt to confirm a detection via rapid successive acquisitionbursts, at the expense of delaying the sampling of the next key.Each key has its own fast-DI counter and limit value; theselimits can be changed via the Setups block on a per-key basis.

The ‘outer’ counter is referred to as the ‘normal-DI’; this DIcounter increments whenever the fast-DI counter has reachedits limit value. If a fast-DI counter failed to reach its terminalcount, the corresponding normal-DI counter is also reset. Thenormal-DI counter also has a limit value which is settable on aper-key basis. If a normal-DI counter reaches its terminal count,the corresponding key is declared to be touched and becomes‘active’. Note that the normal-DI can only be incremented onceper complete keyscan cycle, ie more slowly, whereas thefast-DI is incremented ‘on the spot’ without interruption.

The net effect of this mechanism is a multiplication of the innerand outer counters and hence a highly noise-resistancesensing method. If the inner limit is set to 5, and the outer to 3,the net effect is 5x3=15 successive threshold crossings todeclare a key as active.

2.16 FMEA TestsFMEA (Failure Modes and Effects Analysis) is a tool used todetermine critical failure problems in control systems. FMEA

analysis is being applied increasingly to a wide variety ofapplications including domestic appliances. To survive FMEAtesting the control board must survive any single problem in away that the overall product can either continue to operate in asafe way, or shut down.

The most common FMEA requirements regard opens andshorts analysis of adjacent pins on components andconnectors. However other criteria must usually be taken intoaccount, for example complete device failure, and the use ofredundant signaling paths.

QT60xx8 devices incorporate special self-test features whichallow products to pass such FMEA tests easily. These tests areperformed during a dummy timeslot after the last enabled key.

The FMEA testing is done on all enabled keys in the matrix, andresults are reported via the serial interface through a dedicatedstatus command (page 13). Disabled keys are not tested. Theexistence of an error is also reported in normal key reportingcommands such as Report 1st Key, page 13.

All FMEA tests are repeated every second or faster duringnormal run operation. Sometimes, FMEA errors can occur intermittently, for example due to momentary powerfluctuations. It is advisable to confirm a true FMEA faultcondition by making sure the error flags persist for a severalseconds.

Since the devices only communicate in slave mode, the hostcan determine immediately if the QT has suffered acatastrophic failure.

The FMEA tests performed are:

X drive line shorts to Vdd and Vss

X drive line shorts to other pins

X drive signal deviation

Y line shorts to Vdd and Vss

Y line shorts to other pins

X to Y line shorts

Cs capacitor checks including shorts and opens

Vref test

Key gain test

Other tests incorporated into the devices include:

A test for signal levels against a preset min value (LSLsetup, see page 21). If any signal level falls below thislevel, an error flag is generated.

CRC communications checks on all critical command anddata transmissions.

‘Last-command’ command to verify that an instruction wasproperly received.

Some very small key designs have very low X-Y coupling. Inthese cases, the amount of signal will be very small, and thekey gain will be low. As a result, small keys can fail the LSLtest (page 21) or the FMEA key gain test (above). In suchcases, the burst length of the key should be increased so thatthe key gain increases. Failing that, a small ceramic capacitor,for example 3pF, can be added between the X and Y linesserving the key to artificially boost signal strength.

For those applications requiring it, Quantum can supply sampleFMEA test data on special request.

lQ 7 QT60248-AS R4.02/0405

2.17 WiringTable 2.2 - Pin Listing

Leave openX2 matrix drive lineOX232Leave openX1 matrix drive lineOX131Leave openX0 matrix drive lineOX030

Leave open or VddReset low; has internal 30K ~ 80K pull-upI/RST29

Y2A line connectionIY2A28Leave open

Y1A line connectionIY1A27Y0A line connectionIY0A26

Leave openY2B line connectionIY2B25Y1B line connectionIY1B24

Leave openY0B line connectionIY0B23

Leave openNot usedN/ANC22-Supply groundPVss21-Power, +3 ~ +5VPVdd20

VddMains sync inputISYNC19-Power, +3 ~ +5VPVdd18-SPI clock inputISCK17-SPI data outputOMISO16-SPI data inputIMOSI15

-SPI slave select; has internal 20K ~ 50K pull-upI/SS14

-1= Comms ready; has internal 20K ~ 50K pull-upODRDY13

-Sample drive outputOSMP12Leave openScope Sync: Synchronization test signal outputOS_Sync11

-0.05V nominal +/-10% via external dividerIVref10Leave openX7 matrix drive lineOX79Leave openX6 matrix drive lineOX68Leave openX5 matrix drive lineOX57

-Power, +3 ~ +5VPVdd6-Supply groundPVss5-Power, +3 ~ +5VPVdd4-Supply groundPVss3

Leave openX4 matrix drive lineOX42Leave openX3 matrix drive lineOX31

If Unused, Connect To..CommentsI/OFunctionPin

lQ 8 QT60248-AS R4.02/0405

Figure 2.7 Wiring DiagramSee Table 2.2 for further connection information.

lQ 9 QT60248-AS R4.02/0405

+

MA

TR

IX Y

SC

AN

IN

MA

TR

IX X

DR

IVE

MISO

MOSI

DRDY

Note 1

SS

SCLK

+

10K

100

RS2

470K

RS0

470K

1KRX2

1KRX6

1KRY1

1KRY2

1KRY0

1KRX0

1KRX4

Vunreg +3 to +5V VREG

VDD

QT60248QT60168

100nF

LINE SYNC

SCOPE SYNC

Note 2

Note 2

VDD

SP

I

4.7uF 4.7uF

RS1

470K

Note 1: Wire 100nF bypass cap very close to pins 3, 4, 5, 6

Note 2: Leave Y2A, Y2B unconnected for QT60168

CS1 4.7nF

1KRX1

1KRX3

1KRX7

CS2 4.7nF

4.7nFCS0

1KRX5

3 Serial CommunicationsThese devices use SPI communications, in slave mode.

The host device always initiates communications sequences;the QT is incapable of chattering data back to the host. This isintentional for FMEA purposes so that the host always has totalcontrol over the communications with the QT60xx8. In SPImode the device is a slave, so that even return data following acommand is controlled by the host.

A command from the host always ends in a response of somekind from the QT. Some transmission types from the host or theQT employ a CRC check byte to provide for robustcommunications.

A DRDY line is provided that handshakes transmissions.Generally this is needed by the host from the QT to ensure thattransmissions are not sent when the QT is busy or has not yetprocessed a prior command.

Initiating or Resetting Communications: After a reset, or,should communications be lost due to noise or out-of-sequencereception, the host should send a 0x0f (return last command)command repeatedly until the compliment of 0x0f, i.e. 0xf0, isreceived back. Then, the host can resume normal run modecommunications from a clean start.

Poll rate: The typical poll rate in normal ‘run’ operation shouldbe no faster than once per 10ms; 25ms is more than fastenough to extract status data using the 0x06 command (reportfirst key: see page 13) in most situations. Streaming multi-byteresponse commands like the 0x0d command (dump setups: seepage 13) or multi-byte response commands like 0x07 can andshould pace at the maximum possible rate.

Run Poll Sequence: In normal run mode the host should limittraffic with a minimalist control structure (see also Section 4.18).The host should just send a 0x06 command until somethingrequires a deeper state inspection. If there is more than one keyin detect, the host should use 0x07 to find which additional keysare in detect. If there is an error, the host should ascertain theerror type based on commands 0x0b and 0x0c and takeappropriate action. Issuing a 0x07 command all the time iswasteful of bandwidth, requires more host processor time, andactually conveys less information (no error flags are sent via a0x07 command).

3.1 DRDY PinDRDY is an open-drain output with an internal 20K ~ 50K pullupresistor.

Serial communications pacing is controlled by this pin. The hostis permitted to send data only when DRDY is high. After a byteis received DRDY will always go low even if only for a fewmicroseconds; during this period the host should not send data.Therefore, after each byte transmission the host should firstcheck that DRDY is high again.

If the host desires to send a byte to the QT it should behave asfollows:

1. If DRDY is low, wait2. If DRDY is high: send a command to QT3. Wait at least 40µs (time S5 in Figure 3-3: DRDY is

guaranteed to go low before this 40µs expires)4. Wait until DRDY is high (it may already be high again)5. Send next command or a null byte 0x00 to QT

The time it takes for DRDY to go high again after a commanddepends on the command. Following is a list of commands andthe time required to process them and then raise DRDY:

0x0E Eeprom CRC [ 25ms0x01 Load Setups [ 25msAll other commands: [ 2ms between bytes;

[ 40µs after CRC byte is sent

Other DRDY specs:

Min time DRDY is low: 1µsMin time DRDY is low

after reset: 1ms

3.2 SPI CommunicationsSPI communications operates in slave mode only, and obeysDRDY control signaling. The clocking is as follows:

Clock idle: HighClock shift out edge: FallingClock data in edge: RisingMax clock rate: 1.5MHz

SPI mode requires 5 signals to operate:

MOSI - Master out / Slave in data pin; used as an input fordata from the host (master). This pin should be connectedto the MOSI (DO) pin of the host device.

MISO - Master in / Slave out data pin; used as an output fordata to the host. This pin should be connected to the MISO

lQ 10 QT60248-AS R4.02/0405

Figure 3-2 Filtered SPI Connections

MOSI

MISO

SCK

DRDY

SS

QT60xx8 Circuit

Ra1K

Ra

Ra

Ra

Ra

RESET1K

Host MCU

1K

Yn

Xn

X drives(1 of 8

shown)

Y Lines(1 of 3

shown)

Ca

Ca

Ca

Ca

Ca

1nF

SCK

MISO

MOSI

P_IN

P_OUT1

P_OUT2

1nF2,20050kHz470pF2,200100kHz270pF1,000400kHz100pF6801.5MHz

CaRaSPI Clock RateRecommended Values of Ra & Ca

Figure 3-1 Basic SPI Connections

MOSI MOSIMISOMISO

SCK SCK

DRDYP_OUT

P_INSS

Host MCU QT60xx8

(DI) pin of the host. MISO floats when /SS is high to allowmulti-drop communications along with other slave parts.

SCK - SPI clock - input only clock from host. The host mustshift out data on the falling SCK edge; the QT60xx8 clocksdata in on the rising edge. The QT60xx8 likewise shifts dataout on the falling edge of SCK back to the host so that thehost can shift the data in on the rising edge. Important:SCK must idle high; it should never float.

/SS - Slave select - input only; acts as a framing signal to thesensor from the host. /SS must be low before and duringreception of data from the host. It must not go high againuntil the SCK line has returned high; /SS must idle high.This pin includes an internal pull-up resistor of 20K ~ 50K.When /SS is high, MISO floats.

DRDY - Data Ready - active-high - indicates to the host thatthe QT is ready to send or receive data. This pin idles high.This pin includes an internal pull-up resistor of 20K ~ 50K.In SPI mode this pin is an output only (i.e. open drain withinternal pull-up).

The MISO pin on the QT floats in 3-state mode between byteswhen /SS is high. This facilitates multiple devices on one SPIbus.

Null Bytes: When the QT responds to a command with one ormore response bytes, the host should issue a null commands(0x00) to get the response bytes back. The host should notsend new commands until all the responses are accepted backfrom the QT from the prior command via nulls.

New commands attempted during intermediate byte transfersare ignored.

SPI Line Noise: In some designs it is necessary to run SPIlines over ribbon cable across a lengthy distance on a PCB.This can introduce ringing, ground bounce, and other noiseproblems which can introduce false SPI clocking or false data.Simple RC networks and slower data rates as shown in Figure3-2 are helpful to resolve these issues.

CRC checks have been added to critical commands in order todetect transmission errors to a high level of certainty.

3.3 Command Error HandlingIf an unrecognized command is received, the device will releaseDRDY high and the communications error flag will be set in theGeneral Status byte (see Section 4.5).

4 Control CommandsRefer to Table 4.2, page 16 for further details.

The devices feature a set of commands which are used forcontrol and status reporting. The host device has to send thecommand to the QT60xx8 and await a response.

SPI mode: While waiting the host should delay for 40µs fromthe end of the command, then start to check if DRDY is or goeshigh. If it is high, then the host master can clock out theresulting byte(s).

Command timeouts: Where a command involves multi-bytetransfers in either direction, each byte must be transmittedwithin 100ms of the prior byte or the command will timeout. Noerror is reported for this condition; the command simply ceases.

Word return byte order: Where a word or long word isreturned (16 or 24 bit number or bit pattern) the low order byteis sent or received first.

4.1 Null Command - 0x00Used to shift back data from the QT. Since the host device isalways the master in SPI mode, and data is clocked in bothdirections, the Null command is required frequently to act as aplaceholder where the desire is to only get data back from theQT, not to send a command.

In SPI communications, when the QT60xx8 responds to acommand with one or more response bytes, the host can issuea new command instead of a null on the last byte shiftoperation.

New commands during intermediate byte shift-out operationsare ignored, and null bytes should always be used.

lQ 11 QT60248-AS R4.02/0405

Figure 3-3 SPI Slave-Only Mode Timing

S1: m333ns S2: [20ns S3: m25ns S4: [20nsS5: [40µs S6: m1µs S7: m333ns S8: m333ns S9: m667ns

S6

high via pullup-RDRDY

(from QT)

S1 S5

/SS (from Host)

S3

CLK (from Host)

MOSI(Data from Host)

MISO 3-state 3-state(Data from QT)

02367 12 1 0 45

45 01237 6 5 672 1 0 ?? 4 3

5 4 3

?

0 7 6? 7 6 5 4 3 2 1

7 6 5 4 3 2 1 0

S7

S9

S8

Data shifts out of QT on falling edge

data response

{optional 2nd command byte} {null byte or next command to get QT response}

Data shifts in to QT on rising edge

{Command byte} S4S2

4.2 Enter Setups Mode - 0x01This command is used to initiate the Setups block transfer fromHost to QT.

The command must be repeated 2x within 100ms or thecommand will fail; the repeating command must be sequentialwithout any intervening command. After the 2nd 0x01 from thehost, the QT will stop scanning keys and reply with thecharacter 0xFE. In SPI mode this character must be shifted outby sending a null (0x00) from the host. This commandsuspends normal sensing starting from the receipt of thesecond 0x01. A failure of the command will cause a timeout.

Each byte in the block must arrive at the QT no later than100ms after the previous one or a timeout will occur.

Any timeout will cause the device to cancel the block load andgo back to normal operation.

If no response comes back, the command was not received andthe device should preferably be reset from the host by hardwarereset just in case there are any other problems.

If 0xFE is received by the host, then the host should begin totransmit the block of Setups to the QT. DRDY handshakes thedata. The delay between bytes can be as short as 10µs but thehost can make it longer than this if required, but no more than100ms. The last byte the host should send is the CRC for theblock of data only, ie the command itself should not be foldedinto the CRC.

After the block transfer the QT will check the CRC and respondwith 0x00 if there was an error. Regardless, it will program theinternal eeprom. If the CRC was correct it will reply with asecond 0xFE after the eeprom was programmed.

At the end of the full block load sequence, the device restartssensing without recalibration. It is highly recommended thatthe part be reset after a block load to allow the part toproperly initialize itself, clear any setup flags, using the resetcommand or the reset pin.

4.3 Cal All - 0x03This command must be repeated 2x within 100ms or thecommand will fail; the repeating command must be sequentialwithout any intervening command.

After the 2nd 0x03 from the host, the QT will reply with thecharacter 0xFC. Shortly thereafter the device will recalibrate allkeys and restart operation.

If no 0xFC comes back, the command was not properlyreceived and the device should preferably be reset.

The host can monitor the progress of the recalibration bychecking the status byte, using command 0x05.

A key will show an error flag (via command 0x8k) indicating thekey has failed calibration if its signal is too noisy or if its signal isbelow the low signal threshold. A key is deemed too noisy if, atthe end of calibration, the signal is no longer between itscomputed negative hysteresis level and positive thresholds.

4.4 Force Reset - 0x04The command must be repeated 2x within 100ms or thecommand will fail; the repeating command must be sequentialwithout any intervening command. After the 2nd 0x04, the QTwill reply with the character 0xFB just prior to executing thereset operation.

The host can monitor the progress of the reset by checking thestatus byte for recalibration, using command 0x05. Thecomplete reset sequence is as follows:

1. Reset command received by QT2. Response byte (0xFB) recovered by host3. DRDY floats high4. 20ms elapses until device completes reset5. DRDY clamped low6. 4ms or 22ms elapses - (see Section 2.12)7. DRDY floats high again - device reset has completed

If the host does not recover the response byte in step 2, theQT device will self-reset within 2 seconds.

4.5 General Status - 0x05This command returns the general status bits. They are asfollows:

1= any key in detect01= any key in calibration1

1= calibration has failed on anenabled key or, an LSL failure

21= mains sync error3Reserved41= FMEA failure detected51= communications error6Reserved7DescriptionBIT

Notes:

Bit 7: Reserved

Bit 6: Set if a communications failure, such as an unrecognizedcommand. This bit can be reset by sending command 0x0f(“last command command”) repeatedly until a response of 0xf0is received.

Bit 5: Set if an FMEA error was detected during operation. SeeSection 2.16. A further amplification of what the FMEA errorconsisted of is described in Section 4.9.

Bit 4: Reserved

Bit 3: Set if there was a mains sync error, for example therewas no Sync signal detected within the allotted 100ms amountof time. See Section 5.10. This condition is not necessarily fatalto operation, however the device will operate very slowly andmay suffer from noise problems if the sync feature was requiredfor noise reasons.

Bit 2: Reports either a cal failure (failed in 5 sequentialattempts) on any enabled key or, that an enabled key has avery low signal reference value, lower than the user-settableLSL value (Section 5.12). Disabled keys do not cause this bit 2error flag to be set even if they generate an error flag in the0x8k response.

Bit 1: Set if any key is in the process of calibrating.

Bit 0: Set if any key is in detection (touched).

A CRC byte is appended to the response to the 0x05 command;this CRC folds in the command value 0x05 itself initially.

lQ 12 QT60248-AS R4.02/0405

4.6 Report 1st Key - 0x06Reports the first or only key to be touched, plus indicates ifthere are yet other keys that are also touched.

The return bits are as follows:

Key bit 00Key bit 11Key bit 22Key bit 33Key bit 44Unused51= any error condition is present61= more than 1 key is active7DescriptionBIT

Bits 4..0 encode for the first detected key in range 0..23. If nokeys are active, these 5 bits are all 1’s (0x1F, 31 decimal whenbits 5, 6, 7 are masked off). Disabled keys do not report asactive and do not generate an error flag in bit 6, even if they arereporting an error via command 0x8k.

If 2 or more keys in detection, bit 7 is set and the host shouldinterrogate the part via the 0x07 command to read out all thekey detections. This one command should be the dominantinterrogation command in the host interface; further commandscan be issued if the response to 0x06 warrants it.

A CRC byte is appended to the response; this CRC folds in thecommand 0x06 itself initially.

4.7 Report Detections for All Keys - 0x07Returns three bytes which indicate all keys in detection if any,as a bitfield; active keys report as 1’s.. Key 0 reports in bit 0 ofthe first byte returned; key 23 is reported in bit 7 of the last bytereturned. See Table 4.1 and Table 5.2. Disabled keys report asinactive (0).

A CRC byte is appended to the response; this CRC folds in thecommand 0x07 itself initially.

Table 4.1 Bits for key reporting and numbering

16171819202122232891011121314151012345670Byte Number

Returned(Y line #)

01234567Bit Number (X line #)Key #

4.8 Report Error Flags for All Keys - 0x0bReturns three bytes which show error flags as a bitfield for allkeys. Key 0 reports in bit 0 of the first byte returned; key 23 isreported in bit 7 of the last byte returned. See Table 4.1 andTable 5.2.

A key that is in calibration also is reported as an error in theresponse. The error flag is self-cleared once the keysuccessfully exits from calibration.

Important note: These error bits exclude FMEA error flags.

A CRC byte is appended to the response; this CRC folds in thecommand 0x0b itself initially.

4.9 Report FMEA Status - 0x0cReturns one byte which shows the FMEA error status of the Xand/or Y matrix scan lines. If an X line is in error, thecorresponding bit (below) is set. If a Y line has an FMEA error,the entire field is set to ones (0xFF).

Due to the physics of matrix wiring, a fault on any Y line willcause faults to be reported on all X lines as well. It is notpossible to separate out these faults for reporting purposes.

X0X1X2X3X4X5X6X7b0b1b2b3b4b5b6b7

A CRC byte is appended to the response; this CRC folds in thecommand 0x0C itself initially.

Sometimes, FMEA errors can occur intermittently, for exampledue to momentary power fluctuations. It is advisable to confirma true FMEA fault condition by making sure the error flagspersist for a several seconds.

For more information see Section 2.16.

4.10 Dump Setups Block - 0x0dThis command causes the device to dump the entire internalSetups block back to the host.

If the transfer is not paced faster than 100ms per byte thetransfer will be aborted and the device will time out. This canhappen if the host is also controlling DRDY.

During the transfer, sensing is halted. Sensing is resumed afterthe command has finished.

An 8-bit CRC is appended to the response; this CRC is thesame as the Setups table CRC.

4.11 Eeprom CRC - 0x0eThis command returns the 8-bit CRC byte calculated from theeeprom contents. The CRC sent back is the same CRC that isappended to the end of the Setups block.

This command requires substantial amounts of time to processand return a result; it is not recommended to use this commandexcept perhaps on startup or very infrequently.

No CRC is appended to the response.

4.12 Return Last Command - 0x0fThis command returns the last received command character, in1’s complement (inverted). If the command is repeated twice ormore, it will return the inversion of 0x0f, 0xf0.

If a prior command was not valid or was corrupted, it will returnthe bad command as well. This command also will reset thecommunications error flag (Section 4.5).

No CRC is appended to the response.

4.13 Internal Code - 0x10This command returns a 1-byte internal code.

A CRC byte is appended to the response; this CRC folds in thecommand 0x10 itself initially.

4.14 Internal Code - 0x12This command returns an internal code byte of the part forfactory diagnostic purposes. A response might take as long as500ms.

No CRC is appended to the response.

lQ 13 QT60248-AS R4.02/0405

4.15 Data Set for One Key - 0x4kReturns the data set for key k, where k = {0..23} encoded intothe low nibble of this command. This command returns 5 bytes,in the sequence:

Signal (2 bytes)Reference (2 bytes)Normal Detect Integrator (1 byte)

Signal and Reference are returned LSByte first. No CRC isappended.

Keys that are disabled report ‘0’ for both signal and reference.

4.16 Status for Key ‘k’ - 0x8kReturns a bitfield for key ‘k’ where k is from {0..23}. The bitfieldindicates as follows:

1= cal on this key failed 5 times01= this key is in cal11= signal ref < LSL (low signal error)21= key is in detect31= key is enabled41= reserved51= reserved61= reserved7DescriptionBIT

Bit 2 - LSL notes: See page 21.

A CRC byte is appended to the response; this CRC folds in thecommand 0x8k itself initially.

Disabled Keys: A disabled key never reports as being indetect, but always reports an LSL error (if LSL >0). An LSL errorflag generated for this reason is not reflected elsewhere, forexample via the 0x05 or 0x06 commands. An LSL error on anenabled key is however reflected in the 0x05 and 0x06commands.

A disabled key also reports back with bit 0 high (failed Cal). ACal error flag generated for this reason is not reflectedelsewhere, for example via the 0x05 or 0x06 commands. A Calerror on an enabled key is however reflected in the 0x05 and0x06 commands.

Just after reset or after a CAL command (commands 0x03 or0xCk), a disabled key will report back as being in calibration foronly one matrix scan cycle, then will report as having failed cal.

See also Section 2.2.

4.17 Cal Key ‘k’ - 0xckThis command must be repeated 2x within 100ms or thecommand will fail; the repeating command must be sequentialwithout any intervening command.

This command functions the same as 0x03 CAL commandexcept this command only affects one key ‘k’ where ‘k’ is from 0to 23.

The chosen key ‘k’ is recalibrated in its native timeslot; normalrunning of the part is not interrupted and all other keys operatecorrectly throughout. This command is for use only duringnormal operation to try to recover a single key that has failed oris not calibrated correctly.

Returns the 1’s compliment of 0xck just before the key isrecalibrated.

4.18 Command SequencingTo interface the device with a host, the flow diagram of Figure4-1, page 15, is suggested. The actual settings of the Setupsblock used should normally just be the default settings exceptwhere changes are specifically required, such as for sensiti vity,timing, or AKS changes.

The circles in this drawing are communications interchangesbetween host and sensor. The rectangles are internal hoststates or processing events. If any communications exchangefails, either the device will fail to respond within the allotted time,or the response CRC will be incorrect, or the response will beout of context (the response is clearly not for the intendedcommand). In these cases the host should just repeat thecommand.

The control flow will spend 99% of its time alternating betweenthe two states within the dashed rectangle. If a key is detected,the control flow will enter ‘Key Detection Processing’.

Stuck Key Detection processing (0xCk) is optional, since thedevice contains the max on-duration timeout function and cantherefore recalibrate the stuck key automatically. However, thehost can recalibrate stuck keys with greater flexibility if therecalibration timeouts are set to infinite and the host recalibratesthem under specific conditions.

Error handling takes place whenever an error flag is detected,or the device stops communicating (not shown). The errorhandling procedure is up to the designer, however normally thiswould entail shutting down the product if the error is seriousenough (for example, a key that will not calibrate, or a FMEAclass error).

An eeprom CRC error report is serious, and requires that thehost reload the Setups table into the device and thereafter issuea reset command or hardware reset.

The ‘Last Command’ command can be used at any time to clearcomms error flags and to resynchronize failed communications,for example due to timing errors etc.

lQ 14 QT60248-AS R4.02/0405

lQ 15 QT60248-AS R4.02/0405

Figure 4-1 Suggested Communications Flow

0x0ESetups CRC

Check

0x04Force Reset

0x06Report 1st Key

0x07Report alldetections

Only 1 Keyin Detect

0xckCal Key 'k'

~10ms Delay

Key Detection(s) Processing

No key,no error

mmmm 2 KeysDetected

resolvableerror

0x0FGet

'Last command'(clear error)

CommsError

Setups CRC failed 2x

Setups CRCfailed 1x

0x05Get

General Status

calibration fail, orFMEA fail, or

multiple errors

CRC is OK

Power On or Hardware Reset

Stuck KeyDetected(optional)

0x0CGet

FMEA Status

0x0BGet

Errors for AllKeys

Error Handling

Error Flag(takes

precedence)

FMEAError

CalibrationError

Done

Keys OK

Note: CRC errors or incorrectresponses should causeeach transmission to retry

Internal HostProcesses

Comms withQT

0x0FGet

'Last command' 0xF0returned

0xF0 notreturned

0x01Load Setups

Block

132nd return byte is CRC-8 of cmmd + return dataYes0..0xFF21FMEA bitfield on X, Y linesFMEA status0x0C

134th return byte is CRC-8 of cmmd + return dataYes0..0xFF3 bytes41Error bit fieldsError flags for all0x0B

134th return byte is CRC-8 of cmmd + return dataYes0..0xFF3 bytes41Sends back all key detect status bits (bitfield)Report all keys0x07

13

Bit 7: 1= indicates 2 or more touches if set. Bit 6: 1= any of the following conditions prevail: calibrating, key(s)

failed cal 5 times, sync fail, comms error, FMEA failure.Bit 5: UnusedBits 4..0: indicates key number (0..23) of first key touched; reads

0x1F (31 decimal) if no touch. 2nd return byte is CRC-8 of cmmd + return data

Yes0..0xFF21Get indication of first touched key + othersReport 1st key0x06

12

Bit 7: reservedBit 6: 1= comms error: unrecognized command received

This bit can be reset by the 0x0F cmmdBit 5: 1= FMEA failureBit 4: 1= ReservedBit 3: 1= line sync failureBit 2: 1= cal failed 5 times on an enabled key, or, an enabled key has

a low reference (Ref < LSL)Bit 1: 1= any key in calibrationBit 0: 1= any key is in detect2nd return byte is CRC-8 of cmmd + return data

Yes0..0xFF21Get general part status.General status0x05

12Returns 1’s complement of command to acknowledge command prior

to reset. If 2 commands not received in 100ms, times out and noresponse is issued.

-0xFB12Force device to reset. Command must berepeated 2x consecutively without anyintervening command in 100ms to execute

Force reset0x04

12

Returns 1’s complement of command to acknowledge cmd once thecal has been initiated.

If 2 commands not received in 100ms, times out and no response isissued.

-0xFC12

Force device to recalibrate all keys; re-entersRUN mode afterwards automatically; 0x03 mustbe repeated 2x consecutively without anyintervening command in 100ms to execute

CAL all0x03

12

First 0xFE issued when ready to get data, second 0xFE issued whenall loaded and burned; else timeout.

If 2 commands not received in 100ms, times out and no response isissued. Part will timeout if each byte not received within 100ms ofprevious byte.

If CRC failure, returns 0x00 instead of 0xFEData block length is 100 + 1 (added +1 byte is CRC-8). LSL should be

sent low byte first. A CRC of 0x00 is also acceptable in whichcase the CRC is not checked.

The internal EEPROM will be programmed regardless of CRC health.

-

0xFE+ 0xFE

OR

0xFE+ 0x00 (err)

22+100+1

Enter Setups, stop sensing; followed by blockload of binary Setups of length ‘nn’. Commandmust be repeated 2x consecutively without anyintervening command in 100ms to execute.Sensing auto-restarts, however, the deviceshould be reset after the block load to ensure allnew setups will take effect.

Enter Setupsmode0x01

11Flushes pending data from QT; one required to extract each responsebyte.-0..0xFF11Used to get data back in SPI modeNull command0x00

PageNotesCRCRtn range# Rtnd#/CmdDescriptionNameHexTable 4.2 Command Summary

lQ 16 QT60248-AS R4.02/0405

14

Used in Run mode. Normal sensing of other keys not affected.CAL of ‘k’ only takes place in the key’s normal timeslot.

Returns the ones compliment of the cmd char, once the cal isscheduled.

-~0xCk12

Force calibration of key # k where k= 0..23.Command must be repeated 2x consecutivelywithout any intervening command in 100ms toexecute

CAL key ‘k’0xCk

14

Bits 7..5: reservedBit 4: 1= key is enabledBit 3: 1= key is in detectBit 2: 1= (Ref < LSL), even on a disabled keyBit 1: 1= key is in calibrationBit 0: 1= calibration of this key failed 5 timesSecond return byte is CRC of cmmd + return data

Yes0..0xFF21Get status byte for key ‘k’ {0..23}Status for key ‘k’0x8k

14Diagnostic use only, not to be relied upon (no CRC). Signal andref are Tx as 2 bytes, LSB first.-0..0xFF

Each byte51Get signal, ref, Norm DI for key k {0..23}Signal: 2 bytes; Ref: 2 bytes; Norm DI: 1byte

Data for 1 key0x4k

13Returns 1’s compliment of last command even if bad. Resets thecommunications error flag.-0..0xFF11Returns last command receivedReturn last

cmmd0x0F

13CRC-8 only on Setups array section of eepromThis CRC is the same as the CRC at the end of Setups block load.Yes0..0xFF11Get eeprom CRCEeprom CRC0x0E

13100 block data bytes + 1 CRC byte returned.Yes0..0xFFEach byte1001

Returns Setups block area followed by CRC.Scanning is halted and then auto-restartedafter the cmd has completed.

Dump Setups0x0D

PageNotesCRCRtn range# Rtnd#/CmdDescriptionNameHex

lQ 17 QT60248-AS R4.02/0405

5 SetupsThe devices calibrate and process all signals using anumber of algorithms specifically designed to provide forhigh survivability in the face of adverse environmentalchallenges. They provide a large number of processingoptions which can be user-selected to implement veryflexible, robust keypanel solutions.

User-defined Setups are employed to alter these algorithmsto suit each application. These setups are loaded into thedevice in a block load over the serial interface. The Setupsare stored in an onboard eeprom array. After a setups blockload, the device should be reset to allow the new Setupsparameters to take effect. This reset can be either ahardware or software reset.

Refer to Table 5.1, page 22 for a table of all Setups.

Block length issues: The setups block is 100 bytes long toaccommodate 24 keys. This can be a burden on smaller hostcontrollers with limited memory. In larger quantities thedevices can be procured with the setups blockpreprogrammed from Quantum. If the application onlyrequires a small number of keys (such as 16) then thesetups table can be compressed in the host by filling largestretches of the Setups area with nulls.

Many setups employ lookup-table value translation. TheSetups Block Summary on page 23 shows all translationvalues.

Default Values shown are factory defaults.

5.1 Negative Threshold - NTHRThe negative threshold value is established relative to akey’s signal reference value. The threshold is used todetermine key touch when crossed by a negative-goingsignal swing after having been filtered by the detectionintegrator. Larger absolute values of threshold desensitizekeys since the signal must travel farther in order to cross thethreshold level. Conversely, lower thresholds make keysmore sensitive.

As Cx and Cs drift, the reference point drift-compensates forthese changes at a user-settable rate; the threshold level isrecomputed whenever the reference point moves, and thus italso is drift compensated.

The amount of NTHR required depends on the amount ofsignal swing that occurs when a key is touched. Thickerpanels or smaller key geometries reduce ‘key gain’, ie signalswing from touch, thus requiring smaller NTHR values todetect touch.

The negative threshold is programmed on aper-key basis using the Setup process. See table,page 23.

Negative hysteresis: NHYST is fixed at 12.5% ofthe negative threshold value and cannot bealtered.

Typical values: 3 to 8(7 to 12 counts of threshold; 4 is internallyadded to NTHR to generate the threshold).

Default value: 6(10 counts of threshold)

5.2 Positive Threshold - PTHRThe positive threshold is used to provide a mechanism forrecalibration of the reference point when a key's signalmoves abruptly to the positive. This condition is not normal,and usually occurs only after a recalibration when an objectis touching the key and is subsequently removed. The desireis normally to recover from these events quickly.

Positive hysteresis: PHYST is fixed at 12.5% of the positivethreshold value and cannot be altered.

Positive threshold levels are all fixed at 6 counts of signaland cannot be modified.

5.3 Drift Compensation - NDRIFT, PDRIFTSignals can drift because of changes in Cx and Cs over timeand temperature. It is crucial that such drift be compensated,else false detections and sensitivity shifts can occur.

Drift compensation (Figure 5-1) is performed by making thereference level track the raw signal at a slow rate, but onlywhile there is no detection in effect. The rate of adjustmentmust be performed slowly, otherwise legitimate detectionscould be ignored. The devices drift compensate using aslew-rate limited change to the reference level; the thresholdand hysteresis values are slaved to this reference.

When a finger is sensed, the signal falls since the humanbody acts to absorb charge from the cross-coupling betweenX and Y lines. An isolated, untouched foreign object (a coin,or a water film) will cause the signal to rise very slightly dueto an enhancement of coupling. This is contrary to the waymost capacitive sensors operate.

Once a finger is sensed, the drift compensation mechanismceases since the signal is legitimately detecting an object.Drift compensation only works when the signal in questionhas not crossed the negative threshold level.

The drift compensation mechanism can be asymmetric; thedrift-compensation can be made to occur in one directionfaster than it does in the other simply by changing theNDRIFT Setup parameter. This can be done on a per-keybasis.

The PDRIFT parameter is fixed at 0.4 seconds per count ofreference drift.

Specifically, drift compensation should be set to compensatefaster for increasing signals than for decreasing signals.Decreasing signals should not be compensated quickly,since an approaching finger could be compensated forpartially or entirely before even touching the touch pad.

lQ 18 QT60248-AS R4.02/0405

Figure 5-1 Thresholds and Drift Compensation

Threshold

Signal

Hysteresis

Reference

Output

However, an obstruction over the sense pad, for which thesensor has already made full allowance for, could suddenlybe removed leaving the sensor with an artificially suppressedreference level and thus become insensitive to touch. In thislatter case, the sensor should compensate for the object'sremoval by raising the reference level relatively quickly.

Drift compensation and the detection time-outs work togetherto provide for robust, adaptive sensing. The time-outsprovide abrupt changes in reference calibration dependingon the duration of the signal 'event'.

NDRIFT Typical values: 9 to 11(2 to 3.3 seconds per count of drift compensation)

NDRIFT Default value: 10(2.5s / count of drift compensation)

PDRIFT Fixed value: 0.4 secsNote: This value cannot be altered and does not appearin the Setups block.

5.4 Detect Integrators - NDIL, FDILNDIL is used to enable or disable keys and to provide signalfiltering. To enable a key, its NDIL parameter should benon-zero (ie NDIL=0 disables a key). See Section 2.2.

To suppress false detections caused by spurious events likeelectrical noise, the device incorporates a 'detectionintegrator' or DI counter mechanism that acts to confirm adetection by consensus (all detections in sequence mustagree). The DI mechanism counts sequential detections of akey that appears to be touched, after each burst for the key.For a key to be declared touched, the DI mechanism mustcount to completion without even one detection failure.

The DI mechanism uses two counters. The first is the ‘fastDI’ counter FDIL. When a key’s signal is first noted to bebelow the negative threshold, the key enters ‘fast burst’mode. In this mode the burst is rapidly repeated for up to thespecified limit count of the fast DI counter. Each key has itsown counter and its own specified fast-DI limit (FDIL), whichcan range from 1 to 15. When fast-burst is entered the QTdevice locks onto the key and repeats the acquire burst untilthe fast-DI counter reaches FDIL, or, the detection failsbeforehand. After this the device resumes normalkeyscanning and goes on to the next key.

The ‘Normal DI’ counter counts the number of times thefast-DI counter reached its FDIL value. The Normal DIcounter can only increment once per complete scan of allkeys. Only when the Normal DI counter reaches NDIL doesthe key become formally ‘active’.

The net effect of this is that the sensor can rapidly lock ontoand confirm a detection with many confirmations, while stillscanning other keys. The ratio of ‘fast’ to ‘normal’ counts iscompletely user-settable via the Setups process. The totalnumber of required confirmations is equal to FDIL timesNDIL.

If FDIL = 5 and NDIL = 2, the total detection confirmationsrequired is 10, even though the device only scanned throughall keys only twice.

The DI is extremely effective at reducing false detections atthe expense of slower reaction times. In some applications aslow reaction time is desirable; the DI can be used tointentionally slow down touch response in order to requirethe user to touch longer to operate the key.

If FDIL = 1, the device functions conventionally; eachchannel acquires only once in rotation, and the normal detect

integrator counter (NDIL) operates to confirm a detection.Fast-DI is in essence not operational.

If FDIL m 2, then the fast-DI counter also operates in additionto the NDIL counter.

If Signal [ NThr: The fast-DI counter is incremented towardsFDIL due to touch.

If Signal >NThr then the fast-DI counter is cleared due tolack of touch.

Disabling a key: If NDIL =0, the key becomes disabled.Keys disabled in this way are pared from the burst sequencein order to improve sampling rates and thus response time.See Section 2.2, page 3.

NDIL Typical values: 2, 3NDIL Default value: 2 FDIL Typical values: 4 to 6FDIL Default value: 5

5.5 Negative Recal Delay - NRDIf an object unintentionally contacts a key resulting in adetection for a prolonged interval it is usually desirable torecalibrate the key in order to restore its function, perhapsafter a time delay of some seconds.

The Negative Recal Delay timer monitors such detections; ifa detection event exceeds the timer's setting, the key will beautomatically recalibrated. After a recalibration has takenplace, the affected key will once again function normallyeven if it is still being contacted by the foreign object. Thisfeature is set on a per-key basis using the NRD setupparameter.

NRD can be disabled by setting it to zero (infinite timeout) inwhich case the key will never auto-recalibrate during acontinuous detection (but the host could still command it).

NRD is set using one byte per key, which can range in valuefrom 0..254. NRD above 0 is expressed in 0.5s increments.Thus if NRD =120, the timeout value will actually be 60seconds. 255 is not a legal number to use.

NRD Typical values: 20 to 60 (10 to 30 seconds)NRD Default value: 20 (10 seconds)NRD Range: 0..254 (∞, 0.5 .. 127s)

5.6 Positive Recalibration Delay - PRDA recalibration occurs automatically if the signal swings morepositive than the positive threshold level. This condition canoccur if there is positive drift but insufficient positive driftcompensation, or, if the reference moved negative due to aNRD auto-recalibration, and thereafter the signal rapidlyreturned to normal (positive excursion).

As an example of the latter, if a foreign object or a fingercontacts a key for period longer than the Negative RecalDelay (NRD), the key is by recalibrated to a new lowerreference level. Then, when the condition causing thenegative swing ceases to exist (e.g. the object is removed)the signal suddenly swings positive to its normal reference.

It is almost always desirable in these cases to cause the keyto recalibrate quickly so as to restore normal touchoperation. The time required to do this is governed by PRD.In order for this to work, the signal must rise through thepositive threshold level PTHR continuously for the PRDperiod.

lQ 19 QT60248-AS R4.02/0405

After the PRD interval has expired and the auto- recalibrationhas taken place, the affected key will once again functionnormally. PRD is fixed at 1 second for all keys, and cannotbe altered.

5.7 Burst Length - BLThe signal gain for each key is controlled by circuitparameters as well as the burst length.

The burst length is simply the number of times thecharge-transfer (‘QT’) process is performed on a given key.Each QT process is simply the pulsing of an X line once, witha corresponding Y line enabled to capture the resultingcharge passed through the key’s capacitance Cx.

QT60xx8 devices use a fixed number of QT cycles which areexecuted in burst mode. There can be up to 64 QT cycles ina burst, in accordance with the list of permitted values shownin Table 5.3.

Increasing burst length directly affects key sensitivity. Thisoccurs because the accumulation of charge in the chargeintegrator is directly linked to the burst length. The burstlength of each key can be set individually, allowing for directdigital control over the signal gains of each key individually.

Apparent touch sensitivity is also controlled by the NegativeThreshold level (NTHR). Burst length and NTHR interact;normally burst lengths should be kept as short as possible tolimit RF emissions, but NTHR should be kept above 6 toreduce false detections due to external noise. The detectionintegrator mechanism also helps to prevent false detections.

BL Typical values: 2, 3 (48, 64 pulses / burst)BL Default value: 2 (48 pulses / burst)BL possible values: 16, 32, 48, 64

5.8 Adjacent Key Suppression - AKSThese devices incorporate adjacent key suppression (‘AKS’ -patent pending) that can be selected on a per-key basis.AKS permits the suppression of multiple key presses basedon relative signal strength. This feature assists in solving theproblem of surface moisture which can bridge a key touch toan adjacent key, causing multiple key presses. This featureis also useful for panels with tightly spaced keys, where afingertip might inadvertently activate an adjacent key.

AKS works for keys that are AKS-enabled anywhere in thematrix and is not restricted to physically adjacent keys; thedevice has no knowledge of which keys are actuallyphysically adjacent. When enabled for a key, adjacent keysuppression causes detections on that key to be suppressedif any other AKS-enabled key in the panel has a morenegative signal deviation from its reference.

This feature does not account for varying key gains (burstlength) but ignores the actual negative detection thresholdsetting for the key. If AKS-enabled keys in a panel havedifferent sizes, it may be necessary to reduce the gains oflarger keys relative to smaller ones to equalize the effects ofAKS. The signal threshold of the larger keys can be alteredto compensate for this without causing problems with keysuppression.

Adjacent key suppression works to augment the naturalmoisture suppression of narrow gated transfer switchescreating a more robust sensing method.

AKS Default value: 0 (Off)

5.9 Oscilloscope Sync - SSYNCPin 11 (S_Sync) can output a positive pulse oscilloscopesync that brackets the burst of a selected key. More than oneburst can output a sync pulse as determined by the Setupsparameter SSYNC for each key.

The SSYNC function does not become effective until the parthas been reset, or the desired key(s) are recalibrated.

This feature is invaluable for diagnostics; without it,observing signals clearly on an oscilloscope for a particularburst is very difficult.

This function is supported in Quantum’s QmBtn PC software.

SSYNC Default value: 0 (Off)

5.10 Mains Sync - MSYNCThe MSync feature uses the SYNC pin.

External fields can cause interference leading to falsedetections or sensitivity shifts. Most fields come from ACpower sources. RFI noise sources are heavily suppressedby the low impedance nature of the QT circuitry itself.

Noise such as from 50Hz or 60Hz fields becomes a problemif it is uncorrelated with acquisition signal sampling;uncorrelated noise can cause aliasing effects in the keysignals. To suppress this problem the SYNC input allowsbursts to synchronize to the noise source.

The noise sync operating mode is set by parameter MSYNCin Setups.

The sync occurs only at the burst for the lowest numberedenabled key in the matrix; the device waits for the syncsignal for up to 100ms after the end of a preceding full matrixscan, then when a negative sync edge is received, the matrixis scanned in its entirety again.

The sync signal drive should be a buffered logic signal, butnever a raw AC signal from the mains; slow or erratic edgeson MSYNC can cause the device to sync on the wrong edge,or both edges. The device should only sync to the fallingedge.

Since Noise sync is highly effective and inexpensive toimplement, it is strongly advised to take advantage of itanywhere there is a possibility of encountering low frequency(i.e. 50/60Hz) electric fields. Quantum’s QmBtn software canshow such noise effects on signals, and will hence assist indetermining the need to make use of this feature.

If the sync feature is enabled but no sync signal exists, thesensor will continue to operate but with a delay of 100msfrom the end of one scan to the start of the next, and hencewill have a slow response time. A failed Sync signal (oneexceeding a 100ms period) will cause an error flag (seecommands 0x05, 0x06).

MSYNC Default value: 0 (Off)MSYNC Possible range: 0, 1 (Off, On)

5.11 Burst Spacing - BSThe interval of time from the start of one burst to the start ofthe next is known as the burst spacing. This is an alterableparameter which affects all keys. The burst spacing can beviewed as a scheduled timeslot in which a burst occurs. Thisapproach results in an orderly and predictable sequencing ofkey scanning with predictable response times.

lQ 20 QT60248-AS R4.02/0405

Shorter spacings result in a faster response time to touch;longer spacings permit higher burst lengths and longerconversion times but slow down response time.

BS Default value: 1 (500µs)BS Possible range: 1..11 (500µs .. 3ms)

5.12 Lower Signal Limit - LSLThis Setup determines the lowest acceptable value of signallevel for all keys. If any key’s reference level falls below thisvalue, the device declares an error condition in the statusbits.

Testing is required to ensure that there are adequatemargins in this determination. Key size, shape, panel

material, and burst length all factor into the detected signallevels.

This parameter occupies 2 bytes of the setups table. The loworder byte should be sent first.

LSL Default value: 100LSL Possible range: 0..2047

5.13 Host CRC - HCRCThe setups block terminates with a 8-bit CRC, HCRC, of theentire block. The formulae for calculating this CRC is shownin Section 7.

lQ 21 QT60248-AS R4.02/0405

Table 5.1 Setups Block Setups data is sent from the host to the QT in a block of hex data. The block can only be loaded in Setups mode following two se quential 0x01 commands (page 12). Alldevices this datasheet pertain to have the same block length. Refer also to Table 5.3, page 23 for further details, and all of Section 5.

101Block length21--80..2551HCRCHost CRC byte1008

21Lower limit of acceptable signal; below this value, device declares an error.The low order byte should be sent first.10024160..20482LSLLower signal Limit987

20Lower nibble = burst spacing1244BS = 0..111BSBurst spacing97620Bit 6 = Mains sync, negative edge, 1 = enabled; default = 0 (off)0241MSYNC = 0, 11MSYNCMains Sync965

202020

Bits 5, 4: = BL, via LUT, default = 48 (setting =2)Bit 6 = AKS, 1 - enabledBit 7 = Scope sync, 1 = enabled

200

111

211

BL = 0, 1, 2, 3AKS = 0, 1

SSYNC = 0, 124

BLAKS

SSYNC

Burst LengthAKSScope Sync

724

19Range is in 0.5 sec increments; 0 = infinite; default = 10s (operand = 20)Range is { infinite, 0.5...127s }; 255 is illegal to use20180..25424NRDNeg recal delay483

19Lower nibble = Normal DI Limit, values same as operand (0 = disables key)Upper nibble = Fast DI Limit, values same as operand (0 does not work)

25

11

44

NDIL = 0..15FDIL = 0..1524NDIL

FDILNormal DI LimitFast DI Limit242

1818

Lower nibble = Neg Threshold - take operand and add 4 to get valueUpper nibble = Neg Drift comp - Via LUT

610

11

44

NTHR = 0..15NDRIFT = 0..1524NTHR

NDRIFTNeg threshNeg Drift Comp01

PageDescriptionDefaultValue

KeyScopeBitsValid rangeBytesSymbolParameterByte

Item#

CRC Note: A CRC calculator for Windows is available free of charge from Quantum Research on request.

Table 5.2 Key MappingSome commands return bitfields related to keys. For example, command 0x07 (report all keys) returns 3 bytes containing flag bits, one per key, to indicate which keys are reportingtouches. The following table shows the byte and bit order of the keys. The table contains the key number reported in each bit.

The key number is related to the X and Y scan lines which address each particular key. Each byte in the return stream represents one set of keys along a Y line, ie up to 8 keys.Thus, key 0 is at location X0,Y0 and key 19 is at location X3,Y2. .

Note: Byte 0 is returned first.

lQ 22 QT60248-AS R4.02/0405

16171819202122232891011121314151012345670Byte

(Y line)

01234567Bit (X line)

Table 5.3 Setups Block SummaryTypical values: For most touch applications, use the values shown in the outlined cells. Bold text items indicate default settings. The number to send to the QT is the number inthe leftmost column (0..15), not numbers from within the table. The QT uses lookup tables to translate the 0..15 to the parameters for each function.

NRD is an exception: It can range from 0..254 which is translated from 1= 0.5s to 254= 127s with zero = infinity.

1515101915

14147.51814

131361713

12124.51612

3,000µs11113.31511

2,750µs1010- 2.5 -1410

2,500µs992139

2,250µs881.5128

2,000µs771.2117

1,750µs661- 10 -6

1,500µs- 5 -50.895

1,250µs440.684

1,000µs64330.473

750µs- 48 -Default=10s

2- 2 -0.362

- 500µs -OnOnOn320.5 .. 127s110.251

unused- Off -- Off -- Off -160 (Infinite)unusedKey off0.140GlobalGlobalPer keyPer keyPer keyPer keyPer keyPer keyPer keyPer key

BSMSYNCScope SyncAKSBL

pulsesNRDsecs

FDILcountsNDIL counts

NDRIFTsecs

NTHRcounts

Parameter

Index Number

lQ 23 QT60248-AS R4.02/0405

6 Specifications 6.1 Absolute Maximum Electrical SpecificationsOperating temp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40OC to +105OCStorage temp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55OC to +125OCVDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +5.5VMax continuous pin current, any control or drive pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10mAShort circuit duration to ground, any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . infiniteShort circuit duration to VDD, any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . infiniteVoltage forced onto any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6V to (Vdd + 0.6) VoltsEeprom setups maximum writes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100,000 write cycles

6.2 Recommended operating conditionsVDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0V to 5.25VSupply ripple+noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mV p-p maxCx transverse load capacitance per key. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 20pF

6.3 DC SpecificationsVdd = 5.0V, Cs = 4.7nF, Rs = 470K; Ta = recommended range, unless otherwise noted

k✡8030Internal /RST pullup resistorRrst

DRDY, /SS pinsk✡50 20Internal pullup resistorsRpbits119Acquisition resolutionArµA±1Input leakage currentIil

1mA sourceVVdd-0.7High output voltageVoh4mA sinkV0.6Low output voltageVol

V2.2High input logic levelVhlV0.8Low input logic levelVil

V2.92.7 Vdd internal reset voltageVrExcluding external componentsmA25Supply current, runningIddr

NotesUnitsMaxTypMinDescriptionParameter

6.4 Timing Specifications

Max guaranteed is a min of 1.5MHzMHz1.5SPI Clock rateFckSPI parameter controlled by hostns667CLK periodS9SPI parameter controlled by hostns333CLK high pulse widthS8SPI parameter controlled by hostns333CLK low pulse widthS7

SPI parameter controlled by QTµs1DRDY low pulse widthS6SPI parameter controlled by QTµs40 /SS to falling DRDYS5SPI parameter controlled by QTns20 /SS to 3-state MISOS4SPI parameter controlled by hostns25Last CLK to /SSS3SPI parameter controlled by QTns20 CLK to valid MISOS2SPI parameter controlled by hostns333 /SS to first CLK edgeS1

%±8Burst modulation, percentFmkHz226Burst center frequencyFc

Adjustable parameter via Setupsµs3,000500Burst spacingTBS

NotesUnitsMaxTypMinDescriptionParameter

lQ 24 QT60248-AS R4.02/0405

6.5 Mechanical Dimensions

6.6 Marking

lQ 25 QT60248-AS R4.02/0405

1234

8765

11109

32 31 30 28

2324

25262729

12 14 16

18

22

20

1517

19

21

13

SYMBOL

AeEhHLp

a

Millimeters InchesMin Max Notes Min Max Notes

E

H h

a

e

p

A

L

o

9.25 8.75 0.344 0.3540.09 0.20 0.003 0.0080.450.05

0.750.151.20

0.0180.002

0.0300.0060.047

0.800.30

BSC0.800.45

0.0310.012

BSC0.0310.018

6.90 7.10 0.272 0.280

--

o 0 7 0 7

SQSQSQSQ

Package Type: 32 Pin TQFP

YesQT60248-AG24QT60248-ASG-400C to +1050CYesQT60168-AG16QT60168-ASG-400C to +1050C

Lead-FreeMarkingKeysTQFP PartNumberTA

7 Appendix7.1 8-Bit CRC Algorithm

// 8 bits crc calculation. Initial value is 0.// polynomial = X8 + X5 + X4 + 1// data is an 8 bit number; crc is a 8 bit number

unsigned char eight_bit_crc(unsigned char crc, unsigned char data){ unsigned char index; // shift counter

unsigned char fb;

index = 8; // initialise the shift counterdo{ fb = (crc ^ data) & 0x01;

data >>= 1;crc >>= 1;

If(fb){ crc ^= 0x8c; }

} while(--index);

return crc;}

A CRC calculator for Windows is available free of charge from Quantum Research.

lQ 26 QT60248-AS R4.02/0405

7.2 1-Sided Key LayoutThis key design can be made on a 1-sided SMT PCB. A single 0-ohm jumperallows the wiring to be done on a single side with full pass-through of X and Ytraces to allow matrix connections to be made across a large number of keys.Key size, shape, and number of interleavings can be varied substantially fromthis drawing. The below drawing shows 6 interleave white spaces; only adouble interleave is required in the case of smaller keys.

The PCB is bonded to a panel on its underside, and the fields fire through thePCB, adhesive, and panel in that sequence. This results in a very low costdesign.

7.3 PCB LayoutShown is an example PCB layout using inexpensive 1-sided CEM-1 or FR-1 PCB laminate. The key layouts follow the designrules shown above. (PCB design shown uses a QT60326 chip but still represents a good example).

lQ 27 QT60248-AS R4.02/0405

X

Y

X

Y

0-ohm SMT Jumper

lQ Copyright © 2004 QRG Ltd. All rights reservedPatented and patents pending

Corporate Headquarters1 Mitchell Point

Ensign Way, Hamble SO31 4RFGreat Britain

Tel: +44 (0)23 8056 5600 Fax: +44 (0)23 8045 3939

www.qprox.com

North America651 Holiday Drive Bldg. 5 / 300

Pittsburgh, PA 15220 USATel: 412-391-7367 Fax: 412-291-1015

This device covered under one or more of the following United States and international patents: 5,730,165, 6,288,707, 6,377,009, 6,452,514,6,457,355, 6,466,036, 6,535,200. Numerous further patents are pending which may apply to this device or the applications thereof.

The specifications set out in this document are subject to change without notice. All products sold and services supplied by QRG are subjectto our Terms and Conditions of sale and supply of services which are available online at www.qprox.com and are supplied with every orderacknowledgement. QProx, QTouch, QMatrix, QLevel, QSlide, and QWheel are trademarks of QRG. QRG products are not suitable formedical (including lifesaving equipment), safety or mission critical applications or other similar purposes. Except as expressly set out inQRG's Terms and Conditions, no licenses to patents or other intellectual property of QRG (express or implied) are granted by QRG inconnection with the sale of QRG products or provision of QRG services. QRG will not be liable for customer product design and customersare entirely responsible for their products and applications which incorporate QRG's products.

Development Team: Dr. Tim Ingersoll, Samuel Brunet, Hal Philipp