Q3’13 ArxCis-NV TM NVDIMM Technology & Roadmap Review

Q3’13

ArxCis-NVTM NVDIMM Technology & Roadmap Review

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NEW MEMORY LANDSCAPE

SCM (STORAGE CLASS MEMORIES) ARGUABLY NOT VIABLE FOR MAINSTREAM ADOPTION FOR ~ 4-5 YRS

NVDIMM

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NVDIMM

• NVDIMM is “leading the charge” of Non-Volatility & Persistence to main memory• Will lead to radical changes in computing / storage architecture / paradigms• Many different usage models, with strong Value Prop

Arxcis-NV Technical Overview

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FEATURES


» DRAM Capacities: 2GB, 4GB, 8GB» DDR3 1.5V 1333MT/s» NAND 2x DRAM Capacity

» Multiple Host Trigger Methods (incl ADR)» Supercapacitor Charged via DIMM» Save / Restore @ ~10 sec/GB

Powered by SuperCapacitors in event of power-failure

DRAM Endurance & Speed NAND for Persistence

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• Fastest storage tier, 11GB/S, DDR3 DIMM speed & bandwidth more than 300% faster than PCI-E (3.2GB/S).

• 1.4 million IOPS Read & Write, 3 times faster than PCI-E cards. (430K Write IOPS)

• DRAM chips never wear out, no limit on number of writes.• DIMM interface “talks” to CPU more directly.• 1000x better latency performance than PCI-E, 10 nanoseconds

vs 10 microseconds.• Complete solution with supercap, monitors supercap health.

ArxCis NVDIMM Key Features I.


6 Arxcis-NV Technical Overview




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• Use as RAMDISK, and data will be saved in event of power failure. (PRAMDISK)

• Faster recover from power failure, back to system environment before power failure.

• Support Instant On, apps layer data kept in flash, fastest boot. • Configure as block device for caching, performance +

endurance. • Memcache application pushing up demand for NVDIMM.• Support both ADR & NMI power failure data saving functions.• Intel’s chosen partner for NVDIMM enablement for Grantely

platform.

ArxCis NVDIMM Key Features II.


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- Removing need to write on SSDs, extend life of SSD based servers.

- No need over-provisioning, releasing extra storage space from SSDs.

- No operation cycles wasted on wear leveling.- No longer a “write cliff”, nor need to closely monitor drive usage.- Rapid increase in ROI for enterprise or data center applications.

ArxCis NVDIMM, Perfect Match For SSD based Enterprise & DCN Systems.


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ArxCis NVDIMM Actual Installation.


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ArxCis NVDIMM Actual Installation.


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ARXCIS-NVTM

NVDIMM – HOW IT FUNCTIONS



NVDIMM: HOW IT FUNCTIONS (SAVE)

SuperCap powersSub-system

P/FAILSystem Crash

DATA SAVE FROM DRAM TO FLASH


NVDIMM: HOW IT FUNCTIONS (RESTORE)

SuperCap powersSub-system

P/FAILSystem Crash

RESTORES DATA FROM FLASH TO DRAM

Host can access

RESTORED data

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ArxCis-NV™Controller

DDR3

DDR3 SDRAM

Power Supply Manager

Data

I2C

Clock

Clocks

SupercapPack

Address / Command

JEDECSPD EEPROM

Clock

Clocks

VDD

Status / Ctrl Voltages Clock

Flash Controller

NANDFlash

NANDFlash

NANDFlash

NANDFlash

SSTL-15DDR3 RPLL

Bus Switch

JEDEC Standard DDR3 DIMM Edge Connector

SATA

ARXCIS-NV BLOCK DIAGRAM


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ARXCIS-NV OPERATING MODE

NORMAL

SAVE RESTOREOFF

JEDEC Standard DDR3 RDIMM Operation1333 MT/sec, 2GB or 4GB capacities

RESTORE Command

SAVETrigger

Data TransferredFrom Flash To DRAM

Disconnect From Host

Disconnect From Host

ReconnectTo Host

Data TransferredFrom DRAM To Flash


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ARXCIS-NVTM ROADMAP


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NVDIMM (DDR INTERFACE)


Product 2H ‘13 1H ‘14 2H ‘14 1H ‘15

DDR3 RDIMM

DDR3 LRDIMM

DDR4RDIMM

Committed

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ARXCIS-NVTM DDR4 FEATURES


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• DDR4 DRAM Interface. DDR4 JEDEC pin-out. Module voltage @ 1.2V. • 1866MT/s Min Speed for ES. 2133MT/ for QS. (2R @ 2DPC)• Data Transfer Speeds (DRAM Flash) @ Max 5 sec/GB. • OEM target of <60sec for SAVE/RESTORE of 16GB DIMM.• NVDIMM meets JEDEC Standard DDR4 (X-Y-Z) Mechanical dimensions (note DDR4

module max height increases to 31.25mm)• 1-Rank & 2-Rank Module Configurations Required. 2nd rank enabled via DDP/BGA

stacking – Supporting 36 physical DRAM packages on DIMM• 4Gb Mono DRAM Base: 8GB 1-Rank & 16GB 2-Rank• 8Gb Mono DRAM Base: 16GB 1-Rank & 32GB 2-Rank

• SSD capacity – (Appropriately sized for contents of DRAM + ECC)• Encryption AES-256 & Password Lock• Multiple Image support

DDR4 FEATURE SUPPORT


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• Early warning detection of Flash/SSD failure / wear-out, Bad block count / detection.• Erase operation. Host can initiate an erase operation to securely delete data on SSD.• In-field Firmware upgradable.• Firmware Reliability Feature. In case of firmware hang, watch dog timer feature

implemented in FPGA to reset itself• JEDEC Pin-227 SAVE-pin• Intel MRC support• 12V pins. Design NVDIMM to support host systems using 12V pin as route of power (i.e

consolidated supercap pack)• Build option to support supercap tethered individually to the DIMM.

DDR4 FEATURE SUPPORT (MISC)


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NVDIMM SYSTEM INTEGRATIONVIKING NVDIMM SUPPORTS BOTH “ADR” & “NMI” TRIGGER

- SANDY BRIDGE- IVY BRIDGE


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» Early Power Failure Hardware NMI Signal To Processor» SAVE_n Signal Routed From Processor To NVDIMM» Power Supply w/ minimum 1 msec holdup post power loss» NVDIMM-Aware System BIOS» NMI Handler And Driver

NMI TRIGGER SYSTEM SUPPORT REQUIREMENTS (ALTERNATE TO ADR)


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» ArxCis-NV™ Is A Storage Device. » The Same Techniques Used To Enhance Data Integrity With

Traditional Storage Devices Can Be Applied To ArxCis-NV» DIMM Mirroring

Built into Sandybridge memory controller» Memory Scrubbing» Intel Machine Check Architecture

Provides ability to handle some memory related faults that would have crashed system in earlier architectures

» Software Techniques Software RAID Checkpointing / Journaling

SYSTEM LEVEL RELIABILITY ENHANCEMENT


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ITEM Description

ArxCis-NV Datasheet [1] NVDIMM datasheet providing AC and DC electrical characteristics, detailed functional description, status/command register definitions, and module pinout.

ArxCis-NV System Hardware Design Guide [2] Provides guidance on required motherboard hardware support and power supply selection.

ArxCis-NV Event Handler Specification [3] Describes function and implementation of ArxCis-NV Linux NMI Handler.

ArxCis-NV Event Handler Reference Code Linux open source reference code written in C.

ArxCis-NV NVDriver Specification [4] Describes function and implementation of ArxCis-NV driver, which is required to map ArxCis into application memory space.

ArxCis-NV NVDriver Reference Code Linux open source reference code written in C.

ArxCis-NV Management Driver Specification [5] Describes function and implementation of ArxCis-NV management driver, which serves as an interface for applications to access ArxCis-NV management interfaces, such as supercapacitor health monitoring info.

ArxCis-NV Management Driver Reference Code Linux open source reference code written in C.

ArxCis-NV BIOS Porting Guide [6] Describes required BIOS modifications for ArxCis-NV support. Code base is AMI BIOS distribution for Intel Rose City platform (Sandybridge).

ArxCis-NV BIOS Reference Code C code distributed to customer at no cost under terms of Viking’s license with AMI.

ArxCis-NV EFI POST Test Specification [7] Describes Power on self test module for ArxCis-NV.

ArxCis-NV EFI POST Test Reference Code. Reference code written in C for the ArxCis-NV POST test module.

SUPPORT DOCUMENTATION AND REFERENCE CODE


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SUPERCAP PACKS FOR INTERNAL HDD BRACKET

• ArxCis-NV Supercapacitor packs• Designed to be retained in internal 2.5” HDD bracket

ArxCis-NV Supercap options

1. 2GB NVDIMM

2. 4GB NVDIMM

3. 8GB NVDIMM

• Upper row of 3 = 8GB Pack

• Lower row of 2 = 4GB Pack

• Lower row of 1 = 2GB Pack(not shown)

Viking Confidential

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SUPERCAPACITOR BLADES

Cylindrical Supercapacitor power source to fit 1.2 width chassis.

Viking Product Portfolio

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GLOBAL LOCATIONS

European HeadquartersLerchenstrasse 1D-91710 GunzenhausenGermanyPhone: +49 2921 981 6463

Japan HeadquartersShinagawa Grand Central Tower2-16-4 Konan, Minato-KuPhone: +81 3 6863 5351

Singapore HeadquartersNo 2 Chai Chee DriveSingapore, 109840Phone: +65 6839 8008

U.S. Headquarters 20091 EllipseFoothill Ranch, CA 92610Phone: +1 949 643 7255Fax: +1 949 643 7250

www.vikingtechnology.com


Documents

Q3’13 ArxCis-NV TM NVDIMM Technology & Roadmap Review