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3D Integration of standard integrated circuits
René Puschmann, Mathias Böttcher, Irene Bartusseck,Frank
Windrich, Conny Fiedler, Peggy John, Charles
Manier, Kai Zoschke, Jürgen Grafe, HermannOppermann, M. Jürgen
Wolf, K. Dieter Lang
Fraunhofer IZM-ASSID
Ringstrasse 12, 01468 Moritzburg, Germany
[email protected]
Michael Ziesmann NXP Semiconductors Germany
GmbHStresemannallee 101, 22529 Hamburg
Abstract —In this paper we present the process
and electrical
results of a 3D integration using through silicon vias (TSV).
A
flash memory chip has been directly connected to a processor
die.
The TSVs have been applied from the wafer front-side into a
fully processed advanced CMOS 300 mm wafers using a via last
approach. After dry etching the 20 by 107 μm holes into the
substrate an isolation and barrier seed films are deposited
andthen filled with copper. The electrical connection between the
pad
level of the processor chips and the interface to the
external
connections is realized with a two level redistribution
wiring.
Subsequently the wafer is flipped, temporary bonded to a
carrier
wafer, thinned and the TSVs are connected from the wafer
back-
side. Finally the flash chips are assembled to the controller
die
using a die-to-wafer (D2W) technique. Electrical tests have
been
conducted and a high yield after TSV processing and assembly
determined. The isolation properties and electrical resistance
was
measured. The linear current in stress transistors was used
to
define a keep out zone.
Keywords— Through Silicon Vias, TSV, 3D technology, 3D
IC
process, 3D mechanical stress analyses
I. I NTRODUCTION
A vertical integration of devices opens numerousopportunities to
connect microelectronic or micromechanicalcomponents. There is the
possibility to bring microcontrollerand MEMS into one package or to
achieve wide IOconnections allowing high data rates. Another
usefulapplication of 3D integration is the stacking of ICs
havingdifferent semiconductor technologies. To realize
verticalconnections between the wafer top-side and the wafer
back-side one way is to use through silicon vias. When applying
avia last approach, the impact on existing CMOS integrationschemes
is comparable small, only free space for the TSVs and pads for
their connection must be provided by the design. Morethan that one
can realize the FEOL and BEOL processing inone location and apply
the TSVs, re-distribution layers (RDL)and bumping in another
location. The 3D integration cantherefore be offered as closed
process module in a foundry
based manufacturing environment which can be applied
toalmost any customer wafer.
To realize a via last scheme two main approaches exist:
1) TSVs are processed from the wafer front-side with
theconnection between TSVs and chip wiring in one of the lastmetal
levels by a RDL or
2) from the wafer back-side with landing on one of the
firstmetal levels as for example in [1].
The first approach has the advantage that the TSV as wellas the
top side RDL processing can be carried out on fullthickness wafers,
whereas in the second case all processessuffer the limitations
given by temporary bonding. The wafer
bond adhesive materials used in temporary
bonding/debonding processes are not yet in such a condition
that steep temperatureramp rates and absolute temperatures above
250°C can beenapplied without massive cross-linking of the
adhesive. On theother hand a front-side via requires more free
space in theactive areas and metallization levels compared to a
back-sidevia and the usually thick oxide stacks of the BEOL
arechallenging for dry etch. In addition those fully
processedwafers represent a high value which has to be considered
in
yield calculations.The example given here shows the direct
connection
between a controller chip and a flash memory chip
usingthrough silicon vias where a via last front-side scheme
waschosen. The substrate were the TSVs are applied are advancedCMOS
300 mm wafers which hold the controller chips. Thosesubstrates are
fully processed to the pad level. The BEOL stackhas a total
thickness of about 7 μm with a topography of about2.5 μm.
The flash memory chips are assembled to the back side ofthe
processor wafer as illustrated in Figure 1.
Processor Chip TSV
Si-Bulk
Flash Chip
TS RDL
BS RDL
Figure 1: Schematic of one processor chip with a flash
chip assembled to its
back-side. The processor chip is a die of the wafer in
which the TSVs are
applied.
The TSVs were arranged in 2 rows and did sum up to anopen area
of 0.05 %. They have a target dimension of 20 μm indiameter and 100
μm depth in silicon. In order to establish a
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direct interconnection between two active devices, the
requiredTSVs have to go through the BEOL stack and in the
silicon
bulk material of the processor chip. The electrical
connections between the I/O pads on the processor wafer front
side, theflash memory interface and the TSVs have been realized by
atwo-layer signal redistribution wiring. Electro-platednickel/gold
has been applied as interconnect pad finish. The
back-side processing of the processor wafer (PW) has
been
supported by temporary bonding/debonding. After waferthinning
and TSV reveal the contacts to the TSVs from thewafer back-side
have been realized. The Flash IC assemblywas conducted by applying
a die-to-wafer assembly technique.All steps were carried out on
volume-production compliant 300mm equipment without any manual
interactions.
In the following the results of the TSV formation processwill be
discussed. Electrical results of interconnects will be
presented as well as the results of the impact of the
TSV processing on the logic wafer. Special emphasis was given
tothe influence of mechanical stress on the carrier mobilitycaused
by the copper vias. Therefore transistors have been builtin
proximity to the TSVs. The distances vary from 3 to 58 μm.
It was found that there is a clear correlation between
distanceand linear currents through the PMOS test transistors.
II. TECHNOLOGY
The following summary represents an overview of the process
flow applied on the processor wafer:
1) TSV formation at wafer front-side
2) Patterning of the front-side RDL
3) Temporary wafer bonding
4) Wafer back-side grinding and polish
5) TSV contact patterning6) Patterning of the back-side RDL and
interconnects
7) Assembly of flash memories
As the number of product wafers was very limited most ofthe
development work was done on short loop wafers. Coupontests have
been conducted in addition when applicable. Thecomparison of
results from full wafer short loops and shortloop coupons did show
only minor deviations in DRIE, CVDand PVD processing.
A. TSV formation
1) Lithography
In order to transfer the TSV pattern into the product wafer
a positive photo resist (AZ9260) of 8μm thickness has
beencoated, directly exposed and developed. The resist slope
afterdevelopment was measured to be 84°.
2) BEOL stack dry etchThe BEOL stack consists of
various different materials like
silicon oxide, silicon nitride and low-k materials in a total .
It was etched in a capacitive coupled
plasma reactor at pressures of about 150 mT using oxygen
andfluorocarbon gases. The achieved etching rate in this processwas
850 nm/min and the in-wafer depth non-uniformity was
measured to be
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a) Complete TSV.
b) Sidewall of TSV top at interface BEOL stack to
silicon bulk.
c) TSV top portion showing the oxide stack after
TSV etching.
Figure 3: The SEM images show a TSV after silicon etching. Image
a) gives
an overview of the 20 x 112 μm round hole. In b) the transition
between top
oxide and silicon is shown. A zero-undercut profile could be
achieved. c)gives an impression of the oxide removal during deep
silicon etch.
In Figure 3 c) a slight lateral widening of the BEOL stackcan be
seen which occurs during the TSV silicon etch but theobtained
undercuts are with
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Figure 5: SEM images of the Ti and Cu seed on top of the oxide
isolation. Thesmallest thicknesses deposited are 25 nm for the Ti
and 50 nm Cu in order to
allow a reliable subsequent Cu fill.
6) TSV copper metallization by electrochemical
depositionThe copper TSV metallization was carried out by
electrochemical deposition in an electrolyte with threeadditives
present in the bath. These additives, a suppressor, anaccelerator
and a leveler, are necessary to enable a bottom-upfill mechanism
which allows acceleration of copper plating atthe via bottom and
suppression of plating near the top. To fillthe vias with a
diameter of 20 μm and a depth of 112 μm,
current densities increasing from 1 mA/cm2 to 4 mA/cm2
wereapplied. The wafer was rotating during processing and
anadditional paddle agitation close to the wafer surface wasapplied
to optimize the transport of copper and additives in
theelectrolyte. By analysis of cross-sections it could be shown
that
both the wafer center and the wafer edge are void-free
filled.
a) wafer centre b) wafer edgeFigure 6: Example of Cu filled
TSVs. The images are taken from short-loop
wafers as the limited product wafers could not be analyzed. An
overburden of
5 μm above the TSVs was removed later by CMP.
7) Redistribution metallization on wafer top-sideIn
order to realize the desired tracing between TSVs and
pads for external connections a two-level
redistributionmetallization was manufactured. First the pads of the
processorchip have been opened from isolation oxide by plasma
etching,see Figure 7.
Figure 7: Optical microscope images of the aluminium pads after
opening the
oxide above the pad. Those pads are supposed to electrically
connect theTSVs with the controller chip.
The actual RDL then starts with an adhesion-barrier/seedfilm
consisting of Ti and Cu deposited by PVD. This film is
patterned using photo lithography. The resulting
structures are
filled with Cu using ECD. A low temperature curable polymerforms
the first inter level dielectric (ILD) which is structured aswell.
This loop is repeated two times until the Cu bump levelfinished
with Ni/Au.
8) Wafer temporary bonding, thinning and back-side
redistribution metallizationThe process flow then requires
flipping of the wafer and
temporary bonding to a carrier. As carrier wafer a
siliconsubstrate of about 700μm thickness was used. It is
covered
with an adhesive of about 40μm and the processor wafer
isattached to it with its top-side facing the carrier. The
devicewafer is thinned by a mechanical grinding tool to a
substratethickness of 115 μm. Following an isotropic dry etch
process isapplied in order expose the bottoms of the TSVs by a
softreveal approach.
Figure 8: TSV ends sticking out of the silicon surface of the
thinned wafer
back-side.
This is the prerequisite for the subsequent application of
thesecond redistribution metallization on the wafer back-side,which
is done in the same way as described above for the wafertop-side.
Here the connection between the TSVs and bumpinterface to flash
chips is established.
a) Top of TSV.
50nm25nm
b) Lower sidewall area wereminimum coverage is
observed.
c) Bottom of TSV.
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B. Assembly of flash chips on the processor
wafer
Two options were demonstrated to attach the flash chips tothe
processor wafer. First the flash was assembled to the topside of
the full thickness SEMI wafer. In the second approach –the actual
target flow – the flash chips are connected to the
back side of the thinned processor wafer, which is
stillsupported by a carrier wafer.
After processing of the flash wafers, including waferthinning,
RDL formation, SnAg bumping by electroplating anddicing, the
ensuing flash chips were assembled on the 300 mm
processor wafers using a flip-chip bonder to an accuracy
ofabout 15μm. For the flip-chip assembly, the known good dies(KGD)
are picked up directly from dicing tape or from waffle
packs (in this case chips pre-sorting is required), then
flippedand mounted on the substrate, that is here the processor
wafer.For this, the wafer is fixed on a chuck (planarized and
withouttilt). A recognition system allows the matching of the
picked-up chip with its final position on the substrate wafer.
The
bonder used can combine fine assembly as well as
highthroughput. The D2W mounting includes a reflow and also
anunderfilling step, respectively to interconnect the chip
bumps
with the wafer copper pillars and to ensure a given stiffness
ofthe assembly. The underfilling allows also a safer handling
forfurther processing steps of the D2W stack, especially in
thiscase singulation of the populated processor wafers. Since
thewhole design enables the chip assembly on both wafer sides,flash
chips can be assembled at two different steps of the TSVand RDL
formation, it means during the TSV process (afterTSV filling and
FS-RDL formation) and after its entirecompletion to control and
evaluate its impact. Such assembliesare represented in the Figure
9.
PC
PC
a) Wafer front side. b) Wafer back side.
Figure 9: Images showing the assembled flash chips on the
controller wafer.
On the left side the flash chips assembled to the top of the
full thickness
processor wafer is shown. This is as a shortloop version
for a first evaluation.To the right the final flow is realized with
the flash sitting on the back-side of
the thinned processor wafer.
III. ELECTRICAL RESULTS
Except the RDL resistance and the break down tests allelectrical
analyses have been executed after the complete 3Dintegration
process flow was finished with the flash chipsassembled to the
wafer back-side.
A. Resistance of RDL wiring and TSVs
In order to ensure the electrical functionality the
RDLmetallization has been tested after the completed top-side
processing. With a semi-automated two-point probing
system
a full wafer test was done. As parameter the line resistancewas
chosen. Two independent current paths have been
selected which connect the first with second metal level. It
was found that wiring of all dies had an ohmic resistance of
about 1.3 Ohm with a variance of
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Figure 10: Experimental setup for testing the impact of
mechanical stress
caused by the thermo-mechanical mismatch between copper and
silicon oncharacteristic values of a field effect transistor.
The values determined for the 58 μm distant transistor are
considered as “no TSV” and therefore taken as reference data.As
illustrated in the diagrams in Figure 11 and Figure 12 the
effect of the stress induced be the TSVs is clearly visible.
Transistors as close as 3 μm to the TSV show a drop in the
linear current of 9 % and of the saturation current of
almost 8 %. Other than that the threshold voltage stays
almostconstant (see Figure 13), which coincides with the findings
by
Farooq [6]. The change of the transistor current is also
observed by Mercha [7]. They also see a decrease of the
currents if the direction of the current flow is in radial
direction and an increase if it is in tangential direction to
theTSV. The latter was not tested in our study. However
themagnitude of the current deviation from the case without TSV
is slightly different. The study in [7] sees approximately 2.5
%
less change in the saturation current. This can be explained
by
the difference in the TVS diameter, 5.2 μm compared to 20
μm. It is known that the size of TSVs correlates with the
stress
in the substrate [8].
The results suggest that with regard to future applications
and industrialization a certain exclusion area is needed for
advanced technology nodes. Details of this effect have to be
further investigated with respect to position, geometry and
density of TSVs in proximity to active devices. Allowing a
deviation of the linear current of 3 % a keep out zone of 15
μm would be recommended.
E. Conclusions
A via-last process applied to the wafer front side of acomplete
processed CMOS wafer has been successfullydemonstrated. The major
advantage of this approach is that theTSV formation process can be
executed on a fully processed
product wafer which is still in SEMI standard format.
Nolimitations caused by temporary bonding apply for the front-side
processing. The single process steps of TSV and RDLformation have
been illuminated and results are presented.Breakdown tests and
leakage current measurements proved
good isolation properties against the Si bulk. It could be
shownthat the 20 by 105 μm TSVs in proximity to PMOST
influencetheir transistor currents at about 15 μm distance or
closer.Parametric tests revealed that the whole process chain of
3Dintegration did not degrade the active devices on the
processorwafer. A high yield – considering this was a
non-optimizeddemonstrator – was achieved. In a future application
the flashchip could be replaced by a NFC chip and optional
passiveelements could be integrated.
0 10 20 30 40 50 600,90
0,92
0,94
0,96
0,98
1,00
N o r n a l i z e d
L i n e a r C u r r e n t [ % ]
Distance [μm]
Normalized Linear PMOST Current
Figure 11: Normalized linear current of transistors in different
distances to the
TSVs. I decrease in the current of almost 9 % for the closest
transistors with 3
μm distance can be observed.
0 10 20 30 40 50 600,90
0,92
0,94
0,96
0,98
1,00
Normalized PMOST Saturation Current
N o r m a l i z e d S a t u r a t i o n C u r r e n t [ % ]
Distance [μm]
Figure 12: Saturation current of transistors in correlation to
its distances to theTSVs.
Figure 13: Threshold voltage of the transistors in correlation
the distance. No
significant difference between the close and distant transistors
is visible.
ACKNOWLEDGMENTS
The authors thank NXP especially W. Möring and G.Menges for
supporting the project and providing the electricalmeasurements. We
also thank the team of Fraunhofer IZM-
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