PSP 103 - CEA · 2018-01-15 · PSP 103.6 December 2017 — NXP / CEA-Leti to local and POGFACNUD, PLGFACNUD, PWGFACNUD, PLWGFACNUD, POVSBNUD and PODVSBNUD to binning models. Added

User’s Manual - NXP / CEA-Leti

Issued: 12/2017

PSP 103.6The PSP model is a joint development of CEA-Leti and

NXP Semiconductors

G.D.J. Smit, A.J. Scholten and D.B.M. Klaassen

(NXP Semiconductors)

O. Rozeau, S. Martinie, T. Poiroux and J.C. Barbé

(CEA-Leti)

c© 2004-2017 NXP Semiconductors and 2015-2017 CEA-Leti

NXP / CEA-Leti — December 2017 PSP 103.6

PSP developers (present and past)

• At NXP Semiconductors

– Geert D.J. Smit

– Andries J. Scholten

– Dirk B.M. Klaassen

– Ronald van Langevelde

• At CEA-Leti

– Olivier Rozeau

– Sébastien Martinie

– Thierry Poiroux

– Jean-Charles Barbé

• At Delft University of Technology

– Ramses van der Toorn (from 2011 until 2015)

• At Arizona State University

– Gennady Gildenblat (until 2011)

– Hailing Wang (until 2005)

– Xin Li (until 2011)

– Weimin Wu (until 2011)

Authors’ address O. Rozeau, S. Martinie, [email protected]. Poiroux and J.C. BarbeG.D.J. Smit [email protected]. Scholten [email protected]. Klaassen [email protected]

ii c© 2004-2017 NXP Semiconductors and 2015-2017 CEA-Leti

PSP 103.6 December 2017 — NXP / CEA-Leti

Title: PSP 103.6

Author(s): G.D.J. Smit, A.J. Scholten and D.B.M. Klaassen (NXP Semiconductors)O. Rozeau, S. Martinie, T. Poiroux and J.C. Barbé (CEA-Leti)

Keywords: PSP Model, compact modeling, MOSFET, CMOS, circuit simulation, integrated circuits

Abstract: The PSP model is a compact MOSFET model intended for analog, RF, and digital de-sign. It is jointly developed by NXP Semiconductors and CEA-Leti. (From 2011 to2015, it was jointly developed by NXP Semiconductors and Delft University of Tech-nology. Until 2011, it was jointly developed by NXP Semiconductors and Arizona StateUniversity. The roots of PSP lie in both MOS Model 11 (developed by NXP Semiconduc-tors) and SP (developed at the Pennsylvania State University and later at Arizona StateUniversity). PSP is a surface-potential based MOS Model, containing all relevant phys-ical effects (mobility reduction, velocity saturation, DIBL, gate current, lateral dopinggradient effects, STI stress, etc.) to model present-day and upcoming deep-submicronbulk CMOS technologies. The source/drain junction model, c.q. the JUNCAP2 model,is fully integrated in PSP. This report contains a full description of the PSP model, in-cluding parameter sets, scaling rules, model equations, and a description of the parameterextraction procedure.In December 2005, the Compact Model Council (CMC) has elected PSP as the new in-dustrial standard model for compact MOSFET modeling.Since December 2015, CEA-Leti replaces Delft University of Technology as the support-ing institution.

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iv c© 2004-2017 NXP Semiconductors and 2015-2017 CEA-Leti


Silicon Integration Initiative (Si2) - Compact Model Coalition In-CodeStatement

Copyright 2004-2017 NXP Semiconductors, 2015-2017 Commissariat a l’energie atomique et aux energiesalternatives (CEA), 2012-2015 Delft University of Technology and 2004-2011 Arizona State University Li-censed under the Educational Community License, Version 2.0 (the "License"); you may not use this fileexcept in compliance with the License.

You may obtain a copy of the License at: http://opensource.org/licenses/ECL-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributedon an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express orimplied. See the License for the specific language governing permissions and limitations under the License.

This work is licensed under the Creative Commons Attribution 4.0 International License. To view a copy ofthis license, visit http://creativecommons.org/licenses/by/4.0/ or send a letter to Creative Commons, PO Box1866, Mountain View, CA 94042, USA.

CMC In-Code Statement Revision:

103.6 (PSP), 12/14/2017

200.5.0 (JUNCAP),9/9/2016

c© 2004-2017 NXP Semiconductors and 2015-2017 CEA-Leti v


History of model and documentation

History of the model

April 2005 Release of PSP 100.0 (which includes JUNCAP2 200.0) as part of SiMKit 2.1. A Verilog-Aimplementation of the PSP-model is made available as well. The PSP-NQS model is released as Verilog-Acode only.

August 2005 Release of PSP 100.1 (which includes JUNCAP2 200.1) as part of SiMKit 2.2. Similar tothe previous version, a Verilog-A implementation of the PSP-model is made available as well and the PSP-NQS model is released as Verilog-A code only. Focus of this release was mainly on the optimization of theevaluation speed of PSP. Moreover, the PSP implementation has been extended with operating point output(SiMKit-version only).

March 2006 Release of PSP 101.0 (which includes JUNCAP2 200.1) as part of SiMKit 2.3. PSP 101.0 isnot backward compatible with PSP 100.1. Similar to the previous version, a Verilog-A implementation of thePSP-model is made available as well and the PSP-NQS model is released as Verilog-A code only. Focus of thisrelease was on the implementation of requirements for CMC standardization, especially those which could notpreserve backward compatibility.

June 2006 Release of PSP 102.0 (which includes JUNCAP2 200.1) as part of SiMKit 2.3.2. PSP 102.0 isbackward compatible with PSP 101.0 in all practical cases, provided a simple transformation to the parameterset is applied (see description below). Similar to the previous version, a Verilog-A implementation of thePSP-model is made available as well and the PSP-NQS model is released as Verilog-A code only.

Global parameter sets for PSP 101.0 can be transformed to PSP 102.0 byreplacing DPHIBL (in 102.0 parameter set) by DPHIBO · DPHIBL (from 101.0 parameter set). After thistransformation, the simulation results of PSP 102.0 are identical to those of PSP 101.0 in all practical situations.

October 2006 Release of PSP 102.1 (which includes JUNCAP2 200.2) as part of SiMKit 2.4. PSP 102.1is backward compatible with PSP 102.0. SiMKit 2.4 includes a preliminary implementation of the PSP-NQSmodel. Similar to the previous version, a Verilog-A implementation of the PSP-model is available as well.

October 2007 Release of PSP 102.2 (which includes JUNCAP2 200.3). PSP 102.2 is backward compatiblewith PSP 102.1. This release provides an express version of JUNCAP2.

April 2008 Release of PSP 102.3 (which includes JUNCAP2 200.3) as part of SiMKit 3.1. PSP 102.3 isbackward compatible with PSP 102.2. Focus of this release is on the implementation of asymmetric models forboth junction and overlap regions of the drain side.

November 2008 Release of PSP 103.0 (which includes JUNCAP 200.3) as part of SiMKit 3.2. PSP 103.0 isnot fully backward compatible with PSP 102.3. The main changes are:

• Global, local and binning models are unified. When SWGEO = 1 (default) global model is used. WhenSWGEO = 0 local model is selected. The binning model is invoked if SWGEO is set to 2.

• Added non-uniform doping (NUD) model. The model can be invoked on by setting SWNUD = 1 or 2.When SWNUD = 1, a separate surface potential calculation is carried out and the NUD model does notaffect the CV results. This avoids non-reciprocal capacitances. When SWNUD = 2, the extra surfacepotential calculation is skipped and this may result in non-reciprocal capacitances.Added related model parameters GFACNUDO, GFACNUDL, GFACNUDLEXP, GFACNUDW,GFACNUDLW, VSBNUDO and DVSBNUDO to global, GFACNUD, VSBNUD and DVSBNUD

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to local and POGFACNUD, PLGFACNUD, PWGFACNUD, PLWGFACNUD, POVSBNUD andPODVSBNUD to binning models.

• Added Vth-adjustment model for CV. It can be turned on by setting SWDELVTAC = 1. Note thatthis requires extra computation of surface potentials. Added related model parameters FACNEFFACO,FACNEFFACL, FACNEFFACW, FACNEFFACLW, DELVTACO, DELVTACL, DELVTACLEXP,DELVTACW and DELVTACLW to global, FACNEFFAC and DELVTAC to local andPOFACNEFFAC, PLFACNEFFAC, PWFACNEFFAC, PLWFACNEFFAC, PODELVTAC,PLDELVTAC, PWDELVTAC and PLWDELVTAC to binning model.

• Added external diffusion resistances to source and drain. Added instance parameters NRS and NRD;added model parameters RSH to global and binning, RSE and RDE to local model.

• Modified the geometrical scaling rules of following parameters: VFB, STVFB, DPHIB, STBET andSTTHESAT.

• Modified the binning rule of BETN.

• Removed the effect of FETA from CV.

• Added local parameter values to OP-output.

• Some minor bug-fixes and implementation changes.

May 2009 Release of PSP 103.1 (which includes JUNCAP 200.3) as part of SiMKit 3.3. The main changesare:

• Added external sheet resistance RSHD for drain diffusion (used when SWJUNASYM = 1)

• Bug-fix and minor implementation change in NUD-model

• Minor bug fix in conditional for SP-calculation of overlap areas.

• Added noise source labeling (vA-code only)

December 2009 Release of PSP 103.1.1 (which includes JUNCAP 200.3) as part of SiMKit 3.4. The mainchanges are:

• Modified implementation of the asymmetrical junction model to improve simulation speed of verilog-Acode.

• Modified implementation of the stand-alone JUNCAP2 model.

• Modified implementation of the MULT-scaling factor.

• Modified implementation of NUD model.

• Minor bug fixes.

July 2010 Release of PSP 103.1.2β as part of SiMKit 3.5. The main changes are:

• Changes in the calculation of the surface-potential in the overlap regions and the calculation of the gate-current. These modifications lead to an 7% simulation speed increase, but leads to some small changesin the overlap-capacitance, gate-current, and GIDL-current w.r.t. the previous version.

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December 2012 Release of PSP 103.2.0 (which includes JUNCAP 200.4) as part of SiMKit 4.0.1. The mainchanges are:

• Changes in the calculation of the surface potential in the overlap regions (see July 2010).

• Introduction of self heating. The self heating version of the model has a fifth terminal (dt) to represent thetemperature increase. New parameters: RTH, CTH, STRTH (local model), RTHO, CTHO, STRTHO(global model and binning model).

• Some minor bug-fixes in the calculation of the OP-output.

• Several improvements in the noise-model implementation

– Fixed sign of correlation coefficient (Verilog-A only).

– Simplified implementation and better scaled noise amplitude at internal nodes (Verilog-A only).

– Improved behavior when crossing Vds = 0 at high-frequency.

• Scaled junction parameters added to OP-output.

• New parameter PARAMCHK to set level of clip warnings (SiMKit only).

• More efficient model evaluation when MULT = 0 (SiMKit only).

December 2013 Release of PSP 103.3.0 (which includes JUNCAP 200.4) as part of SiMKit 4.2. The mainchanges are:

• Addition of excess noise, which is important for sub-100-nm channel lengths. This addition is backwardscompatible with PSP 103.2. New parameters: FNTEXC (local model), FNTEXCL (global model), andPOFNTEXC, PLFNTEXC, PWFNTEXC, PLWFNTEXC (binning model).

• Minor bugfixes.

August 2016 Release of PSP 103.4 (which includes JUNCAP 200.5) as part of SiMKit 4.2. PSP 103.4 isbackwards compatible with PSP 103.3. The main changes are:

• Addition of edge MOSFET for modeling of subthreshold hump effect. It can be turned on by settingSWEDGE=1. New parameters: VFBEDGE, STVFBEDGE, DPHIBEDGE, NEFFEDGE, CTEDGE,BETNEDGE, STBETEDGE, PSCEEDGE, PSCEBEDGE, PSCEDEDGE, CFEDGE, CFDEDGE,CFBEDGE, FNTEDGE, NFAEDGE, NFBEDGE, NFCEDGE, EFEDGE (local model), WEDGE,WEDGEW, VFBEDGEO, STVFBEDGEO, STVFBEDGE, STVFBEDGEW, STVFBEDGELW,DPHIBEDGEO, DPHIBEDGEL, DPHIBEDGELEXP, DPHIBEDGEW, DPHIBEDGELW,NSUBEDGEO, NSUBEDGEL, NSUBEDGEW, NSUBEDGELW, CTEDGEO, CTEDGEL, CT-EDGELEXP, FBETEDGE, LPEDGE, BETEDGEW, STBETEDGEO, STBETEDGEL, STBET-EDGEW, STBETEDGELW, PSCEEDGE, PSCEEDGELEXP, PSCEEDGEW, PSCEBEDGEO,PSCEDEDGEO, CFEDGEL, CFEDGELEXP, CFEDGEW, CFDEDGEO, CFBEDGEO, FNTED-GEO, NFAEDGELW, NFBEDGELW, NFCEDGELW, EFEDGEO (global model), andPOVFBEDGE, POSTVFBEDGE, PLSTVFBEDGE, PWSTVFBEDGE, PLWSTVFBEDGE, POD-PHIBEDGE, PLDPHIBEDGE, PWDPHIBEDGE, PLWDPHIBEDGE, PONEFFEDGE,PLNEFFEDGE, PWNEFFEDGE, PLWNEFFEDGE, POCTEDGE, PLCTEDGE, PWCTEDGE,PLWCTEDGE, POBETNEDGE, PLBETNEDGE, PWBETNEDGE, PLWBETNEDGE,POSTBETEDGE,PLSTBETEDGE, PWSTBETEDGE, PLWSTBETEDGE, POPSCEEDGE, PLP-SCEEDGE, PWPSCEEDGE, PLWPSCEEDGE, POPSCEBEDGE, POPSCEDEDGE,POCFEDGE, PLCFEDGE, PWCFEDGE, PLWCFEDGE, POCFDEDGE, POCFBEDGE, POFNT-EDGE, PONFAEDGE, PLNFAEDGE, PWNFAEDGE, PLWNFAEDGE, PONFBEDGE, PLNF-BEDGE, PWNFBEDGE, PLWNFBEDGE, PONFCEDGE, PLNFCEDGE, PWNFCEDGE, PLWN-FCEDGE, POEFEDGE (binning model).

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• New switch to active/disable the induced gate noise SWIGN (default value is 1 for backwards compati-bility).

• New parameters for modeling of short channel effects on subthreshold slope:

– Subthrehold slope degradation for short channel transistors: PSCE (local model), PSCEL,PSCELEXP, PSCEW (global model), and POPSCE, PLPSCE, PWPSCE, PLWPSCE (binningmodel).

– Subthrehold slope dependence with drain voltage: PSCED (local model), PSCEDO (global model),and POPSCED (binning model).

– Subthrehold slope dependence with bulk voltage: PSCEB (local model), PSCEBO (global model),and POPSCEB (binning model).

• New parameter of JUNCAP model: Coefficient for reverse breakdown current limitation FREV.

• Minor bugfixes.

April 2017 Release of PSP 103.5 (which includes JUNCAP 200.5). PSP 103.5 is backwards compatible withPSP 103.4. The main changes are:

• Addition of new mobility parameters for coulomb scattering effect: THECS, STTHECS (local model),THECSO, STTHECSO (global model), and POTHECS, POSTTHECS (binning model).

• Addition of new parameters for quadratic temperature dependence of flatband voltage: ST2VFB (localmodel), ST2VFBO (global model), and POST2VFB (binning model).

December 2017 Release of PSP 103.6 (which includes JUNCAP 200.5). PSP 103.6 is backwards compatiblewith PSP 103.5. The changes are:

• Induced gate noise: clipped value of migid using the correlation factor c_igid.

• Thermal noise of edge transistor: bug fix to avoid possible division by zero during the calculation ofredge.

• Improvement of gm/Id in weak inversion: new model of interface states.

• Addition of new parameter NSUBEDGELEXP: exponent for channel length dependence of edge tran-sistor substrate doping.

• Minimum values of calculated local parameters NOV and NOVD in global mode: now in lines withminimum values of local model parameters.

History of the documentation

April 2005 First release of PSP (PSP 100.0) documentation.

August 2005 Documentation updated for PSP 100.1, errors corrected and new items added.

March 2006 Documentation adapted to PSP 101.0. Added more details on noise-model implementation anda full description of the NQS-model.

June 2006 Documentation adapted to PSP 102.0 and some errors corrected.

October 2006 Documentation adapted to PSP 102.1 and some errors corrected.

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October 2007 Documentation adapted to PSP 102.2 and some errors corrected.

April 2008 Documentation adapted to PSP 102.3 and some errors corrected.

November 2008 Documentation adapted to PSP 103.0 and some errors corrected.

June 2009 Documentation adapted to PSP 103.1 and some errors corrected.

December 2012 Documentation adapted to PSP 103.2.

December 2013 Documentation adapted to PSP 103.3 and some errors corrected.

August 2016 Documentation adapted to PSP 103.4.

April 2017 Documentation adapted to PSP 103.5.

December 2017 Documentation adapted to PSP 103.6

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Contents

1 Introduction 1

1.1 Origin and purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Structure of PSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.3 Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3.1 SiMKit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Constants and Parameters 4

2.1 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 Parameter clipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.3 Circuit simulator variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.4 Model constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.5 Model parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.5.1 Instance parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.5.2 Intrinsic model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.5.3 Parameters for stress model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.5.4 Parameters for well proximity effect model . . . . . . . . . . . . . . . . . . . . . . . 31

2.5.5 Parameters for source-bulk and drain-bulk junction model . . . . . . . . . . . . . . . 32

2.5.6 Parameters for parasitic resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

2.5.7 Parameters for self heating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2.5.8 Parameters for NQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

3 Geometry dependence and Other effects 43

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.2 Geometrical scaling rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.3 Binning equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.4 Parasitic resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.5 Stress effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.5.1 Layout effects for multi-finger devices . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.5.2 Layout effects for regular shapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.5.3 Parameter modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.6 Well proximity effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.6.1 Parameters for pre-layout simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

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3.6.2 Calculation of parameter modifications . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.7 Asymmetric junctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4 PSP Model Equations 71

4.1 Internal Parameters (including Temperature Scaling) . . . . . . . . . . . . . . . . . . . . . . 71

4.2 Current Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

4.2.1 Conditioning of Terminal Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

4.2.2 Short Channel effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.2.3 Bias-Dependent Body Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

4.2.4 Interface States Including Bias Dependences . . . . . . . . . . . . . . . . . . . . . . 78

4.2.5 Surface Potential at Source Side and Related Variables . . . . . . . . . . . . . . . . . 78

4.2.6 Drain Saturation Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4.2.7 Surface Potential at Drain Side and Related Variables . . . . . . . . . . . . . . . . . . 81

4.2.8 Mid-Point Surface Potential and Related Variables . . . . . . . . . . . . . . . . . . . 82

4.2.9 Polysilicon Depletion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

4.2.10 Potential Mid-Point Inversion Charge and Related Variables . . . . . . . . . . . . . . 83

4.2.11 Drain-Source Channel Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

4.2.12 Surface Potential in Gate Overlap Regions . . . . . . . . . . . . . . . . . . . . . . . . 85

4.2.13 Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

4.2.14 Gate-Induced Drain/Source Leakage Current . . . . . . . . . . . . . . . . . . . . . . 88

4.2.15 Edge Transistor Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

4.2.16 Impact Ionization or Weak-Avalanche . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.2.17 Total Terminal Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.3 Charge Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

4.3.1 Quantum-Mechanical Corrections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

4.3.2 Intrinsic Charge Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

4.3.3 Extrinsic Charge Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

4.3.4 Total Terminal Charges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

4.4 Noise Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

4.4.1 Flicker noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

4.4.2 Thermal noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

4.4.3 Shot noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

4.4.4 Edge transistor noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

4.5 Self heating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

5 Non-quasi-static RF model 99

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

5.2 NQS-effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

5.3 NQS Model Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

5.3.1 Internal constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

5.3.2 Position independent quantities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

5.3.3 Position dependent surface potential and charge . . . . . . . . . . . . . . . . . . . . . 101

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5.3.4 Cubic spline interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5.3.5 Continuity equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5.3.6 Non-quasi-static terminal charges . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

6 Embedding 106

6.1 Model selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

6.2 Case of parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

6.3 Embedding PSP in a Circuit Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

6.3.1 Selection of device type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

6.4 Integration of JUNCAP2 in PSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

6.5 Verilog-A versus C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

6.5.1 Implementation of GMIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

6.5.2 Implementation of parasitic resistances . . . . . . . . . . . . . . . . . . . . . . . . . 110

6.5.3 Implementation of the noise-equations . . . . . . . . . . . . . . . . . . . . . . . . . . 111

6.5.4 Clip warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

7 Parameter extraction 117

7.1 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

7.2 Extraction of local parameters at room temperature . . . . . . . . . . . . . . . . . . . . . . . 118

7.3 Extraction of Temperature Scaling Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 122

7.4 Extraction of Geometry Scaling Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

7.5 Summary – Geometrical scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

7.6 Extraction of Binning Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

7.6.1 Binning of BETN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

8 DC Operating Point Output 127

A Auxiliary Equations 137

B Layout parameter calculation 139

B.1 Stress parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

B.1.1 Layout effects for irregular shapes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

B.2 Well proximity effect parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

c© 2004-2017 NXP Semiconductors and 2015-2017 CEA-Leti xiii


Section 1

Introduction

1.1 Origin and purpose

The PSP model is a compact MOSFET model intended for analog, RF, and digital design. It is jointly developedby NXP Semiconductors and CEA-Leti. (From 2011 until 2015, it was jointly developed by NXP Semicon-ductors and Delft University of Technology. Until 2011, it was jointly developed by NXP Semiconductorsand Arizona State University. The roots of PSP lie in both MOS Model 11 (developed by NXP Semiconduc-tors) and SP (developed at the Pennsylvania State University and later at Arizona State University). PSP is asurface-potential based MOS Model, containing all relevant physical effects (mobility reduction, velocity satu-ration, DIBL, gate current, lateral doping gradient effects, STI stress, etc.) to model present-day and upcomingdeep-submicron bulk CMOS technologies. The source/drain junction model, c.q. the JUNCAP2 model, is fullyintegrated in PSP.

PSP not only gives an accurate description of currents, charges, and their first order derivatives (i.e. transcon-ductance, conductance and capacitances), but also of the higher order derivatives, resulting in an accuratedescription of electrical distortion behavior. The latter is especially important for analog and RF circuit design.The model furthermore gives an accurate description of the noise behavior of MOSFETs. Finally, PSP has anoption for simulation of non-quasi-static (NQS) effects.

The source code of PSP and the most recent version of this documentation are available on the PSP model website: http://www.cea.fr/cea-tech/leti/pspsupport and the NXP Semiconductors web site:www.nxp.com/models.

1.2 Structure of PSP

The PSP model has a hierarchical structure, similar to that of MOS Model 11 and SP. This means that there isa strict separation of the geometry scaling in the global model and the model equations in the local model.

As a consequence, PSP can be used at either one of two levels.

• Global level One uses a global parameter set, which describes a whole geometry range. Combinedwith instance parameters (such as L and W ), a local parameter set is internally generated and furtherprocessed at the local level in exactly the same way as a custom-made local parameter set.

• Local level One uses a custom-made local parameter set to simulate a transistor with a specific geometry.Temperature scaling is included at this level.

The set of parameters which occur in the equations for the various electrical quantities is called the localparameter set. In PSP, temperature scaling parameters are included in the local parameter set. An overview ofthe local parameters in PSP is given in Section 2.5.2. Each of these parameters can be determined by purelyelectrical measurements. As a consequence, a local parameter set gives a complete description of the electricalproperties of a device of one particular geometry.

c© 2004-2017 NXP Semiconductors and 2015-2017 CEA-Leti 1


GlobalqparameterqsetGeometryqscalling

Globalqlevel

Localqlevel Localqparameterqset

L, W

SA, SB, SDStressqparameters

Wellqproximityqeffectq(WPE)qparametersSCA, SCB, SCC, SC

Stressqmodel

WPEqmodel

Localqparameterqset

Temperatureqscalling

Modelqequations

T

TerminalqvoltagesCurrentsChargesNoise

Localqmodel

A

Figure 1.1: Simplified schematic overview of PSP’s hierarchical structure.

Since most of these (local) parameters scale with geometry, all transistors of a particular process can be de-scribed by a (larger) set of parameters, called the global parameter set. An overview of the global parametersin PSP is given in Section 2.5.2. Roughly speaking, this set contains all local parameters for a long/wide deviceplus a number of sensitivity coefficients. From the global parameter set, one can obtain a local parameter set fora specific device by applying a set of scaling rules (see Section 3.2). The geometric properties of that specificdevice (such as its length and width) enter these scaling rules as instance parameters.

From PSP 101.0 onwards it is possible to use a set of binning rules (see Section 3.3) as an alternative to thegeometrical (physics based) scaling rules. These binning rules come with their own set of parameters (seeSection 2.5.2). Similar to the geometrical scaling rules, the binning rules yield a local parameter set which isused as input for the local model.

PSP is preferably used at global level when designing a circuit in a specific technology for which a globalparameter set is available. On the other hand, using PSP at local level can be advantageous during parameterextraction.

As an option, it is possible to deal with the modifications of transistor properties due to stress and well proximityeffect (WPE). In PSP, this is implemented by additional sets of transformation rules, which are optionallyapplied to the intermediate local parameter set generated at the global level. The parameters associated withthe stress and WPE models are consequently part of the global parameter set (both geometrical and binning).

The model structure described above is schematically depicted in Fig. 1.1.

The JUNCAP2 model is implemented in such a way that the same set of JUNCAP2 parameters can be used atboth the global and the local level. This is further explained in Section 6.4.

2 c© 2004-2017 NXP Semiconductors and 2015-2017 CEA-Leti


1.3 Availability

The PSP model developers (CEA-Leti and NXP Semiconductors) distribute the PSP code in two formats:

1. Verilog-A code

2. C-code (as part of SiMKit-library)

The C-version is automatically generated from the Verilog-A version by the software package ADMS [1].This procedure guarantees the two implementations to contain identical equations. Nevertheless—due to somespecific limitations/capabilities of the two formats—there are a few minor differences, which are described inSection 6.5.

1.3.1 SiMKit

SiMKit is a simulator-independent compact transistor model library. Simulator-specific connections are handledthrough so-called adapters that provide the correct interfacing to the circuit simulator of choice. Currently,adapters to the following circuit simulators are provided:

1. Spectre (Cadence)

2. Pstar (NXP Semiconductors)

3. ADS (Agilent)

Some other circuit simulators vendors provide their own SiMKit adapter, such that simulations with models inSiMKit are possible.



Section 2

Constants and Parameters

2.1 Nomenclature

The nomenclature of the quantities listed in the following sections has been chosen to express their purposeand their relation to other quantities and to preclude ambiguity and inconsistency. Throughout this document,all PSP parameter names are printed in boldface capitals. Parameters which refer to the long transistor limitand/or the reference temperature have a name containing an ‘O’, while the names of scaling parameters endwith the letter ‘L’ and/or ‘W’ for length or width scaling, respectively. Parameters for temperature scaling startwith ‘ST’, followed by the name of the parameter to which the temperature scaling applies. Parameters usedfor the binning model start with ‘PO’, ‘PL’, ‘PW’, or ‘PLW’, followed by the name of the local parameterthey refer to.

2.2 Parameter clipping

For most parameters, a maximum and/or minimum value is given in the tables below. In PSP, all parametersare limited (clipped) to this pre-specified range in order to prevent difficulties in the numerical evaluation ofthe model, such as division by zero.

N.B. After computation of the scaling rules (either physical or binning), stress and well proximity effect equa-tions, the resulting local parameters are subjected to the clipping values as given in Section 2.5.2.

2.3 Circuit simulator variables

External electrical variables

The definitions of the external electrical variables are illustrated in Fig. 2.1. The relationship between theseexternal variables and the internal variables used in Chapter 4 is given in Fig. 6.1.

Symbol Unit Description

V eD V Potential applied to drain nodeV eG V Potential applied to gate nodeV eS V Potential applied to source nodeV eB V Potential applied to bulk nodeIeD A DC current into drain node

continued on next page. . .



. . . continued from previous page


IeG A DC current into gate nodeIeS A DC current into source nodeIeB A DC current into bulk nodeSefl A2s Spectral density of flicker noise current in the channelSefl,edge A2s Spectral density of flicker noise current of edge transistorSeid A2s Spectral density of thermal noise current in the channelSeid,edge A2s Spectral density of thermal noise current of edge transistorSeig,S A2s Spectral density of induced gate noise at source sideSeig,D A2s Spectral density of induced gate noise at drain sideSeigs A2s Spectral density of gate current shot noise at source sideSeigd A2s Spectral density of gate current shot noise at drain sideSej,S A2s Spectral density of source junction shot noiseSej,D A2s Spectral density of drain junction shot noiseSeigid A2s Cross spectral density between Seid and (SeigS or SeigD)

Other circuit simulator variables

Next to the electrical variables described above, the quantities in the table below are also provided to the modelby the circuit simulator.


TAC Ambient circuit temperature

fop Hz Operation frequency

2.4 Model constants

In the following table the symbolic representation, the value and the description of the various physical con-stants used in the PSP model are given.

No. Symbol Unit Value Description

1 T0 K 273.15 Offset between Celsius and Kelvin tempera-ture scale

2 kB J/K 1.3806505 · 10−23 Boltzmann constant3 ~ J s 1.05457168 · 10−34 Reduced Planck constant4 q C 1.6021918 · 10−19 Elementary unit charge5 m0 kg 9.1093826 · 10−31 Electron rest mass6 ε0 F/m 8.8541878176 · 10−12 Permittivity of free space7 εr,Si – 11.8 Relative permittivity of silicon8 QMN V m

43 C−

23 5.951993 Constant of quantum-mechanical behavior of

electrons9 QMP V m

43 C−

23 7.448711 Constant of quantum-mechanical behavior of

holes



Sigs Sig,S Sig,D Sigd

Sfl, Sfl,edge

Sj,DSj,S

iG

VD

VB

VS

VG

iS

e

e

e

e

e

e

iD

iBe

e

e

Sid, Sid,edge

e e e

ee

e e

e e

ieD = IeD +dQeDdt

ieG = IeG +dQeGdt

ieS = IeS +dQeSdt

ieB = IeB +dQeBdt

Figure 2.1: Definition of external electrical quantities.

2.5 Model parameters

In this section all parameters of the PSP-model are described. The parameters for the intrinsic MOS model,the stress and well proximity effect models and the junction model are given in separate tables. The completeparameter list for each of the model entry levels is composed of several parts, as indicated in the table below.

Entry level Sections

Global (geometrical scaling) 2.5.1 (instance parameters)2.5.2 (intrinsic MOS)2.5.3 (stress)2.5.4 (well proximity effect)2.5.5 (junctions)2.5.6 (parasitic resistances)

Binning 2.5.1 (instance parameters)2.5.2 (intrinsic MOS)2.5.3 (stress)2.5.4 (well proximity effect)2.5.5 (junctions)2.5.6 (parasitic resistances)

Local 2.5.1 (instance parameters)2.5.2 (intrinsic MOS)2.5.5 (junctions)2.5.6 (parasitic resistances)



2.5.1 Instance parameters

The instant parameters for global, local and binning models are listed in the table below. The last column ofGeo. shows for which value of SWGEO the listed parameter is used. Note that, as explained in Section 6.4,the instance parameters for the JUNCAP2 model are used at the local level as well.

No. Name Unit Default Min. Max. Description Geo.

0 L m 10−6 10−9 − Drawn channel length 1, 21 W m 10−6 10−9 − Drawn channel width (total width) 1, 22 ABSOURCE m2 10−12 0 − Source junction area 0, 1, 23 LSSOURCE m 10−6 0 − STI-edge part of source junction

perimeter0, 1, 2

4 LGSOURCE m 10−6 0 − Gate-edge part of source junctionperimeter

0, 1, 2

5 ABDRAIN m2 10−12 0 − Drain junction area 0, 1, 26 LSDRAIN m 10−6 0 − STI-edge part of drain junction

perimeter0, 1, 2

7 LGDRAIN m 10−6 0 − Gate-edge part of drain junctionperimeter

0, 1, 2

8 AS m2 10−12 0 − Source junction area (alternativespec.)

0, 1, 2

9 PS m 10−6 0 − Source STI-edge perimeter(alternative spec.)

0, 1, 2

10 AD m2 10−12 0 − Drain junction area (alternativespec.)

0, 1, 2

11 PD m 10−6 0 − Drain STI-edge perimeter(alternative spec.)

0, 1, 2

12 JW m 1 · 10−6 0 − Junction width 013 DELVTO V 0 − − Threshold voltage shift parameter 0, 1, 214 FACTUO – 1 0 − Zero-field mobility pre-factor 0, 1, 215 DELVTOEDGE V 0 − − Threshold voltage shift parameter

of edge transistor0, 1, 2

16 FACTUOEDGE – 1 0 − Zero-field mobility pre-factor ofedge transistor

0, 1, 2

17 SA m 0 − − Distance between OD-edge andpoly at source side

1, 2

18 SB m 0 − − Distance between OD-edge andpoly at drain side

1, 2

19 SD m 0 − − Distance between neighboringfingers

1, 2

20 SCA – 0 0 − Integral of the first distributionfunction for scattered well dopant

1, 2

21 SCB – 0 0 − Integral of the second distributionfunction for scattered well dopant

1, 2

22 SCC – 0 0 − Integral of the third distributionfunction for scattered well dopant

1, 2

23 SC m 0 − − Distance between OD edge andnearest well edge

1, 2

24 NRS – 0 − − Number of squares of sourcediffusion

1, 2






25 NRD – 0 − − Number of squares of draindiffusion

1, 2

26 NGCON – 1 1 2 Number of gate contacts 1, 227 XGW m 10−7 − − Distance from the gate contact to

the channel edge1, 2

28 NF – 1 1 − Number of fingers; internallyrounded to the nearest integer

1, 2

29 MULT – 1 0 − Number of devices in parallel 0, 1, 2

Note that if both SA and SB are set to 0 the stress-equations are not computed. If SCA, SCB, SCC and SC areall set to 0 the well proximity effect equations are not computed.

The switching parameter SWJUNCAP is used to determine the meaning and usage of the junction instanceparameters, where AB (junction area), LS (STI-edge part of junction perimeter), and LG (gate-edge part ofjunction perimeter) are the instance parameters of a single instance (source or drain) of the JUNCAP2 model.

source drain

SWJUNCAP AB LS LG AB LS LG

0 0 0 0 0 0 01 ABSOURCE LSSOURCE LGSOURCE ABDRAIN LSDRAIN LGDRAIN2 AS PS WE AD PD WE

3 AS PS−WE WE AD PD−WE WE

At the local level, the switching parameter SWJUNCAP is used to determine the meaning and usage of thejunction instance parameters, where AB (junction area), LS (STI-edge part of junction perimeter), and LG(gate-edge part of junction perimeter) are the instance parameters of a single instance (source or drain) of theJUNCAP2 model. Because the transistor width W is not available at the local level, an additional instanceparameter JW (junction width) is required when SWJUNCAP = 2 or 3.

source drain

SWJUNCAP AB LS LG AB LS LG

0 0 0 0 0 0 01 ABSOURCE LSSOURCE LGSOURCE ABDRAIN LSDRAIN LGDRAIN2 AS PS JW AD PD JW3 AS PS− JW JW AD PD− JW JW



2.5.2 Intrinsic model

The model parameters for the intrinsic part of the MOSFET are listed in the table below. The last column—labeled ‘Geo.’—shows for which value of SWGEO the parameter is used. The convention used in this tableis that, if a scaling rule exists for a local parameter its scaling (global and/or binning) parameters are groupedunderneath. Note also some parameters do not have their local counterparts.


0 LEVEL – 103 − − Model selection parameter; seeSec. 6.1

0, 1, 2

1 TYPE – 1 −1 1 Channel type parameter; 1↔NMOS, −1↔ PMOS1

0, 1, 2

2 TR C 21 −273 − Reference temperature 0, 1, 23 DTA K 0 − − Temperature offset w.r.t. ambient

circuit temperature0, 1, 2

Switches

4 PARAMCHK – 0 − − Level of clip-warning info2 0, 1, 25 SWGEO – 1 0 2 Flag for geometrical model (0↔

local, 1↔ global, 2↔ binning )0, 1, 2

6 SWIGATE – 0 0 1 Flag for gate current (0↔ “off”) 0, 1, 27 SWIMPACT – 0 0 1 Flag for impact ionization current

(0↔ “off”)0, 1, 2

8 SWGIDL – 0 0 1 Flag for GIDL/GISL current (0↔“off”)

0, 1, 2

9 SWJUNCAP – 0 0 3 Flag for JUNCAP (0↔ “off”) 0, 1, 210 SWJUNASYM – 0 − − Flag for asymmetric junctions (0

↔ “off”)0, 1, 2

11 SWNUD – 0 0 2 Flag for NUD-effect (0↔ “off”) 0, 1, 212 SWEDGE – 0 0 1 Flag for drain current of edge

transistors (0↔ “off”)0, 1, 2

13 SWDELVTAC – 0 0 1 Flag for separate charge calculation(0↔ “off”)

0, 1, 2

14 QMC – 1 0 − Quantum-mechanical correctionfactor

0, 1, 2

Labels for binning set

15 LMIN m 0 − − Dummy parameter to label binningset

2

16 LMAX m 1 − − Dummy parameter to label binningset

2

17 WMIN m 0 − − Dummy parameter to label binningset

2

18 WMAX m 1 − − Dummy parameter to label binningset

2

Process Parameters


1See Section 6.3.1 for more information on usage of TYPE in various simulators.2Only in SiMKit-version of PSP. See Section 6.5.4 for more information.





19 LVARO m 0 − − Geometry independent differencebetween actual and programmedpoly-silicon gate length

1, 2

20 LVARL – 0 − − Length dependence of ∆LPS 1, 221 LVARW – 0 − − Width dependence of ∆LPS 1, 222 LAP m 0 − − Effective channel length reduction

per side due to lateral diffusion ofsource/drain dopant ions

1, 2

23 WVARO m 0 − − Geometry independent differencebetween actual and programmedfield-oxide opening

1, 2

24 WVARL – 0 − − Length dependence of ∆WOD 1, 225 WVARW – 0 − − Width dependence of ∆WOD 1, 226 WOT m 0 − − Effective reduction of channel

width per side due to lateraldiffusion of channel-stop dopantions

1, 2

27 DLQ m 0 − − Effective channel length offset forCV

1, 2

28 DWQ m 0 − − Effective channel width offset forCV

1, 2

29 VFB V −1 − − Flat-band voltage at TR 0

30 VFBO V −1 − − Geometry-independent part 131 VFBL V 0 − − Length dependence 132 VFBW V 0 − − Width dependence 133 VFBLW V 0 − − Area dependence 1

34 POVFB V −1 − − Geometry independent part 235 PLVFB V 0 − − Length dependence 236 PWVFB V 0 − − Width dependence 237 PLWVFB V 0 − − Length times width dependence 2

38 STVFB V/K 5 · 10−4 − − Temperature dependence of VFB 0

39 STVFBO V/K 5 · 10−4 − − Geometry-independent part 140 STVFBL V/K 0 − − Length dependence 141 STVFBW V/K 0 − − Width dependence 142 STVFBLW V/K 0 − − Area dependence 1

43 POSTVFB V/K 5 · 10−4 − − Geometry independent part 244 PLSTVFB V/K 0 − − Length dependence 245 PWSTVFB V/K 0 − − Width dependence 246 PLWSTVFB V/K 0 − − Length times width dependence 2

47 ST2VFB K−1 0 − − Quadratic temperature dependenceof VFB

0

48 ST2VFBO K−1 0 − − Geometry-independent part 1






49 POST2VFB K−1 0 − − Geometry independent part 2

50 TOX m 2 · 10−9 10−10 − Gate oxide thickness 0

51 TOXO m 2 · 10−9 10−10 − Gate oxide thickness 1

52 POTOX m 2 · 10−9 − − Geometry independent part 2

53 EPSROX – 3.9 1 − Relative permittivity of gatedielectric

0

54 EPSROXO – 3.9 1 − Geometry independent part 1

55 POEPSROX – 3.9 1 − Geometry independent part 2

56 NEFF m−3 5 · 1023 1020 1026 Substrate doping 0

57 NSUBO m−3 3 · 1023 1020 − Geometry independent substratedoping

1

58 NSUBW – 0 − − Width dependence of substratedoping due to segregation

1

59 WSEG m 10−8 10−10 − Characteristic length forsegregation of substrate doping

1

60 NPCK m−3 1024 0 − Pocket doping level 161 NPCKW – 0 − − Width dependence of NPCK due

to segregation1

62 WSEGP m 10−8 10−10 − Characteristic length forsegregation of pocket doping

1

63 LPCK m 10−8 10−10 − Characteristic length for lateraldoping profile

1

64 LPCKW – 0 − − Width dependence of LPCK due tosegregation

1

65 FOL1 – 0 − − First order length dependence ofshort channel body-effect

1

66 FOL2 – 0 − − Second order length dependence ofshort channel body-effect

1

67 PONEFF m−3 5 · 1023 − − Geometry independent part 268 PLNEFF m−3 0 − − Length dependence 269 PWNEFF m−3 0 − − Width dependence 270 PLWNEFF m−3 0 − − Length times width dependence 2

71 FACNEFFAC – 1 0 − Pre-factor for effective substratedoping in separate chargecalculation whenSWDELVTAC = 1

0

72 FACNEFFACO – 1 0 − Geometry independent part 173 FACNEFFACL – 0 − − Length dependence 174 FACNEFFACW – 0 − − Width dependence 175 FACNEFFACLW – 0 − − Area dependence 1

76 POFACNEFFAC – 1 − − Geometry independent part 2






77 PLFACNEFFAC – 0 − − Length dependence 278 PWFACNEFFAC – 0 − − Width dependence 279 PLWFACNEFFAC – 0 − − Area dependence 2

80 GFACNUD – 1 0.01 − Bodyfactor change due toNUD-effect

0

81 GFACNUDO – 1 − − Geometry independent part 182 GFACNUDL – 0 − − Length dependence 183 GFACNUDLEXP – 1 − − Exponent for length dependence 184 GFACNUDW – 0 − − Width dependence 185 GFACNUDLW – 0 − − Area dependence 1

86 POGFACNUD – 1 − − Geometry independent part 287 PLGFACNUD – 0 − − Length dependence 288 PWGFACNUD – 0 − − Width dependence 289 PLWGFACNUD – 0 − − Area dependence 2

90 VSBNUD V 0 0 − Lower VSB-value for NUD-effect 0

91 VSBNUDO V 0 − − Geometry independent part 1

92 POVSBNUD V 0 − − Geometry independent part 2

93 DVSBNUD V 1 0.1 − VSB-range for NUD-effect 0

94 DVSBNUDO V 1 − − Geometry independent part 1

95 PODVSBNUD V 1 − − Geometry independent part 2

96 VNSUB V 0 − − Effective doping bias-dependenceparameter

0

97 VNSUBO V 0 − − Geometry independent part 1

98 POVNSUB V 0 − − Geometry independent part 2

99 NSLP V 0.05 10−3 − Effective doping bias-dependenceparameter

0

100 NSLPO V 0.05 − − Geometry independent part 1

101 PONSLP V 0.05 − − Geometry independent part 2

102 DNSUB V−1 0 0 1 Effective doping bias-dependenceparameter

0

103 DNSUBO V−1 0 − − Geometry independent part 1

104 PODNSUB V−1 0 − − Geometry independent part 2

105 DPHIB V 0 − − Offset of ϕB 0

106 DPHIBO V 0 − − Geometry independent part 1107 DPHIBL V 0 − − Length dependence 1108 DPHIBLEXP – 1 − − Exponent for length dependence 1






109 DPHIBW V 0 − − Width dependence 1110 DPHIBLW V 0 − − Area dependence 1

111 PODPHIB V 0 − − Geometry independent part 2112 PLDPHIB V 0 − − Length dependence 2113 PWDPHIB V 0 − − Width dependence 2114 PLWDPHIB V 0 − − Length times width dependence 2

115 DELVTAC V 0 − − Offset of ϕB in separate chargecalculation whenSWDELVTAC = 1

0

116 DELVTACO V 0 − − Geometry independent part 1117 DELVTACL V 0 − − Length dependence 1118 DELVTACLEXP – 1 − − Exponent for length dependence 1119 DELVTACW V 0 − − Width dependence 1120 DELVTACLW V 0 − − Area dependence 1

121 PODELVTAC V 0 − − Geometry independent part 2122 PLDELVTAC V 0 − − Length dependence 2123 PWDELVTAC V 0 − − Width dependence 2124 PLWDELVTAC V 0 − − Length times width dependence 2

125 NP m−3 1026 0 − Gate poly-silicon doping 0

126 NPO m−3 1026 − − Geometry-independent part 1127 NPL – 0 − − Length dependence 1

128 PONP m−3 1026 − − Geometry independent part 2129 PLNP m−3 0 − − Length dependence 2130 PWNP m−3 0 − − Width dependence 2131 PLWNP m−3 0 − − Length times width dependence 2

132 TOXOV m 2 · 10−9 10−10 − Overlap oxide thickness 0

133 TOXOVO m 2 · 10−9 10−10 − Geometry independent part 1

134 POTOXOV m 2 · 10−9 − − Geometry independent part 2

135 TOXOVD m 2 · 10−9 10−10 − Overlap oxide thickness for drainside

0

136 TOXOVDO m 2 · 10−9 10−10 − Geometry independent part 1

137 POTOXOVD m 2 · 10−9 − − Geometry independent part 2

138 LOV m 0 0 − Overlap length for overlapcapacitance

1

139 LOVD m 0 0 − Overlap length for gate/drainoverlap capacitance

1

140 NOV m−3 5 · 1025 1020 1027 Effective doping of overlap region 0

141 NOVO m−3 5 · 1025 − − Geometry independent part 1






142 PONOV m−3 5 · 1025 − − Geometry independent part 2143 PLNOV m−3 0 − − Length dependence 2144 PWNOV m−3 0 − − Width dependence 2145 PLWNOV m−3 0 − − Length times width dependence 2

146 NOVD m−3 5 · 1025 1020 1027 Effective doping of overlap regionfor drain side

0

147 NOVDO m−3 5 · 1025 − − Geometry independent part 1

148 PONOVD m−3 5 · 1025 − − Geometry independent part 2149 PLNOVD m−3 0 − − Length dependence 2150 PWNOVD m−3 0 − − Width dependence 2151 PLWNOVD m−3 0 − − Length times width dependence 2

Interface States Parameters

152 CT – 0 0 − Interface states factor 0

153 CTO – 0 − − Geometry-independent part 1154 CTL – 0 − − Length dependence 1155 CTLEXP – 1 − − Exponent for length dependence 1156 CTW – 0 − − Width dependence 1157 CTLW – 0 − − Area dependence 1

158 POCT – 0 − − Geometry independent part 2159 PLCT – 0 − − Length dependence 2160 PWCT – 0 − − Width dependence 2161 PLWCT – 0 − − Length times width dependence 2

162 CTG – 0 0 − Gate voltage dependence ofinterface states factor

0

163 CTGO – 0 − − Geometry-independent part 1

164 POCTG – 0 − − Geometry independent part 2

165 CTB – 0 − − Bulk voltage dependence ofinterface states factor

0

166 CTBO – 0 − − Geometry-independent part 1

167 POCTB – 0 − − Geometry independent part 2

168 STCT – 1 − − Temperature dependence of CT 0

169 STCTO – 1 − − Geometry-independent part 1

170 POSTCT – 1 − − Geometry independent part 2

DIBL Parameters

171 CF – 0 0 − DIBL parameter 0

172 CFL – 0 − − Length dependence 1






173 CFLEXP – 2 − − Exponent for length dependence 1174 CFW – 0 − − Width dependence 1

175 POCF – 0 − − Geometry independent part 2176 PLCF – 0 − − Length dependence 2177 PWCF – 0 − − Width dependence 2178 PLWCF – 0 − − Length times width dependence 2

179 CFB V−1 0 0 1 Back-bias dependence of CF 0

180 CFBO V−1 0 − − Geometry independent part 1

181 POCFB V−1 0 − − Geometry independent part 2

182 CFD V−1 0 0 − Drain voltage dependence of CF 0

183 CFDO V−1 0 − − Geometry independent part 1

184 POCFD V−1 0 − − Geometry independent part 2

Subthreshold Slope Parameters

185 PSCE – 0 0 − Subthreshold slope coefficient forshort channel transistor

0

186 PSCEL – 0 − − Length dependence 1187 PSCELEXP – 2 − − Exponent for length dependence 1188 PSCEW – 0 − − Width dependence 1

189 POPSCE – 0 − − Geometry independent part 2190 PLPSCE – 0 − − Length dependence 2191 PWPSCE – 0 − − Width dependence 2192 PLWPSCE – 0 − − Length times width dependence 2

193 PSCEB V−1 0 0 1 Back-bias dependence of PSCE 0

194 PSCEBO V−1 0 − − Geometry independent part 1

195 POPSCEB V−1 0 − − Geometry independent part 2

196 PSCED V−1 0 0 − Drain voltage dependence of PSCE 0

197 PSCEDO V−1 0 − − Geometry independent part 1

198 POPSCED V−1 0 − − Geometry independent part 2

Mobility Parameters

199 BETN m2/V/s 7 · 10−2 0 − Product of channel aspect ratio andzero-field mobility at TR

0

200 UO m2/V/s 5 · 10−2 − − Zero-field mobility at TR 1201 FBET1 – 0 − − Relative mobility decrease due to

first lateral profile1

202 FBET1W – 0 − − Width dependence of FBET1 1203 LP1 m 10−8 10−10 − Mobility-related characteristic

length of first lateral profile1






204 LP1W – 0 − − Width dependence of LP1 1205 FBET2 – 0 − − Relative mobility decrease due to

second lateral profile1

206 LP2 m 10−8 10−10 − Mobility-related characteristiclength of second lateral profile

1

207 BETW1 – 0 − − First higher-order width scalingcoefficient of BETN

1

208 BETW2 – 0 − − Second higher-order width scalingcoefficient of BETN

1

209 WBET m 10−9 10−10 − Characteristic width for widthscaling of BETN

1

210 POBETN m2/V/s 7 · 10−2 − − Geometry independent part 2211 PLBETN m2/V/s 0 − − Length dependence 2212 PWBETN m2/V/s 0 − − Width dependence 2213 PLWBETN m2/V/s 0 − − Length times width dependence 2

214 STBET – 1 − − Temperature dependence of BETN 0

215 STBETO – 1 − − Geometry independent part 1216 STBETL – 0 − − Length dependence 1217 STBETW – 0 − − Width dependence 1218 STBETLW – 0 − − Area dependence 1

219 POSTBET – 1 − − Geometry independent part 2220 PLSTBET – 0 − − Length dependence 2221 PWSTBET – 0 − − Width dependence 2222 PLWSTBET – 0 − − Length times width dependence 2

223 MUE m/V 0.5 0 − Mobility reduction coefficient atTR

0

224 MUEO m/V 0.5 − − Geometry independent part 1225 MUEW – 0 − − Width dependence 1

226 POMUE m/V 0.5 − − Geometry independent part 2227 PLMUE m/V 0 − − Length dependence 2228 PWMUE m/V 0 − − Width dependence 2229 PLWMUE m/V 0 − − Length times width dependence 2

230 STMUE – 0 − − Temperature dependence of MUE 0

231 STMUEO – 0 − − Geometry independent part 1

232 POSTMUE – 0 − − Geometry independent part 2

233 THEMU – 1.5 0 − Mobility reduction exponent at TR 0

234 THEMUO – 1.5 0 − Geometry independent part 1

235 POTHEMU – 1.5 − − Geometry independent part 2






236 STTHEMU – 1.5 − − Temperature dependence ofTHEMU

0

237 STTHEMUO – 1.5 − − Geometry independent part 1

238 POSTTHEMU – 1.5 − − Geometry independent part 2

239 CS – 0 0 − Coulomb scattering parameter atTR

0

240 CSO – 0 − − Geometry independent part 1241 CSL – 0 − − Length dependence 1242 CSLEXP – 1 − − Exponent for length dependence 1243 CSW – 0 − − Width dependence 1244 CSLW – 0 − − Area dependence 1

245 POCS – 0 − − Geometry independent part 2246 PLCS – 0 − − Length dependence 2247 PWCS – 0 − − Width dependence 2248 PLWCS – 0 − − Length times width dependence 2

249 STCS – 0 − − Temperature dependence of CS 0

250 STCSO – 0 − − Geometry independent part 1

251 POSTCS – 0 − − Geometry independent part 2

252 THECS – 2 0 − Coulomb scattering exponent atTR

0

253 THECSO – 2 0 − Geometry-independent part 1

254 POTHECS – 2 0 − Geometry independent part 2

255 STTHECS – 0 − − Temperature dependence ofTHECS

0

256 STTHECSO – 0 − − Geometry-independent part 1

257 POSTTHECS – 0 − − Geometry independent part 2

258 XCOR V−1 0 0 − Non-universality parameter 0

259 XCORO V−1 0 − − Geometry independent part 1260 XCORL – 0 − − Length dependence 1261 XCORW – 0 − − Width dependence 1262 XCORLW – 0 − − Area dependence 1

263 POXCOR V−1 0 − − Geometry independent part 2264 PLXCOR V−1 0 − − Length dependence 2265 PWXCOR V−1 0 − − Width dependence 2266 PLWXCOR V−1 0 − − Length times width dependence 2

267 STXCOR – 0 − − Temperature dependence of XCOR 0

268 STXCORO – 0 − − Geometry independent part 1






269 POSTXCOR – 0 − − Geometry independent part 2

270 FETA – 1 0 − Effective field parameter 0

271 FETAO – 1 − − Geometry independent part 1

272 POFETA – 1 − − Geometry independent part 2

Series Resistance Parameters

273 RS Ω 30 0 − Source/drain series resistance atTR

0

274 RSW1 Ω 50 − − Source/drain series resistance for achannel width WEN

1

275 RSW2 – 0 − − Higher-order width scaling 1

276 PORS Ω 30 − − Geometry independent part 2277 PLRS Ω 0 − − Length dependence 2278 PWRS Ω 0 − − Width dependence 2279 PLWRS Ω 0 − − Length times width dependence 2

280 STRS – 1 − − Temperature dependence of RS 0

281 STRSO – 1 − − Geometry dependent part 1

282 POSTRS – 1 − − Geometry independent part 2

283 RSB V−1 0 −0.5 1 Back-bias dependence of RS 0

284 RSBO V−1 0 − − Geometry independent part 1

285 PORSB V−1 0 − − Geometry independent part 2

286 RSG V−1 0 −0.5 − Gate-bias dependence of RS 0

287 RSGO V−1 0 − − Geometry independent part 1

288 PORSG V−1 0 − − Geometry independent part 2

Velocity Saturation Parameters

289 THESAT V−1 1 0 − Velocity saturation parameter atTR

0

290 THESATO V−1 0 − − Geometry independent part 1291 THESATL V−1 0.05 − − Length dependence 1292 THESATLEXP – 1 − − Exponent for length dependence 1293 THESATW – 0 − − Width dependence 1294 THESATLW – 0 − − Area dependence 1

295 POTHESAT V−1 1 − − Geometry independent part 2296 PLTHESAT V−1 0 − − Length dependence 2297 PWTHESAT V−1 0 − − Width dependence 2298 PLWTHESAT V−1 0 − − Length times width dependence 2






299 STTHESAT – 1 − − Temperature dependence ofTHESAT

0

300 STTHESATO – 1 − − Geometry independent temperaturedependence

1

301 STTHESATL – 0 − − Length dependence 1302 STTHESATW – 0 − − Width dependence 1303 STTHESATLW – 0 − − Area dependence 1

304 POSTTHESAT – 1 − − Geometry independent part 2305 PLSTTHESAT – 0 − − Length dependence 2306 PWSTTHESAT – 0 − − Width dependence 2307 PLWSTTHESAT – 0 − − Length times width dependence of

temperature dependence2

308 THESATB V−1 0 −0.5 1 Back-bias dependence of velocitysaturation

0

309 THESATBO V−1 0 − − Geometry independent part 1

310 POTHESATB V−1 0 − − Geometry independent part 2311 PLTHESATB V−1 0 − − Length dependence 2312 PWTHESATB V−1 0 − − Width dependence 2313 PLWTHESATB V−1 0 − − Length times width dependence 2

314 THESATG V−1 0 −0.5 − Gate-bias dependence of velocitysaturation

0

315 THESATGO V−1 0 − − Geometry independent part 1

316 POTHESATG V−1 0 − − Geometry independent part 2317 PLTHESATG V−1 0 − − Length dependence 2318 PWTHESATG V−1 0 − − Width dependence 2319 PLWTHESATG V−1 0 − − Length times width dependence 2

Saturation Voltage Parameter

320 AX - 3 2 − Linear/saturation transition factor 0

321 AXO – 18 − − Geometry independent 1322 AXL – 0.4 0 − Length dependence 1

323 POAX – 3 − − Geometry independent part 2324 PLAX – 0 − − Length dependence 2325 PWAX – 0 − − Width dependence 2326 PLWAX – 0 − − Length times width dependence 2

Channel Length Modulation (CLM) Parameters

327 ALP – 0.01 0 − CLM pre-factor 0328 ALPL – 5 · 10−4 − − Length dependence 1329 ALPLEXP – 1 − − Exponent for length dependence 1330 ALPW – 0 − − Width dependence 1






331 POALP – 0.01 − − Geometry independent part 2332 PLALP – 0 − − Length dependence 2333 PWALP – 0 − − Width dependence 2334 PLWALP – 0 − − Length times width dependence 2

335 ALP1 V 0 0 − CLM enhancement factor abovethreshold

0

336 ALP1L1 V 0 − − Length dependence 1337 ALP1LEXP – 0.5 − − Exponent for length dependence 1338 ALP1L2 – 0 0 − Second order length dependence 1339 ALP1W – 0 − − Width dependence 1

340 POALP1 V 0 − − Geometry independent part 2341 PLALP1 V 0 − − Length dependence 2342 PWALP1 V 0 − − Width dependence 2343 PLWALP1 V 0 − − Length times width dependence 2

344 ALP2 V−1 0 0 − CLM enhancement factor belowthreshold

0

345 ALP2L1 V 0 − − Length dependence 1346 ALP2LEXP – 0.5 − − Exponent for length dependence 1347 ALP2L2 – 0 0 − Second order length dependence 1348 ALP2W – 0 − − Width dependence 1

349 POALP2 V−1 0 − − Geometry independent part 2350 PLALP2 V−1 0 − − Length dependence 2351 PWALP2 V−1 0 − − Width dependence 2352 PLWALP2 V−1 0 − − Length times width dependence 2

353 VP V 0.05 10−10 − CLM logarithmic dependenceparameter

0

354 VPO V 0.05 − − Geometry independent part 1

355 POVP V 0.05 − − Geometry independent part 2

Impact Ionization (II) Parameters

356 A1 – 1 0 − Impact-ionization pre-factor 0

357 A1O – 1 − − Geometry independent part 1358 A1L – 0 − − Length dependence 1359 A1W – 0 − − Width dependence 1

360 POA1 – 1 − − Geometry independent part 2361 PLA1 – 0 − − Length dependence 2362 PWA1 – 0 − − Width dependence 2363 PLWA1 – 0 − − Length times width dependence 2

364 A2 V 10 0 − Impact-ionization exponent at TR 0






365 A2O V 10 − − Geometry independent part 1

366 POA2 V 10 − − Geometry independent part 2

367 STA2 V 0 − − Temperature dependence of A2 0

368 STA2O V 0 − − Geometry independent part 1

369 POSTA2 V 0 − − Geometry independent part 2

370 A3 – 1 0 − Saturation-voltage dependence ofII

0

371 A3O – 1 − − Geometry independent part 1372 A3L – 0 − − Length dependence 1373 A3W – 0 − − Width dependence 1

374 POA3 – 1 − − Geometry independent part 2375 PLA3 – 0 − − Length dependence 2376 PWA3 – 0 − − Width dependence 2377 PLWA3 – 0 − − Length times width dependence 2

378 A4 V−12 0 0 − Back-bias dependence of II 0

379 A4O V−12 0 − − Geometry independent part 1

380 A4L – 0 − − Length dependence 1381 A4W – 0 − − Width dependence 1

382 POA4 V−12 0 − − Geometry independent part 2

383 PLA4 V−12 0 − − Length dependence 2

384 PWA4 V−12 0 − − Width dependence 2

385 PLWA4 V−12 0 − − Length times width dependence 2

Gate Current Parameters

386 GCO – 0 −10 10 Gate tunnelling energy adjustment 0

387 GCOO – 0 − − Geometry independent part 1

388 POGCO – 0 − − Geometry independent part 2

389 IGINV A 0 0 − Gate channel current pre-factor 0

390 IGINVLW A 0 − − Gate channel current pre-factor fora channel area of WEN · LEN

1

391 POIGINV A 0 − − Geometry independent part 2392 PLIGINV A 0 − − Length dependence 2393 PWIGINV A 0 − − Width dependence 2394 PLWIGINV A 0 − − Length times width dependence 2

395 IGOV A 0 0 − Gate overlap current pre-factor 0

396 IGOVW A 0 − − Gate overlap current pre-factor fora channel width of WEN

1






397 POIGOV A 0 − − Geometry independent part 2398 PLIGOV A 0 − − Length dependence 2399 PWIGOV A 0 − − Width dependence 2400 PLWIGOV A 0 − − Length times width dependence 2

401 IGOVD A 0 0 − Gate overlap current pre-factor fordrain side

0

402 IGOVDW A 0 − − Gate overlap current pre-factor fora channel width of WEN for drainside

1

403 POIGOVD A 0 − − Geometry independent part 2404 PLIGOVD A 0 − − Length dependence 2405 PWIGOVD A 0 − − Width dependence 2406 PLWIGOVD A 0 − − Length times width dependence 2

407 STIG – 2 − − Temperature dependence of gatecurrent

0

408 STIGO – 2 − − Geometry independent part 1

409 POSTIG – 2 − − Geometry independent part 2

410 GC2 – 0.375 0 10 Gate current slope factor 0

411 GC2O – 0.375 − − Geometry independent part 1

412 POGC2 – 3.75 · 10−1 − − Geometry independent part 2

413 GC3 – 0.063 −2 2 Gate current curvature factor 0

414 GC3O – 0.063 − − Geometry independent part 1

415 POGC3 – 6.3 · 10−2 − − Geometry independent part 2

416 CHIB V 3.1 1 − Tunnelling barrier height 0

417 CHIBO V 3.1 − − Geometry independent part 1

418 POCHIB V 3.1 − − Geometry independent part 2

Gate-Induced Drain Leakage (GIDL) Parameters

419 AGIDL A/V3 0 0 − GIDL pre-factor 0

420 AGIDLW A/V3 0 − − Width dependence 1

421 POAGIDL A/V3 0 − − Geometry independent part 2422 PLAGIDL A/V3 0 − − Length dependence 2423 PWAGIDL A/V3 0 − − Width dependence 2424 PLWAGIDL A/V3 0 − − Length times width dependence 2

425 AGIDLD A/V3 0 0 − GIDL pre-factor for drain side 0

426 AGIDLDW A/V3 0 − − Width dependence 1






427 POAGIDLD A/V3 0 − − Geometry independent part 2428 PLAGIDLD A/V3 0 − − Length dependenceof 2429 PWAGIDLD A/V3 0 − − Width dependenceof 2430 PLWAGIDLD A/V3 0 − − Length times width dependence 2

431 BGIDL V 41 0 − GIDL probability factor at TR 0

432 BGIDLO V 41 − − Geometry independent part 1

433 POBGIDL V 41 − − Geometry independent part 2

434 BGIDLD V 41 0 − GIDL probability factor at TR fordrain side

0

435 BGIDLDO V 41 − − Geometry independent part 1

436 POBGIDLD V 41 − − Geometry independent part 2

437 STBGIDL V/K 0 − − Temperature dependence ofBGIDL

0

438 STBGIDLO V/K 0 − − Geometry independent part 1

439 POSTBGIDL V/K 0 − − Geometry independent part 2

440 STBGIDLD V/K 0 − − Temperature dependence ofBGIDL for drain side

0

441 STBGIDLDO V/K 0 − − Geometry independent part 1

442 POSTBGIDLD V/K 0 − − Geometry independent part 2

443 CGIDL – 0 − − Back-bias dependence of GIDL 0

444 CGIDLO – 0 − − Geometry independent part 1

445 POCGIDL – 0 − − Geometry independent part 2

446 CGIDLD – 0 − − Back-bias dependence of GIDL fordrain side

0

447 CGIDLDO – 0 − − Geometry independent part 1

448 POCGIDLD – 0 − − Geometry independent part 2

Charge Model Parameters

449 COX F 10−14 0 − Oxide capacitance for intrinsicchannel

0

450 POCOX F 10−14 − − Geometry independent part 2451 PLCOX F 0 − − Length dependence 2452 PWCOX F 0 − − Width dependence 2453 PLWCOX F 0 − − Length times width dependence 2

454 CGOV F 10−15 0 − Oxide capacitance forgate–drain/source overlap

0






455 POCGOV F 10−15 − − Geometry independent part 2456 PLCGOV F 0 − − Length dependence 2457 PWCGOV F 0 − − Width dependence 2458 PLWCGOV F 0 − − Length times width dependence 2

459 CGOVD F 10−15 0 − Oxide capacitance forgate–drain/source overlap for drainside

0

460 POCGOVD F 10−15 − − Geometry independent part 2461 PLCGOVD F 0 − − Length dependence 2462 PWCGOVD F 0 − − Width dependence 2463 PLWCGOVD F 0 − − Length times width dependence 2

464 CGBOV F 0 0 − Oxide capacitance for gate–bulkoverlap

0

465 CGBOVL F 0 − − Oxide capacitance for gate–bulkoverlap for a channel length ofLEN

1

466 POCGBOV F 0 − − Geometry independent part 2467 PLCGBOV F 0 − − Length dependence 2468 PWCGBOV F 0 − − Width dependence 2469 PLWCGBOV F 0 − − Length times width dependence 2

470 CFR F 0 0 − Outer fringe capacitance 0

471 CFRW F 0 − − Outer fringe capacitance for achannel width of WEN

1

472 POCFR F 0 − − Geometry independent part 2473 PLCFR F 0 − − Length dependence 2474 PWCFR F 0 − − Width dependence 2475 PLWCFR F 0 − − Length times width dependence 2

476 CFRD F 0 0 − Outer fringe capacitance for drainside

0

477 CFRDW F 0 − − Outer fringe capacitance for achannel width of WEN for drainside

1

478 POCFRD F 0 − − Geometry independent part 2479 PLCFRD F 0 − − Length dependence 2480 PWCFRD F 0 − − Width dependence 2481 PLWCFRD F 0 − − Length times width dependence 2

Noise Model Parameters

482 FNT – 1 0 − Thermal noise coefficient 0

483 FNTO – 1 − − Geometry independent part 1






484 POFNT – 1 − − Geometry independent part 2

485 FNTEXC – 0 0 − Excess noise coefficient 0

486 FNTEXCL – 0 0 − Length-dependence of excess noise 1

487 POFNTEXC – 0 − − Geometry independent part 2488 PLFNTEXC – 0 − − Length dependence 2489 PWFNTEXC – 0 − − Width dependence 2490 PLWFNTEXC – 0 − − Length times width dependence 2

491 NFA V−1/m4 8 · 1022 0 − First coefficient of flicker noise 0

492 NFALW V−1/m4 8 · 1022 − − First coefficient of flicker noise fora channel area of WEN · LEN

1

493 PONFA V−1/m4 8 · 1022 − − Geometry independent part 2494 PLNFA V−1/m4 0 − − Length dependence 2495 PWNFA V−1/m4 0 − − Width dependence 2496 PLWNFA V−1/m4 0 − − Length times width dependence 2

497 NFB V−1/m2 3 · 107 0 − Second coefficient of flicker noise 0

498 NFBLW V−1/m2 3 · 107 − − Second coefficient of flicker noisefor a channel area of WEN · LEN

1

499 PONFB V−1/m2 3 · 107 − − Geometry independent part 2500 PLNFB V−1/m2 0 − − Length dependence 2501 PWNFB V−1/m2 0 − − Width dependence 2502 PLWNFB V−1/m2 0 − − Length times width dependence 2

503 NFC V−1 0 0 − Third coefficient of flicker noise 0

504 NFCLW V−1 0 − − Third coefficient of flicker noisefor a channel area of WEN · LEN

1

505 PONFC V−1 0 − − Geometry independent part 2506 PLNFC V−1 0 − − Length dependence 2507 PWNFC V−1 0 − − Width dependence 2508 PLWNFC V−1 0 − − Length times width dependence 2

509 EF – 1 0 − Flicker noise frequency exponent 0

510 EFO – 1 − − Geometry independent part 1

511 POEF – 1 − − Geometry independent part 2

512 LINTNOI m 0 − − Length offset for flicker noise 1

513 ALPNOI – 2 − − Exponent for length offset 1

Edge Transistor Model Parameters

514 WEDGE m 10−8 0 − Electrical width of edge transistorper side

1






515 WEDGEW m 0 0 − Main transistor width dependenceof WEDGE

1

516 VFBEDGE V −1 − − Flat band voltage of edge transistorat TR

0

517 VFBEDGEO V −1 − − Geometry independent part 1

518 POVFBEDGE V −1 − − Geometry independent part 2

519 STVFBEDGE V/K 5 · 10−4 − − Temperature dependence ofVFBEDGE

0

520 STVFBEDGEO V/K 5 · 10−4 − − Geometry independent part 1521 STVFBEDGEL V/K 0 − − Length dependence 1522 STVFBEDGEW V/K 0 − − Width dependence 1523 STVFBEDGELW V/K 0 − − Area dependence 1

524 POSTVFBEDGE V/K 5 · 10−4 − − Geometry independent part 2525 PLSTVFBEDGE V/K 0 − − Length dependence 2526 PWSTVFBEDGE V/K 0 − − Width dependence 2527 PLWSTVFBEDGE V/K 0 − − Length times width dependence 2

528 DPHIBEDGE V 0 − − Offset of ϕB for edge transistor 0

529 DPHIBEDGEO V 0 − − Geometry independent part 1530 DPHIBEDGEL V 0 − − Length dependence 1531 DPHIBEDGELEXP – 1 − − Exponent for length dependence 1532 DPHIBEDGEW – 0 − − Width dependence 1533 DPHIBEDGELW – 0 − − Area dependence 1

534 PODPHIBEDGE V 0 − − Geometry independent part 2535 PLDPHIBEDGE V 0 − − Length dependence 2536 PWDPHIBEDGE V 0 − − Width dependence 2537 PLWDPHIBEDGE V 0 − − Length times width dependence 2

538 NEFFEDGE m−3 5 · 1023 1020 1026 Effective substrate doping of edgetransistor

0

539 NSUBEDGEO m−3 5 · 1023 1020 − Geometry independent substratedoping

1

540 NSUBEDGEL – 0 − − Length dependence 1541 NSUBEDGELEXP – 1 − − Exponent for length dependence 1542 NSUBEDGEW – 0 − − Width dependence of edge

transistor substrate doping1

543 NSUBEDGELW – 0 − − Area dependence 1

544 PONEFFEDGE m−3 5 · 1023 − − Geometry independent part 2545 PLNEFFEDGE m−3 0 − − Length dependence 2546 PWNEFFEDGE m−3 0 − − Width dependence 2547 PLWNEFFEDGE m−3 0 − − Length times width dependence 2






548 CTEDGE – 0 0 − Interface states factor of edgetransistor

0

549 CTEDGEO – 0 − − Geometry-independent part 1550 CTEDGEL – 0 − − Length dependence 1551 CTEDGELEXP – 1 − − Exponent for length dependence 1

552 POCTEDGE – 0 − − Geometry independent part 2553 PLCTEDGE – 0 − − Length dependence 2554 PWCTEDGE – 0 − − Width dependence 2555 PLWCTEDGE – 0 − − Length times width dependence 2

556 BETNEDGE m2/V/s 5 · 10−4 0 − Product of channel aspect ratio andzero-field mobility of edgetransistor at TR

0

557 FBETEDGE – 0 − − Length dependence 1558 LPEDGE m 10−8 10−10 − Exponent for length dependence 1559 BETEDGEW – 0 − − Width scaling coefficient 1

560 POBETNEDGE m2/V/s 5 · 10−4 − − Geometry independent part 2561 PLBETNEDGE m2/V/s 0 − − Length dependence 2562 PWBETNEDGE m2/V/s 0 − − Width dependence 2563 PLWBETNEDGE m2/V/s 0 − − Length times width dependence 2

564 STBETEDGE – 1 − − Temperature dependence ofBETNEDGE

0

565 STBETEDGEO – 1 − − Geometry independent part 1566 STBETEDGEL – 0 − − Length dependence 1567 STBETEDGEW – 0 − − Width dependence 1568 STBETEDGELW – 0 − − Area dependence 1

569 POSTBETEDGE – 1 − − Geometry independent part 2570 PLSTBETEDGE – 0 − − Length dependence 2571 PWSTBETEDGE – 0 − − Width dependence 2572 PLWSTBETEDGE – 0 − − Length times width dependence 2

573 PSCEEDGE – 0 0 − Subthreshold slope coefficient forshort channel edge transistor

0

574 PSCEEDGEL – 0 − − Length dependence 1575 PSCEEDGELEXP – 2 − − Exponent for length dependence 1576 PSCEEDGEW – 0 − − Width dependence 1

577 POPSCEEDGE – 0 − − Geometry independent part 2578 PLPSCEEDGE – 0 − − Length dependence 2579 PWPSCEEDGE – 0 − − Width dependence 2580 PLWPSCEEDGE – 0 − − Length times width dependence 2

581 PSCEBEDGE V−1 0 0 1 Back-bias dependence ofPSCEEDGE

0






582 PSCEBEDGEO V−1 0 − − Geometry independent part 1

583 POPSCEBEDGE V−1 0 − − Geometry independent part 2

584 PSCEDEDGE V−1 0 0 − Drain voltage dependence ofPSCEEDGE

0

585 PSCEDEDGEO V−1 0 − − Geometry independent part 1

586 POPSCEDEDGE V−1 0 − − Geometry independent part 2

587 CFEDGE – 0 0 − DIBL parameter of edge transistor 0

588 CFEDGEL – 0 − − Length dependence 1589 CFEDGELEXP – 2 − − Exponent for length dependence 1590 CFEDGEW – 0 − − Width dependence 1

591 POCFEDGE – 0 − − Geometry independent part 2592 PLCFEDGE – 0 − − Length dependence 2593 PWCFEDGE – 0 − − Width dependence 2594 PLWCFEDGE – 0 − − Length times width dependence 2

595 CFBEDGE V−1 0 0 1 Back-bias dependence ofCFEDGE

0

596 CFBEDGEO V−1 0 − − Geometry independent part 1

597 POCFBEDGE V−1 0 − − Geometry independent part 2

598 CFDEDGE V−1 0 0 − Drain voltage dependence ofCFEDGE

0

599 CFDEDGEO V−1 0 − − Geometry independent part 1

600 POCFDEDGE V−1 0 − − Geometry independent part 2

601 FNTEDGE – 1 0 − Thermal noise coefficient of edgetransistor

0

602 FNTEDGEO – 1 − − Geometry independent part 1

603 POFNTEDGE – 1 − − Geometry independent part 2

604 NFAEDGE V−1/m4 8 · 1022 0 − First coefficient of flicker noise ofedge transistor

0

605 NFAEDGELW V−1/m4 8 · 1022 − − Area dependence 1

606 PONFAEDGE V−1/m4 8 · 1022 − − Geometry independent part 2607 PLNFAEDGE V−1/m4 0 − − Length dependence 2608 PWNFAEDGE V−1/m4 0 − − Width dependence 2609 PLWNFAEDGE V−1/m4 0 − − Length times width dependence 2

610 NFBEDGE V−1/m2 3 · 107 0 − Second coefficient of flicker noiseof edge transistor

0

611 NFBEDGELW V−1/m2 3 · 107 − − Area dependence 1






612 PONFBEDGE V−1/m2 3 · 107 − − Geometry independent part 2613 PLNFBEDGE V−1/m2 0 − − Length dependence 2614 PWNFBEDGE V−1/m2 0 − − Width dependence 2615 PLWNFBEDGE V−1/m2 0 − − Length times width dependence 2

616 NFCEDGE V−1 0 0 − Third coefficient of flicker noise ofedge transistor

0

617 NFCEDGELW V−1 0 − − Area dependence 1

618 PONFCEDGE V−1 0 − − Geometry independent part 2619 PLNFCEDGE V−1 0 − − Length dependence 2620 PWNFCEDGE V−1 0 − − Width dependence 2621 PLWNFCEDGE V−1 0 − − Length times width dependence 2

622 EFEDGE – 1 0 − Flicker noise frequency exponentof edge transistor

0

623 EFEDGEO – 1 − − Geometry independent part 1

624 POEFEDGE – 1 − − Geometry independent part 2



2.5.3 Parameters for stress model

The stress model of BSIM4.4.0 has been adopted in PSP with as little modifications as possible. Parameternames have been copied, but they have been subjected to PSP conventions by replacing every zero by an ‘O’.Moreover, the parameters STK2 and LODK2 are not available in PSP. Except for these changes, stress param-eters determined for BSIM can be directly applied in PSP. Some trivial conversion of parameters BSIM→PSPis still necessary, see [2].

The parameters in this section are part of PSP’s global parameter set (both geometrical and binning).


0 SAREF m 10−6 10−9 − Reference distance between ODedge to Poly from one side

1, 2

1 SBREF m 10−6 10−9 − Reference distance between ODedge to Poly from other side

1, 2

2 WLOD m 0 − − Width parameter 1, 23 KUO m 0 − − Mobility degradation/enhancement

coefficient1, 2

4 KVSAT m 0 −1 1 Saturation velocitydegradation/enhancementparameter

1, 2

5 TKUO – 0 − − Temperature coefficient of KUO 1, 26 LKUO mLLODKUO 0 − − Length dependence of KUO 1, 27 WKUO mWLODKUO 0 − − Width dependence of KUO 1, 28 PKUO mLLODKUO+WLODKUO 0 − − Cross-term dependence of KUO 1, 29 LLODKUO – 0 0 − Length parameter for mobility

stress effect1, 2

10 WLODKUO – 0 0 − Width parameter for mobility stresseffect

1, 2

11 KVTHO Vm 0 − − Threshold shift parameter 1, 212 LKVTHO mLLODVTH 0 − − Length dependence of KVTHO 1, 213 WKVTHO mWLODVTH 0 − − Width dependence of KVTHO 1, 214 PKVTHO mLLODVTH+WLODVTH 0 − − Cross-term dependence of

KVTHO1, 2

15 LLODVTH – 0 0 − Length parameter for thresholdvoltage stress effect

1, 2

16 WLODVTH – 0 0 − Width parameter for thresholdvoltage stress effect

1, 2

17 STETAO m 0 − − ETAO shift factor related tothreshold voltage change

1, 2

18 LODETAO – 1 0 − ETAO shift modification factor 1, 2



2.5.4 Parameters for well proximity effect model

The WPE model of BSIM4.5.0 has been adopted in PSP with as little modifications as possible. Parameternames have been copied, but they have been subjected to PSP conventions by replacing every zero by an ‘O’.Moreover, the parameter K2WE is not available in PSP. Except for some trivial conversion of parametersBSIM→PSP [2], WPE parameters from BSIM can be used directly in PSP. The WPE parameters have bothgeometrical and binning rules included as explained in Section 3.6.2. The last column—labeled ‘Geo.’—showsfor which value of SWGEO the parameter is used.


0 SCREF m 1 · 10−6 0 − Distance between OD-edge andwell edge of a reference device

1, 2

1 WEB – 0 − − Coefficient for SCB 1, 22 WEC – 0 − − Coefficient for SCC 1, 2

3 KVTHOWEO – 0 − − Geometry independent thresholdshift parameter

1

4 KVTHOWEL – 0 − − Length dependence 15 KVTHOWEW – 0 − − Width dependence 16 KVTHOWELW – 0 − − Area dependence 1

7 POKVTHOWE – 0 − − Geometry independent part ofthreshold shift parameter

2

8 PLKVTHOWE – 0 − − Length dependence 29 PWKVTHOWE – 0 − − Width dependence 210 PLWKVTHOWE – 0 − − Length times width dependence 2

11 KUOWEO – 0 − − Geometry independent mobilitydegradation factor

1

12 KUOWEL – 0 − − Length dependence 113 KUOWEW – 0 − − Width dependence 114 KUOWELW – 0 − − Area dependence 1

15 POKUOWE – 0 − − Geometry independent part ofmobility degradation factor

2

16 PLKUOWE – 0 − − Length dependence 217 PWKUOWE – 0 − − Width dependence 218 PLWKUOWE – 0 − − Length times width dependence 2



2.5.5 Parameters for source-bulk and drain-bulk junction model

The JUNCAP2 parameters are part of both the global and the local parameter sets. The last column of Asym.shows for which value of SWJUNASYM the listed parameter is enabled: i.e., when SWJUNASYM = 0,parameters No. 3-45 are used for both source-bulk and drain-bulk junctions and parameters No. 46-88 areignored; when SWJUNASYM = 1, parameters No. 3-45 are used for source-bulk junction and No. 46-88 areused for drain-bulk junction; parameters No. 0-2 are used in both situations.

No. Name Unit Default Min. Max. Description Asym.

0 TRJ C 21 Tmin − Reference temperature 0, 11 SWJUNEXP – 0 0 1 Flag for JUNCAP2 Express; 0↔

full JUNCAP2 model, 1↔Express model

0, 1

2 IMAX A 103 10−12 − Maximum current up to whichforward current behavesexponentially

0, 1

3 FREV – 103 103 1010 Coefficient for reverse breakdowncurrent limitation

0, 1

Capacitance Parameters

4 CJORBOT F/m2 10−3 10−12 − Zero-bias capacitance perunit-of-area of bottom componentfor source-bulk junction

0, 1

5 CJORSTI F/m 10−9 10−18 − Zero-bias capacitance perunit-of-length of STI-edgecomponent for source-bulkjunction

0, 1

6 CJORGAT F/m 10−9 10−18 − Zero-bias capacitance perunit-of-length of gate-edgecomponent for source-bulkjunction

0, 1

7 VBIRBOT V 1 Vbi,low − Built-in voltage at the referencetemperature of bottom componentfor source-bulk junction

0, 1

8 VBIRSTI V 1 Vbi,low − Built-in voltage at the referencetemperature of STI-edgecomponent for source-bulkjunction

0, 1

9 VBIRGAT V 1 Vbi,low − Built-in voltage at the referencetemperature of gate-edgecomponent for source-bulkjunction

0, 1

10 PBOT – 0.5 0.05 0.95 Grading coefficient of bottomcomponent for source-bulkjunction

0, 1

11 PSTI – 0.5 0.05 0.95 Grading coefficient of STI-edgecomponent for source-bulkjunction

0, 1

12 PGAT – 0.5 0.05 0.95 Grading coefficient of gate-edgecomponent for source-bulkjunction

0, 1






Ideal-current Parameters

13 PHIGBOT V 1.16 − − Zero-temperature bandgap voltageof bottom component forsource-bulk junction

0, 1

14 PHIGSTI V 1.16 − − Zero-temperature bandgap voltageof STI-edge component forsource-bulk junction

0, 1

15 PHIGGAT V 1.16 − − Zero-temperature bandgap voltageof gate-edge component forsource-bulk junction

0, 1

16 IDSATRBOT A/m2 10−12 0 − Saturation current density at thereference temperature of bottomcomponent for source-bulkjunction

0, 1

17 IDSATRSTI A/m 10−18 0 − Saturation current density at thereference temperature of STI-edgecomponent for source-bulkjunction

0, 1

18 IDSATRGAT A/m 10−18 0 − Saturation current density at thereference temperature of gate-edgecomponent for source-bulkjunction

0, 1

Shockley-Read-Hall Parameters

19 CSRHBOT A/m3 102 0 − Shockley-Read-Hall prefactor ofbottom component for source-bulkjunction

0, 1

20 CSRHSTI A/m2 10−4 0 − Shockley-Read-Hall prefactor ofSTI-edge component forsource-bulk junction

0, 1

21 CSRHGAT A/m2 10−4 0 − Shockley-Read-Hall prefactor ofgate-edge component forsource-bulk junction

0, 1

22 XJUNSTI m 10−7 10−9 − Junction depth of STI-edgecomponent for source-bulkjunction

0, 1

23 XJUNGAT m 10−7 10−9 − Junction depth of gate-edgecomponent for source-bulkjunction

0, 1

Trap-assisted Tunneling Parameters

24 CTATBOT A/m3 102 0 − Trap-assisted tunneling prefactor ofbottom component for source-bulkjunction

0, 1

25 CTATSTI A/m2 10−4 0 − Trap-assisted tunneling prefactor ofSTI-edge component forsource-bulk junction

0, 1






26 CTATGAT A/m2 10−4 0 − Trap-assisted tunneling prefactor ofgate-edge component forsource-bulk junction

0, 1

27 MEFFTATBOT – 0.25 .01 − Effective mass (in units of m0) fortrap-assisted tunneling of bottomcomponent for source-bulkjunction

0, 1

28 MEFFTATSTI – 0.25 .01 − Effective mass (in units of m0) fortrap-assisted tunneling of STI-edgecomponent for source-bulkjunction

0, 1

29 MEFFTATGAT – 0.25 .01 − Effective mass (in units of m0) fortrap-assisted tunneling of gate-edgecomponent for source-bulkjunction

0, 1

Band-to-band Tunneling Parameters

30 CBBTBOT AV−3 10−12 0 − Band-to-band tunneling prefactorof bottom component forsource-bulk junction

0, 1

31 CBBTSTI AV−3m 10−18 0 − Band-to-band tunneling prefactorof STI-edge component forsource-bulk junction

0, 1

32 CBBTGAT AV−3m 10−18 0 − Band-to-band tunneling prefactorof gate-edge component forsource-bulk junction

0, 1

33 FBBTRBOT Vm−1 109 − − Normalization field at the referencetemperature for band-to-bandtunneling of bottom component forsource-bulk junction

0, 1

34 FBBTRSTI Vm−1 109 − − Normalization field at the referencetemperature for band-to-bandtunneling of STI-edge componentfor source-bulk junction

0, 1

35 FBBTRGAT Vm−1 109 − − Normalization field at the referencetemperature for band-to-bandtunneling of gate-edge componentfor source-bulk junction

0, 1

36 STFBBTBOT K−1 − 10−3 − − Temperature scaling parameter forband-to-band tunneling of bottomcomponent for source-bulkjunction

0, 1

37 STFBBTSTI K−1 − 10−3 − − Temperature scaling parameter forband-to-band tunneling ofSTI-edge component forsource-bulk junction

0, 1






38 STFBBTGAT K−1 − 10−3 − − Temperature scaling parameter forband-to-band tunneling ofgate-edge component forsource-bulk junction

0, 1

Avalanche and Breakdown Parameters

39 VBRBOT V 10 0.1 − Breakdown voltage of bottomcomponent for source-bulkjunction

0, 1

40 VBRSTI V 10 0.1 − Breakdown voltage of STI-edgecomponent for source-bulkjunction

0, 1

41 VBRGAT V 10 0.1 − Breakdown voltage of gate-edgecomponent for source-bulkjunction

0, 1

42 PBRBOT V 4 0.1 − Breakdown onset tuning parameterof bottom component forsource-bulk junction

0, 1

43 PBRSTI V 4 0.1 − Breakdown onset tuning parameterof STI-edge component forsource-bulk junction

0, 1

44 PBRGAT V 4 0.1 − Breakdown onset tuning parameterof gate-edge component forsource-bulk junction

0, 1

JUNCAP Express Parameters

45 VJUNREF V 2.5 0.5 − Typical maximum source-bulkjunction voltage; usually about2 · Vsup

0, 1

46 FJUNQ V 0.03 0 − Fraction below which source-bulkjunction capacitance componentsare neglected

0, 1

Capacitance Parameters

47 CJORBOTD F/m2 10−3 10−12 − Zero-bias capacitance perunit-of-area of bottom componentfor drain-bulk junction

1

48 CJORSTID F/m 10−9 10−18 − Zero-bias capacitance perunit-of-length of STI-edgecomponent for drain-bulk junction

1

49 CJORGATD F/m 10−9 10−18 − Zero-bias capacitance perunit-of-length of gate-edgecomponent for drain-bulk junction

1

50 VBIRBOTD V 1 Vbi,low − Built-in voltage at the referencetemperature of bottom componentfor drain-bulk junction

1

51 VBIRSTID V 1 Vbi,low − Built-in voltage at the referencetemperature of STI-edgecomponent for drain-bulk junction

1






52 VBIRGATD V 1 Vbi,low − Built-in voltage at the referencetemperature of gate-edgecomponent for drain-bulk junction

1

53 PBOTD – 0.5 0.05 0.95 Grading coefficient of bottomcomponent for drain-bulk junction

1

54 PSTID – 0.5 0.05 0.95 Grading coefficient of STI-edgecomponent for drain-bulk junction

1

55 PGATD – 0.5 0.05 0.95 Grading coefficient of gate-edgecomponent for drain-bulk junction

1

Ideal-current Parameters

56 PHIGBOTD V 1.16 − − Zero-temperature bandgap voltageof bottom component fordrain-bulk junction

1

57 PHIGSTID V 1.16 − − Zero-temperature bandgap voltageof STI-edge component fordrain-bulk junction

1

58 PHIGGATD V 1.16 − − Zero-temperature bandgap voltageof gate-edge component fordrain-bulk junction

1

59 IDSATRBOTD A/m2 10−12 0 − Saturation current density at thereference temperature of bottomcomponent for drain-bulk junction

1

60 IDSATRSTID A/m 10−18 0 − Saturation current density at thereference temperature of STI-edgecomponent for drain-bulk junction

1

61 IDSATRGATD A/m 10−18 0 − Saturation current density at thereference temperature of gate-edgecomponent for drain-bulk junction

1

Shockley-Read-Hall Parameters

62 CSRHBOTD A/m3 102 0 − Shockley-Read-Hall prefactor ofbottom component for drain-bulkjunction

1

63 CSRHSTID A/m2 10−4 0 − Shockley-Read-Hall prefactor ofSTI-edge component for drain-bulkjunction

1

64 CSRHGATD A/m2 10−4 0 − Shockley-Read-Hall prefactor ofgate-edge component fordrain-bulk junction

1

65 XJUNSTID m 10−7 10−9 − Junction depth of STI-edgecomponent for drain-bulk junction

1

66 XJUNGATD m 10−7 10−9 − Junction depth of gate-edgecomponent for drain-bulk junction

1

Trap-assisted Tunneling Parameters






67 CTATBOTD A/m3 102 0 − Trap-assisted tunneling prefactor ofbottom component for drain-bulkjunction

1

68 CTATSTID A/m2 10−4 0 − Trap-assisted tunneling prefactor ofSTI-edge component for drain-bulkjunction

1

69 CTATGATD A/m2 10−4 0 − Trap-assisted tunneling prefactor ofgate-edge component fordrain-bulk junction

1

70 MEFFTATBOTD – 0.25 .01 − Effective mass (in units of m0) fortrap-assisted tunneling of bottomcomponent for drain-bulk junction

1

71 MEFFTATSTID – 0.25 .01 − Effective mass (in units of m0) fortrap-assisted tunneling of STI-edgecomponent for drain-bulk junction

1

72 MEFFTATGATD – 0.25 .01 − Effective mass (in units of m0) fortrap-assisted tunneling of gate-edgecomponent for drain-bulk junction

1

Band-to-band Tunneling Parameters

73 CBBTBOTD AV−3 10−12 0 − Band-to-band tunneling prefactorof bottom component fordrain-bulk junction

1

74 CBBTSTID AV−3m 10−18 0 − Band-to-band tunneling prefactorof STI-edge component fordrain-bulk junction

1

75 CBBTGATD AV−3m 10−18 0 − Band-to-band tunneling prefactorof gate-edge component fordrain-bulk junction

1

76 FBBTRBOTD Vm−1 109 − − Normalization field at the referencetemperature for band-to-bandtunneling of bottom component fordrain-bulk junction

1

77 FBBTRSTID Vm−1 109 − − Normalization field at the referencetemperature for band-to-bandtunneling of STI-edge componentfor drain-bulk junction

1

78 FBBTRGATD Vm−1 109 − − Normalization field at the referencetemperature for band-to-bandtunneling of gate-edge componentfor drain-bulk junction

1

79 STFBBTBOTD K−1 − 10−3 − − Temperature scaling parameter forband-to-band tunneling of bottomcomponent for drain-bulk junction

1

80 STFBBTSTID K−1 − 10−3 − − Temperature scaling parameter forband-to-band tunneling ofSTI-edge component for drain-bulkjunction

1






81 STFBBTGATD K−1 − 10−3 − − Temperature scaling parameter forband-to-band tunneling ofgate-edge component fordrain-bulk junction

1

Avalanche and Breakdown Parameters

82 VBRBOTD V 10 0.1 − Breakdown voltage of bottomcomponent for drain-bulk junction

1

83 VBRSTID V 10 0.1 − Breakdown voltage of STI-edgecomponent for drain-bulk junction

1

84 VBRGATD V 10 0.1 − Breakdown voltage of gate-edgecomponent for drain-bulk junction

1

85 PBRBOTD V 4 0.1 − Breakdown onset tuning parameterof bottom component fordrain-bulk junction

1

86 PBRSTID V 4 0.1 − Breakdown onset tuning parameterof STI-edge component fordrain-bulk junction

1

87 PBRGATD V 4 0.1 − Breakdown onset tuning parameterof gate-edge component fordrain-bulk junction

1

JUNCAP Express Parameters

88 VJUNREFD V 2.5 0.5 − Typical maximum drain-bulkjunction voltage; usually about2 · Vsup

1

89 FJUNQD V 0.03 0 − Fraction below which drain-bulkjunction capacitance componentsare neglected

1



2.5.6 Parameters for parasitic resistances

The parameters for parasitic resistances are listed in the table below. The last column—labeled ‘Geo.’—showsfor which value of SWGEO the parameter is used.


0 RG Ω 0 0 − Gate resistance Rgate 0

1 RGO Ω 0 − − Gate resistance Rgate 1, 22 RINT Ω·m2 0 0 − Contact resistance between silicide

and ploy1, 2

3 RVPOLY Ω·m2 0 0 − Vertical poly resistance 1, 24 RSHG Ω/ 0 0 − Gate electrode diffusion sheet

resistance1, 2

5 DLSIL m 0 − − Silicide extension over the physicalgate length

1, 2

6 RSE Ω 0 0 − External source resistance 0

7 RDE Ω 0 0 − External drain resistance 0

8 RSH Ω/ 0 − − Sheet resistance of source diffusion 1, 2

9 RSHD Ω/ 0 − − Sheet resistance of drain diffusion 1, 2

10 RBULK Ω 0 0 − Bulk resistance Rbulk 0

11 RBULKO Ω 0 − − Bulk resistance Rbulk 1, 2

12 RWELL Ω 0 0 − Well resistance Rwell 0

13 RWELLO Ω 0 − − Well resistance Rwell 1, 2

14 RJUNS Ω 0 0 − Source-side bulk resistance Rjuns 0

15 RJUNSO Ω 0 − − Source-side bulk resistance Rjuns 1, 2

16 RJUND Ω 0 0 − Drain-side bulk resistance Rjund 0

17 RJUNDO Ω 0 − − Drain-side bulk resistance Rjund 1, 2



2.5.7 Parameters for self heating

The parameters for self heating are listed below. They are only available in the self heating version of themodel. The last column—labeled ‘Geo.’—shows for which value of SWGEO the parameter is used.


0 RTH K/W 0 0 − Thermal resistance 0

1 RTHO K/W 0 − − Geometry independent part 1, 22 RTHW1 K/W 0 − − Width dependence 1, 23 RTHW2 – 0 − − Offset in width dependence 1, 24 RTHLW – 0 − − Length-correction to width

dependence1, 2

5 CTH J/K 0 0 − Thermal capacitance 0

6 CTHO J/K 0 − − Geometry independent part 1, 27 CTHW1 J/K 0 − − Width dependence 1, 28 CTHW2 – 0 − − Offset in width dependence 1, 29 CTHLW – 0 − − Length-correction to width

dependence1, 2

10 STRTH – 0 − − Temperature sensitivity of RTH 0

11 STRTHO – 0 − − Geometry independent part 1, 2



2.5.8 Parameters for NQS

The parameters for non-quasi-static effects are listed below. They are only available in the NQS-version of themodel. The last column—labeled ‘Geo.’—shows for which value of SWGEO the parameter is used.


0 SWNQS – 0 0 9 Switch for NQS effects / number ofcollocation points

0, 1, 2

1 MUNQS – 1 0 − Relative mobility for NQSmodeling

0

2 MUNQSO – 1 − − Relative mobility for NQSmodeling

1, 2





Section 3

Geometry dependence and Other effects

3.1 Introduction

The physical geometry scaling rules of PSP (Section 3.2) have been developed to give a good description overthe whole geometry range of CMOS technologies. As an alternative, the binning-rules can be used (Section 3.3)to allow for a more phenomenological geometry dependency. (Note that the user has to choose between thetwo options; the geometrical scaling rules and the binning scaling rules cannot be used at the same time.) Inboth cases, the result is a local parameter set (for a transistor of the specified L and W ), which is fed into thelocal model.

Stress and well proximity effects are included in PSP. Use of the stress model (Section 3.5) and/or well prox-imity effect model (Section 3.6) leads to modification of some of the local parameters calculated from thegeometrical or binning scaling rules.

3.2 Geometrical scaling rules

The physical scaling rules to calculate the local parameters from a global parameter set are given in this section.

Note:• After calculation of the local parameters (and possible application of the stress equations in Section 3.5),

clipping is applied according to Section 2.5.2.• The geometrical scaling equations are only calculated when SWGEO = 1.

Effective length and width

Wf =W

NF(3.1)

Wf =W

NF(3.2)

LEN = 10−6 (3.3)

WEN = 10−6 (3.4)

∆LPS = LVARO ·(

1 + LVARL · LEN

L

)·(

1 + LVARW · WEN

Wf

)(3.5)

∆WOD = WVARO ·(

1 + WVARL · LEN

L

)·(

1 + WVARW · WEN

Wf

)(3.6)



Cross section

gatep p p p p p p p p p p p p p p p p p p p p p p p p p p p p pp p p p p p p p p p p p p p p p p p p p p p p p p p p p pp p p p p p p p p p p p p p p p p p p p p p p p p p p p p p!source "drain

Top viewsource drain

-L+ ∆LPS

-LE

6

?

Wf + ∆WOD

6

?

WE

6WOT

?WOT

- LAP LAP

Figure 3.1: Specification of the dimensions of a MOS transistor

LE = L−∆L = L+ ∆LPS − 2 · LAP (3.7)

WE = Wf −∆W = Wf + ∆WOD − 2 ·WOT (3.8)

LE,CV = L+ ∆LPS − 2 · LAP + DLQ (3.9)

WE,CV = Wf + ∆WOD − 2 ·WOT + DWQ (3.10)

LG,CV = L+ ∆LPS + DLQ (3.11)

WG,CV = Wf + ∆WOD + DWQ (3.12)

Note: If the calculated LE, WE, LE,CV, WE,CV, LG,CV, or WG,CV is smaller than 1 nm (10−9 m), the valueis clipped to this lower bound of 1 nm.

Process Parameters

VFB = VFBO + VFBL · LEN

LE+ VFBW · WEN

WE+ VFBLW · WEN · LEN

WE · LE(3.13)

STVFB = STVFBO + STVFBL · LEN

LE+ STVFBW · WEN

WE+ STVFBLW · WEN · LEN

WE · LE(3.14)

ST2VFB = ST2VFBO (3.15)

TOX = TOXO (3.16)

EPSROX = EPSROXO (3.17)



Nsub0,eff = NSUBO ·MAX([

1 + NSUBW · WEN

WE· ln(

1 +WE

WSEG

)], 10−3

)(3.18)

Npck,eff = NPCK ·MAX([

1 + NPCKW · WEN

WE· ln(

1 +WE

WSEGP

)], 10−3

)(3.19)

Lpck,eff = LPCK ·MAX([

1 + LPCKW · WEN

WE· ln(

1 +WE

WSEGP

)], 10−3

)(3.20)

a = 7.5 · 1010 (3.21)

b =√Nsub0,eff + 0.5 ·Npck,eff −

√Nsub0,eff (3.22)

Nsub =

Nsub0,eff +Npck,eff ·[2− LE

Lpck,eff

]for LE < Lpck,eff

Nsub0,eff +Npck,eff ·Lpck,eff

LEfor Lpck,eff ≤ LE ≤ 2 · Lpck,eff

[√Nsub0,eff +

a · ln(

1 + 2 · Lpck,eff

LE·[exp

(b

a

)− 1

])]2

for LE > 2 · Lpck,eff

(3.23)

NEFF = Nsub ·

(1− FOL1 · LEN

LE− FOL2 ·

[LEN

LE

]2)

(3.24)

FACNEFFAC = FACNEFFACO + FACNEFFACL · LEN

LE

+ FACNEFFACW · WEN

WE+ FACNEFFACLW · LEN ·WEN

LE ·WE(3.25)

GFACNUD = GFACNUDO + GFACNUDL ·[LEN

LE

]GFACNUDLEXP

+ GFACNUDW · WEN

WE+ GFACNUDLW · LEN ·WEN

LE ·WE(3.26)

VSBNUD = VSBNUDO (3.27)

DVSBNUD = DVSBNUDO (3.28)

VNSUB = VNSUBO (3.29)

NSLP = NSLPO (3.30)

DNSUB = DNSUBO (3.31)



DPHIB = DPHIBO + DPHIBL ·[LEN

LE

]DPHIBLEXP

+ DPHIBW · WEN

WE+ DPHIBLW · WEN · LEN

WE · LE(3.32)

DELVTAC = DELVTACO + DELVTACL ·[LEN

LE

]DELVTACLEXP

+ DELVTACW · WEN

WE+ DELVTACLW · WEN · LEN

WE · LE(3.33)

NP = NPO ·MAX

(10−6, 1 + NPL · LEN

LE

)(3.34)

TOXOV = TOXOVO (3.35)

TOXOVD = TOXOVDO (3.36)

NOV = NOVO (3.37)

NOVD = NOVDO (3.38)


CT =

(CTO + CTL ·

[LEN

LE

]CTLEXP)·(

1 + CTW · WEN

WE

)

·(

1 + CTLW · WEN · LEN

WE · LE

)(3.39)

CTG = STGO (3.40)

CTB = CTBO (3.41)

STCT = STCTO (3.42)

DIBL Parameters

CF = CFL ·[LEN

LE

]CFLEXP

·(

1 + CFW · WEN

WE

)(3.43)

CFB = CFBO (3.44)

CFD = CFDO (3.45)


PSCE = PSCEL ·[LEN

LE

]PSCELEXP

·(

1 + PSCEW · WEN

WE

)(3.46)

PSCEB = PSCEBO (3.47)

PSCED = PSCEDO (3.48)



Mobility Parameters

Fβ1,eff = FBET1 ·(

1 + FBET1W · WEN

WE

)(3.49)

LP1,eff = LP1 ·MAX

([1 + LP1W · WEN

WE

], 10−3

)(3.50)

GP,E = 1 + Fβ1,eff ·LP1,eff

LE·[1− exp

(− LE

LP1,eff

)](3.51)

+ FBET2 · LP2LE·[1− exp

(− LE

LP2

)]

GW,E = 1 + BETW1 · WEN

WE+ BETW2 · WEN

WE· ln(

1 +WE

WBET

)(3.52)

BETN =UOGP,E

· WE

LE·GW,E (3.53)

STBET = STBETO + STBETL · LEN

LE+ STBETW · WEN

WE+ STBETLW · WEN · LEN

WE · LE(3.54)

MUE = MUEO ·[1 + MUEW · WEN

WE

](3.55)

STMUE = STMUEO (3.56)

THEMU = THEMUO (3.57)

STTHEMU = STTHEMUO (3.58)

CS =

(CSO + CSL ·

[LEN

LE

]CSLEXP)·(

1 + CSW · WEN

WE

)

·(

1 + CSLW · WEN · LEN

WE · LE

)(3.59)

STCS = STCSO (3.60)

THECS = THECSO (3.61)

STTHECS = STTHECSO (3.62)

XCOR = XCORO ·(

1 + XCORL · LEN

LE

)·(

1 + XCORW · WEN

WE

)

·(

1 + XCORLW · WEN · LEN

WE · LE

)(3.63)

STXCOR = STXCORO (3.64)

FETA = FETAO (3.65)




RS = RSW1 · WEN

WE·[1 + RSW2 · WEN

WE

](3.66)

STRS = STRSO (3.67)

RSB = RSBO (3.68)

RSG = RSGO (3.69)


THESAT =

(THESATO + THESATL · GW,E

GP,E·[LEN

LE

]THESATLEXP)

·(

1 + THESATW · WEN

WE

)·(

1 + THESATLW · WEN · LEN

WE · LE

)(3.70)

STTHESAT = STTHESATO + STTHESATL · LEN

LE

+ STTHESATW · WEN

WE+ STTHESATLW · WEN · LEN

WE · LE(3.71)

THESATB = THESATBO (3.72)

THESATG = THESATGO (3.73)

Saturation Voltage Parameter

AX =AXO

1 + AXL · LEN

LE

(3.74)


ALP = ALPL ·[LEN

LE

]ALPLEXP

·(

1 + ALPW · WEN

WE

)(3.75)

ALP1 =

ALP1L1 ·[LEN

LE

]ALP1LEXP

1 + ALP1L2 ·[LEN

LE

]ALP1LEXP+1·(

1 + ALP1W · WEN

WE

)(3.76)

ALP2 =

ALP2L1 ·[LEN

LE

]ALP2LEXP

1 + ALP2L2 ·[LEN

LE

]ALP2LEXP+1·(

1 + ALP2W · WEN

WE

)(3.77)

VP = VPO (3.78)




A1 = A1O ·(

1 + A1L · LEN

LE

)·(

1 + A1W · WEN

WE

)(3.79)

A2 = A2O (3.80)

STA2 = STA2O (3.81)

A3 = A3O ·(

1 + A3L · LEN

LE

)·(

1 + A3W · WEN

WE

)(3.82)

A4 = A4O ·(

1 + A4L · LEN

LE

)·(

1 + A4W · WEN

WE

)(3.83)


GCO = GCOO (3.84)

IGINV = IGINVLW · WE · LE

WEN · LEN(3.85)

IGOV = IGOVW · WE · LOVWEN · LEN

(3.86)

IGOVD = IGOVDW · WE · LOVDWEN · LEN

(3.87)

STIG = STIGO (3.88)

GC2 = GC2O (3.89)

GC3 = GC3O (3.90)

CHIB = CHIBO (3.91)


AGIDL = AGIDLW · WE · LOVWEN · LEN

(3.92)

AGIDLD = AGIDLDW · WE · LOVDWEN · LEN

(3.93)

BGIDL = BGIDLO (3.94)

BGIDLD = BGIDLDO (3.95)

STBGIDL = STBGIDLO (3.96)

STBGIDLD = STBGIDLDO (3.97)

CGIDL = CGIDLO (3.98)

CGIDLD = CGIDLDO (3.99)




εox = ε0 · EPSROX (3.100)

COX = εox ·WE,CV · LE,CV

TOX(3.101)

CGOV = εox ·WE,CV · LOV

TOXOV(3.102)

CGOVD = εox ·WE,CV · LOVD

TOXOVD(3.103)

CGBOV = CGBOVL · LG,CV

LEN(3.104)

CFR = CFRW · WG,CV

WEN(3.105)

CFRD = CFRDW · WG,CV

WEN(3.106)

Thermal Noise Model Parameters

Note that the equation below makes use of the value of BETN calculated in Eq. (3.53). Because BETN isroughly proportional to WE/LE, the resulting FNTEXC is roughly proportional to 1/L2

E. In addition, it willinherit some minor L- and W -dependence from BETN.

FNTEXC = FNTEXCL · BETN2 ·[WEN

WE

]2

(3.107)

Flicker Noise Model Parameters

Lnoi = MAX(

1− 2 · LINTNOILE

, 10−3

)(3.108)

Lred =1

LALPNOInoi

(3.109)

NFA = Lred · NFALW · WEN · LEN

WE · LE(3.110)

NFB = Lred · NFBLW · WEN · LEN

WE · LE(3.111)

NFC = Lred · NFCLW · WEN · LEN

WE · LE(3.112)

EF = EFO (3.113)

Edge transistor parameters

WE,edge = 2 ·WEDGE + WEDGEW ·WE (3.114)

VFBEDGE = VFBEDGEO (3.115)



STVFBEDGE = STVFBEDGEO + STVFBEDGEL · LEN

LE

+ STVFBEDGEW · WEN

WE+ STVFBEDGELW · WEN · LEN

WE · LE(3.116)

DPHIBEDGE = DPHIBEDGEO + DPHIBEDGEL ·[LEN

LE

]DPHIBEDGELEXP

+ DPHIBEDGEW · WEN

WE+ DPHIBEDGELW · WEN · LEN

WE · LE(3.117)

NEFFEDGE = NSUBEDGEO ·

(1 + NSUBEDGEL ·

[LEN

LE

]NSUBEDGELEXP)

·(

1 + NSUBEDGEW · WEN

WE

)·(

1 + NSUBEDGELW · WEN · LEN

WE · LE

)(3.118)

CTEDGE =

(CTEDGEO + CTEDGEL ·

[LEN

LE

]CTEDGELEXP)

(3.119)

GPE,edge = 1 + FBETEDGE · LPEDGELE

·[1− exp

(− LE

LPEDGE

)](3.120)

BETNEDGE =UO

GPE,edge· WE,edge

LE·(

1 + BETEDGEW · WEN

WE

)(3.121)

STBETEDGE = STBETEDGEO + STBETEDGEL · LEN

LE

+ STBETEDGEW · WEN

WE+ STBETEDGELW · WEN · LEN

WE · LE(3.122)

PSCEEDGE = PSCEEDGEL ·[LEN

LE

]PSCEEDGELEXP

·(

1 + PSCEEDGEW · WEN

WE

)(3.123)

PSCEBEDGE = PSCEBEDGEO (3.124)

PSCEDEDGE = PSCEDEDGEO (3.125)

CFEDGE = CFEDGEL ·[LEN

LE

]CFEDGELEXP

·(

1 + CFEDGEW · WEN

WE

)(3.126)

CFDEDGE = CFDEDGEO (3.127)

CFBEDGE = CFBEDGEO (3.128)

FNTEDGE = FNTEDGEO (3.129)

NFAEDGE = NFAEDGELW · WEN · LEN

WE,edge · LE(3.130)



NFBEDGE = NFBEDGELW · WEN · LEN


NFCEDGE = NFCEDGELW · WEN · LEN


EFEDGE = EFEDGEO (3.133)

WPE parameters

Kvthowe = KVTHOWEO + KVTHOWEL · LEN

LE+ KVTHOWEW · WEN

WE

+ KVTHOWELW · LEN ·WEN

LE ·WE(3.134)

Kuowe = KUOWEO + KUOWEL · LEN

LE+ KUOWEW · WEN

WE

+ KUOWELW · LEN ·WEN

LE ·WE(3.135)

Self heating parameters

RTH = RTHO +RTHW1

RTHW2 +WE

WEN·[1 + RTHLW · LE

LEN

] (3.136)

CTH = CTHO + CTHW1 ·

CTHW2 +WE

WEN·[1 + CTHLW · LE

LEN

](3.137)

STRTH = STRTHO (3.138)

NQS parameters

MUNQS = MUNQSO (3.139)



3.3 Binning equations

The binning equations are provided as a (phenomenological) alternative to the physical scaling equations forcomputing local parameters. The physical geometrical scaling rules have been developed to give a good de-scription over the whole geometry range of CMOS technologies. For processes under development, however,it is sometimes useful to have more flexible scaling relations. In that case on could opt for a binning strategy,where the accuracy with geometry is mostly determined by the number of bins used. The physical scaling rulesof Section 3.2 are generally not suitable for binning strategies, since they may result in discontinuities in localparameter values at the bin boundaries. Consequently, special binning geometrical scaling relations have beendeveloped, which guarantee continuity of the resulting local model parameters at the bin boundaries.

Note: The binning equations are only calculated when SWGEO = 2.

Only four different types of binning scaling rules are used, which are based on first order developments of thegeometrical scaling rules in terms of LE, 1/LE, WE, and 1/WE (examples below are for a fictitious parameterYYY):

1. Type I

YYY = POYYY + PLYYY · LEN

LE+ PWYYY · WEN

WE+ PLWYYY · LEN ·WEN

LE ·WE(3.140)

2. Type II

YYY = POYYY + PLYYY · LE

LEN+ PWYYY · WE

WEN+ PLWYYY · LE ·WE

LEN ·WEN(3.141)

3. Type III

YYY = POYYY + PLYYY · LEN

LE+ PWYYY · WE

WEN+ PLWYYY · WE · LEN

WEN · LE(3.142)

4. Type IV (no binning)

YYY = POYYY (3.143)

In Table 3.2 a survey of the binning type used for each local parameter is given. In some cases where thegeometrical scaling rule is constant, the binning rule is chosen to be more flexible.

When using the binning rules above, the binning parameters for one bin can be directly calculated from thelocal parameter sets of the four corner devices of the bin (see Sec. 7.6). This results in a separate parameter setfor each bin. The binning scheme ensures that the local parameters are exactly reproduced at the bin cornersand that no humps occur in the local parameter values across bin boundaries.

Note: After calculation of the local parameters from the binning rules (and possible applications of the stressequations in Section 3.5 and well proximity equations in Section 3.6), clipping is applied according to Sec-tion 2.5.2.



Table 3.1: Overview of local parameters and binning type. The third column indicateswhether there is a physical geometrical scaling rule for the local parameters.

# parameter physical scaling binning # parameter physical scaling binning

0 VFB yes type I 43 RS yes type I1 STVFB yes type I 44 STRS no no2 ST2VFB no no 45 RSB no no3 TOX no no 46 RSG no no4 EPSROX no no 47 THESAT yes type I5 NEFF yes type I 48 STTHESAT yes type I6 FACNEFFAC yes type I 49 THESATB no type I7 GFACNUD yes type I 50 THESATG no type I8 VSBNUD no no 51 AX yes type I9 DVSBNUD no no 52 ALP yes type I10 VNSUB no no 53 ALP1 yes type I11 NSLP no no 54 ALP2 yes type I12 DNSUB no no 55 VP no no13 DPHIB yes type I 56 A1 yes type I14 DELVTAC yes type I 57 A2 no no15 NP yes type I 58 STA2 no no16 TOXOV no no 59 A3 yes type I17 TOXOVD no no 60 A4 yes type I18 NOV no type I 61 GCO no no19 NOVD no type I 62 IGINV yes type II20 CT yes type I 63 IGOV yes type III21 CTG no no 64 IGOVD yes type III22 CTB no no 65 STIG no no23 STCT no no 66 GC2 no no24 CF yes type I 67 GC3 no no25 CFB no no 68 CHIB no no26 CFD no no 69 AGIDL yes type III27 PSCE yes type I 70 AGIDLD yes type III28 PSCEB no no 71 BGIDL no no29 PSCED no no 72 BGIDLD no no30 BETN yes type I 73 STBGIDL no no31 STBET yes type I 74 STBGIDLD no no32 MUE yes type I 75 CGIDL no no33 STMUE no no 76 CGIDL no no34 THEMU no no 77 CGIDLD no no35 STTHEMU no no 78 COX yes type II36 CS yes type I 79 CGOV yes type III37 STCS no no 80 CGOVD yes type III38 THECS no no 81 CGBOV yes type II39 STTHECS no no 82 CFR yes type III40 XCOR yes type I 83 CFRD yes type III41 STXCOR no no 84 FNT no no42 FETA no no 85 FNTEXC yes type I



Table 3.2: Overview of local parameters and binning type. The third column indicateswhether there is a physical geometrical scaling rule for the local parameters.

# parameter physical scaling binning # parameter physical scaling binning

86 NFA yes type I 98 PSCEEDGE yes type I87 NFB yes type I 99 PSCEBEDGE no no88 NFC yes type I 100 PSCEDEDGE no no89 EF no no 101 CFEDGE yes type I90 DTA no no 102 CFDEDGE no no91 VFBEDGE no no 103 CFBEDGE no no92 STVFBEDGE yes type I 104 FNTEDGE no no93 DPHIBEDGE yes type I 105 NFAEDGE yes type I94 NEFFEDGE yes type I 106 NFBEDGE yes type I95 CTEDGE yes type I 107 NFCEDGE yes type I96 BETNEDGE yes type I 108 EFEDGE no no97 STBETEDGE yes type I

Effective length and width

LEN = 10−6 (3.144)

WEN = 10−6 (3.145)

∆LPS = LVARO ·(

1 + LVARL · LEN

L

)(3.146)

∆WOD = WVARO ·(

1 + WVARW · WEN

Wf

)(3.147)

LE = L−∆L = L+ ∆LPS − 2 · LAP (3.148)

WE = Wf −∆W = Wf + ∆WOD − 2 ·WOT (3.149)

LE,CV = L+ ∆LPS − 2 · LAP + DLQ (3.150)

WE,CV = Wf + ∆WOD − 2 ·WOT + DWQ (3.151)

LG,CV = L+ ∆LPS + DLQ (3.152)

WG,CV = Wf + ∆WOD + DWQ (3.153)

Note: If the calculated LE, WE, LE,CV, WE,CV, LG,CV, or WG,CV is smaller than 1 nm (10−9 m), the valueis clipped to this lower bound of 1 nm.

Process Parameters

VFB = POVFB + PLVFB · LEN

LE+ PWVFB · WEN

WE+ PLWVFB · LEN ·WEN

LE ·WE(3.154)



STVFB = POSTVFB + PLSTVFB · LEN

LE

+ PWSTVFB · WEN

WE+ PLWSTVFB · LEN ·WEN

LE ·WE(3.155)

ST2VFB = POST2VFB (3.156)

TOX = POTOX (3.157)

EPSROX = POEPSROX (3.158)

NEFF = PONEFF + PLNEFF · LEN

LE+ PWNEFF · WEN

WE+ PLWNEFF · LEN ·WEN

LE ·WE(3.159)

FACNEFFAC = POFACNEFFAC + PLFACNEFFAC · LEN

LE

+ PWFACNEFFAC · WEN

WE+ PLWFACNEFFAC · LEN ·WEN

LE ·WE(3.160)

GFACNUD = POGFACNUD + PLGFACNUD · LEN

LE

+ PWGFACNUD · WEN

WE+ PLWGFACNUD · LEN ·WEN

LE ·WE(3.161)

VSBNUD = POVSBNUD (3.162)

DVSBNUD = PODVSBNUD (3.163)

VNSUB = POVNSUB (3.164)

NSLP = PONSLP (3.165)

DNSUB = PODNSUB (3.166)

DPHIB = PODPHIB + PLDPHIB · LEN

LE

+ PWDPHIB · WEN

WE+ PLWDPHIB · LEN ·WEN

LE ·WE(3.167)

DELVTAC = PODELVTAC + PLDELVTAC · LEN

LE

+ PWDELVTAC · WEN

WE+ PLWDELVTAC · LEN ·WEN

LE ·WE(3.168)

NP = PONP + PLNP · LEN

LE+ PWNP · WEN

WE+ PLWNP · LEN ·WEN

LE ·WE(3.169)

TOXOV = POTOXOV (3.170)



TOXOVD = POTOXOVD (3.171)

NOV = PONOV + PLNOV · LEN

LE+ PWNOV · WEN

WE+ PLWNOV · LEN ·WEN

LE ·WE(3.172)

NOVD = PONOVD + PLNOVD · LEN

LE+ PWNOVD · WEN

WE+ PLWNOVD · LEN ·WEN

LE ·WE(3.173)


CT = POCT + PLCT · LEN

LE+ PWCT · WEN

WE+ PLWCT · LEN ·WEN

LE ·WE(3.174)

CTG = POCTG (3.175)

CTB = POCTB (3.176)

STCT = POSTCT (3.177)

DIBL Parameters

CF = POCF + PLCF · LEN

LE+ PWCF · WEN

WE+ PLWCF · LEN ·WEN

LE ·WE(3.178)

CFB = POCFB (3.179)

CFD = POCFD (3.180)


PSCE = POPSCE + PLPSCE · LEN

LE+ PWPSCE · WEN

WE+ PLWPSCE · LEN ·WEN

LE ·WE(3.181)

PSCEB = POPSCEB (3.182)

PSCED = POPSCED (3.183)

Mobility Parameters

BETN =WE

LE·

(POBETN + PLBETN · LEN

LE

+ PWBETN · WEN

WE+ PLWBETN · LEN ·WEN

LE ·WE

)(3.184)

(See Section 7.6.1 for an explanation of this binning rule.)

STBET = POSTBET + PLSTBET · LEN

LE

+ PWSTBET · WEN

WE+ PLWSTBET · LEN ·WEN

LE ·WE(3.185)



MUE = POMUE + PLMUE · LEN

LE+ PWMUE · WEN

WE+ PLWMUE · LEN ·WEN

LE ·WE(3.186)

STMUE = POSTMUE (3.187)

THEMU = POTHEMU (3.188)

STTHEMU = POSTTHEMU (3.189)

CS = POCS + PLCS · LEN

LE+ PWCS · WEN

WE+ PLWCS · LEN ·WEN

LE ·WE(3.190)

STCS = POSTCS (3.191)

THECS = POTHECS (3.192)

STTHECS = POSTTHECS (3.193)

XCOR = POXCOR + PLXCOR · LEN

LE+ PWXCOR · WEN

WE+ PLWXCOR · LEN ·WEN

LE ·WE(3.194)

STXCOR = POSTXCOR (3.195)

FETA = POFETA (3.196)


RS = PORS + PLRS · LEN

LE+ PWRS · WEN

WE+ PLWRS · LEN ·WEN

LE ·WE(3.197)

STRS = POSTRS (3.198)

RSB = PORSB (3.199)

RSG = PORSG (3.200)


THESAT = POTHESAT + PLTHESAT · LEN

LE

+ PWTHESAT · WEN

WE+ PLWTHESAT · LEN ·WEN

LE ·WE(3.201)

STTHESAT = POSTTHESAT + PLSTTHESAT · LEN

LE

+ PWSTTHESAT · WEN

WE+ PLWSTTHESAT · LEN ·WEN

LE ·WE(3.202)

THESATB = POTHESATB + PLTHESATB · LEN

LE

+ PWTHESATB · WEN

WE+ PLWTHESATB · LEN ·WEN

LE ·WE(3.203)



THESATG = POTHESATG + PLTHESATG · LEN

LE

+ PWTHESATG · WEN

WE+ PLWTHESATG · LEN ·WEN

LE ·WE(3.204)

Saturation Voltage Parameters

AX = POAX + PLAX · LEN

LE+ PWAX · WEN

WE+ PLWAX · LEN ·WEN

LE ·WE(3.205)


ALP = POALP + PLALP · LEN

LE+ PWALP · WEN

WE+ PLWALP · LEN ·WEN

LE ·WE(3.206)

ALP1 = POALP1 + PLALP1 · LEN

LE+ PWALP1 · WEN

WE+ PLWALP1 · LEN ·WEN

LE ·WE(3.207)

ALP2 = POALP2 + PLALP2 · LEN

LE+ PWALP2 · WEN

WE+ PLWALP2 · LEN ·WEN

LE ·WE(3.208)

VP = POVP (3.209)


A1 = POA1 + PLA1 · LEN

LE+ PWA1 · WEN

WE+ PLWA1 · LEN ·WEN

LE ·WE(3.210)

A2 = POA2 (3.211)

STA2 = POSTA2 (3.212)


LE+ PWA3 · WEN


LE ·WE(3.213)


LE+ PWA4 · WEN


LE ·WE(3.214)


GCO = POGCO (3.215)

IGINV = POIGINV + PLIGINV · LE

LEN

+ PWIGINV · WE

WEN+ PLWIGINV · LE ·WE

LEN ·WEN(3.216)

IGOV = POIGOV + PLIGOV · LEN

LE+ PWIGOV · WE

WEN+ PLWIGOV · WE · LEN

WEN · LE(3.217)



IGOVD = POIGOVD + PLIGOVD · LEN

LE

+ PWIGOVD · WE

WEN+ PLWIGOVD · WE · LEN

WEN · LE(3.218)

STIG = POSTIG (3.219)

GC2 = POGC2 (3.220)

GC3 = POGC3 (3.221)

CHIB = POCHIB (3.222)


AGIDL = POAGIDL + PLAGIDL · LEN

LE

+ PWAGIDL · WE

WEN+ PLWAGIDL · WE · LEN

WEN · LE(3.223)

AGIDLD = POAGIDLD + PLAGIDLD · LEN

LE

+ PWAGIDLD · WE

WEN+ PLWAGIDLD · WE · LEN

WEN · LE(3.224)

BGIDL = POBGIDL (3.225)

BGIDLD = POBGIDLD (3.226)

STBGIDL = POSTBGIDL (3.227)

STBGIDLD = POSTBGIDLD (3.228)

CGIDL = POCGIDL (3.229)

CGIDLD = POCGIDLD (3.230)


COX = POCOX + PLCOX · LE,CV

LEN+ PWCOX · WE,CV

WEN+ PLWCOX · LE,CV ·WE,CV

LEN ·WEN(3.231)

CGOV = POCGOV + PLCGOV · LEN

LE,CV

+ PWCGOV · WE,CV

WEN+ PLWCGOV · WE,CV · LEN

WEN · LE,CV(3.232)



CGOVD = POCGOVD + PLCGOVD · LEN

LE,CV

+ PWCGOVD · WE,CV

WEN+ PLWCGOVD · WE,CV · LEN

WEN · LE,CV(3.233)

CGBOV = POCGBOV + PLCGBOV · LG,CV

LEN

+ PWCGBOV · WG,CV

WEN+ PLWCGBOV · LG,CV ·WG,CV

LEN ·WEN(3.234)

CFR = POCFR + PLCFR · LEN

LG,CV+ PWCFR · WG,CV

WEN+ PLWCFR · WG,CV · LEN

WEN · LG,CV(3.235)

CFRD = POCFRD + PLCFRD · LEN

LG,CV+ PWCFRD ·WG,CV

WEN+ PLWCFRD ·WG,CV · LEN

WEN · LG,CV(3.236)

Thermal Noise Model Parameters

FNT = POFNT (3.237)

FNTEXC =

[LEN

LE

]2

·

(POFNTEXC + PLFNTEXC · LEN

LE

+ PWFNTEXC · WEN

WE+ PLWFNTEXC · LEN ·WEN

LE ·WE

)(3.238)

Flicker Noise Model Parameters

NFA = PONFA + PLNFA · LEN

LE+ PWNFA · WEN

WE+ PLWNFA · LEN ·WEN

LE ·WE(3.239)

NFB = PONFB + PLNFB · LEN

LE+ PWNFB · WEN

WE+ PLWNFB · LEN ·WEN

LE ·WE(3.240)

NFC = PONFC + PLNFC · LEN

LE+ PWNFC · WEN

WE+ PLWNFC · LEN ·WEN

LE ·WE(3.241)

EF = POEF (3.242)


VFBEDGE = POVFBEDGE (3.243)

STVFBEDGE = POSTVFBEDGE + PLSTVFBEDGE · LEN

LE

+ PWSTVFBEDGE · WEN

WE+ PLWSTVFBEDGE · LEN ·WEN

LE ·WE(3.244)



DPHIBEDGE = PODPHIBEDGE + PLDPHIBEDGE · LEN

LE

+ PWDPHIBEDGE · WEN

WE+ PLWDPHIBEDGE · LEN ·WEN

LE ·WE(3.245)

NEFFEDGE = PONEFFEDGE + PLNEFFEDGE · LEN

LE

+ PWNEFFEDGE · WEN

WE+ PLWNEFFEDGE · LEN ·WEN

LE ·WE(3.246)

CTEDGE = POCTEDGE + PLCTEDGE · LEN

LE

+ PWCTEDGE · WEN

WE+ PLWCTEDGE · LEN ·WEN

LE ·WE(3.247)

BETNEDGE =LEN

LE·

(POBETNEDGE + PLBETNEDGE · LEN

LE

+ PWBETNEDGE · WEN

WE+ PLWBETNEDGE · LEN ·WEN

LE ·WE

)(3.248)

STBETEDGE = POSTBETEDGE + PLSTBETEDGE · LEN

LE

+ PWSTBETEDGE · WEN

WE+ PLWSTBETEDGE · LEN ·WEN

LE ·WE(3.249)

PSCEEDGE = POPSCEEDGE + PLPSCEEDGE · LEN

LE

+ PWPSCEEDGE · WEN

WE+ PLWPSCEEDGE · LEN ·WEN

LE ·WE(3.250)

PSCEBEDGE = POPSCEBEDGE (3.251)

PSCEDEDGE = POPSCEDEDGE (3.252)

CFEDGE = POCFEDGE + PLCFEDGE · LEN

LE

+ PWCFEDGE · WEN

WE+ PLWCFEDGE · LEN ·WEN

LE ·WE(3.253)

CFDEDGE = POCFDEDGE (3.254)

CFBEDGE = POCFBEDGE (3.255)

FNTEDGE = POFNTEDGE (3.256)



NFAEDGE = PONFAEDGE + PLNFAEDGE · LEN

LE

+ PWNFAEDGE · WEN

WE+ PLWNFAEDGE · LEN ·WEN

LE ·WE(3.257)

NFBEDGE = PONFBEDGE + PLNFBEDGE · LEN

LE

+ PWNFBEDGE · WEN

WE+ PLWNFBEDGE · LEN ·WEN

LE ·WE(3.258)

NFCEDGE = PONFCEDGE + PLNFCEDGE · LEN

LE

+ PWNFCEDGE · WEN

WE+ PLWNFCEDGE · LEN ·WEN

LE ·WE(3.259)

EFEDGE = POEFEDGE (3.260)

WPE parameters

Kvthowe = POKVTHOWE + PLKVTHOWE · LEN

LE+ PWKVTHOWE · WEN

WE

+ PLWKVTHOWE · LEN ·WEN

LE ·WE(3.261)

Kuowe = POKUOWE + PLKUOWE · LEN

LE+ PWKUOWE · WEN

WE

+ PLWKUOWE · LEN ·WEN

LE ·WE(3.262)

Self heating parameters

(Also for SWGEO = 2, the geometrical scaling rules are used.)

RTH = RTHO +RTHW1

RTHW2 +WE

WEN·[1 + RTHLW · LE

LEN

] (3.263)

CTH = CTHO + CTHW1 ·

CTHW2 +WE

WEN·[1 + CTHLW · LE

LEN

](3.264)

STRTH = STRTHO (3.265)

NQS parameters

(Also for SWGEO = 2, the geometrical scaling rules are used.)

MUNQS = MUNQSO (3.266)



3.4 Parasitic resistances

PSP model contains a network of parasitic elements: a gate resistance, two diffusion resistances for sourceand drain, and four bulk resistances. Note that the junction diodes are no longer directly connected to the bulkterminal of the intrinsic MOS-transistor. The complete circuit is shown in Fig. 3.2. At this moment, only thegate resistance is scaled with geometry (facilitating the implementation of multi-finger devices).

Note: The resistance equations are calculated when SWGEO = 1 or 2.

Lf = L+ ∆LPS (3.267)

Lsil,f = Lf + DLSIL (3.268)

WE,f = Wf + ∆WOD (3.269)

XGWE = XGW− 0.5 ·∆WOD (3.270)

RG = RGO +1

NF·

RSHG ·(

WE,f

3·NGCON +XGWE

)NGCON · Lsil,f

+RINT + RVPOLY

WE,f · Lf

(3.271)

RSE = NRS · RSH (3.272)

RDE = NRD · RSHD (3.273)

RBULK = RBULKO (3.274)

RWELL = RWELLO (3.275)

RJUNS = RJUNSO (3.276)

RJUND = RJUNDO (3.277)

Note: The values of Lf , Lsil,f , WE,f and XGWE are clipped to a minimum value of 1 nm. The calculated localparameters are subject to the boundaries specified in Section 2.5.6.

GP

BPDI

BD

D

BI

B

BS

SIS

G

Rgate

Rbulk

RdrainRsource

Rjuns Rjund

Rwell

Figure 3.2: Parasitics circuit



3.5 Stress effects

The stress model of BSIM4.4.0 [3] has been adopted in PSP without any modifications, except for two changes:(1) in the original BSIM parameter names all zeros have been replaced by “O”s, in order to comply with PSPconventions and (2) the BSIM parameters STK2 and LODK2 are not available in PSP. Some trivial conversionof parameters BSIM→PSP is still necessary, see [2].

The local PSP parameters affected by the stress equations are BETN, THESAT, VFB, CF.BETNEDGE,VFBEDGE and CFEDGE.

Calculation of SA and SB for irregular layouts is given in Section B.1.

Note:

• After modification of the local parameters by the stress equations, clipping is applied according to Sec-tion 2.5.2.

• If both SA and SB are set to 0, the stress-equations are not computed.• The stress equations are calculated when SWGEO = 1 or 2.

3.5.1 Layout effects for multi-finger devices

For multi-finger devices, effective values SAeff and SBeff for the instance parameters are calculated (seeFig. 3.3).

1

SAeff + 0.5 · L=

1

NF·

NF−1∑i=0

1

SA + 0.5 · L+ i · (SD + L)(3.278)

1

SBeff + 0.5 · L=

1

NF·

NF−1∑i=0

1

SB + 0.5 · L+ i · (SD + L)(3.279)

3.5.2 Layout effects for regular shapes

RA =1

SAeff + 0.5 · L(3.280)

RB =1

SBeff + 0.5 · L(3.281)

RA,ref =1

SAREF + 0.5 · L(3.282)

RB,ref =1

SBREF + 0.5 · L(3.283)



L

SBSA SD

W

LOD

Figure 3.3: A typical layout of multi-finger devices with an additional instance parameters SD.

Trench isolation edge

L

SA SBW

L OD

Figure 3.4: Typical layout of a MOSFET. Note that LOD = SA + SB + L, where OD is the active regiondefinition.



3.5.3 Parameter modifications

Mobility-related equations

Ku0 =

(1 +

LKUO(L+ ∆LPS)

LLODKUO +WKUO

(Wf + ∆WOD + WLOD)WLODKUO

+PKUO

(L+ ∆LPS)LLODKUO · (Wf + ∆WOD + WLOD)WLODKUO

)

·[1 + TKUO ·

(TKA

TKR− 1

)](3.284)

ρβ =KUOKu0

· (RA +RB) (3.285)

ρβ,ref =KUOKu0

· (RA,ref +RB,ref) (3.286)

BETN =1 + ρβ

1 + ρβ,ref· BETNref (3.287)

THESAT =1 + ρβ

1 + ρβ,ref· 1 + KVSAT · ρβ,ref

1 + KVSAT · ρβ· THESATref (3.288)

BETNEDGE =1 + ρβ

1 + ρβ,ref· BETNEDGEref (3.289)

Threshold-voltage-related equations

Kvth0 = 1 +LKVTHO

(L+ ∆LPS)LLODVTH +

WKVTHO(Wf + ∆WOD + WLOD)

WLODVTH

+PKVTHO

(L+ ∆LPS)LLODVTH · (Wf + ∆WOD + WLOD)WLODVTH (3.290)

∆R = RA +RB −RA,ref −RB,ref (3.291)

VFB = VFBref + KVTHO · ∆R

Kvth0(3.292)

CF = CFref + STETAO · ∆R

KLODETAOvth0

(3.293)

VFBEDGE = VFBEDGEref + KVTHO · ∆R

Kvth0(3.294)

CFEDGE = CFEDGEref + STETAO · ∆R

KLODETAOvth0

(3.295)



3.6 Well proximity effects

The well proximity effect (WPE) model from BSIM4.5.0 [4, 5, 6] has been adopted in PSP with two changesrelative to BSIM4.5.0: (1) in the original BSIM parameter names all zeros have been replaced by ‘O’s in orderto comply with PSP naming convention and (2) the BSIM parameter K2WE is not available in PSP. Except forsome trivial conversion of parameters BSIM→PSP [2], WPE parameters from BSIM can be used directly inPSP.

The local PSP parameters affected by the WPE equations are VFB, BETN, VFBEDGE and BETNEDGE

How to calculate SCA, SCB, and SCC is shown in Section B.2.

Note:

• After modification of the local parameters by the WPE equations, clipping is applied according to Sec-tion 2.5.2.

• If SCA, SCB, SCC and SC are all set to 0, the WPE equations are not computed.• The WPE equations are calculated when SWGEO = 1 or 2.

3.6.1 Parameters for pre-layout simulation

If SCA = SCB = SCC = 0 and SC > 0, SCA, SCB, and SCC will be computed from SC according toEqs. (B.9)–(B.11), as shown below. Here, SC should be taken as the distance to the nearest well edge (see Fig.3.5). If any of the parameters SCA, SCB, or SCC is positive, all three values as supplied will be used and SCwill be ignored.

If SCA = SCB = SCC = 0 and SC > 0

SCA =SCREF2

Wf·(

1

SC− 1

SC +Wf

)(3.296)

SC

L

W

Figure 3.5: A layout of MOS devices for pre-layout simulation using estimated value for SC.



SCB =1

Wf · SCREF·

[SCREF

10· SC · exp

(−10 · SC

SCREF

)+

SCREF2

100· exp

(−10 · SC

SCREF

)

− SCREF10

· (SC +Wf) · exp

(−10 · SC +Wf

SCREF

)

− SCREF2

100· exp

(−10 · SC +Wf

SCREF

)](3.297)

SCC =1

Wf · SCREF·

[SCREF

20· SC · exp

(−20 · SC

SCREF

)+

SCREF2

400· exp

(−20 · SC

SCREF

)

− SCREF20

· (SC +Wf) · exp

(−20 · SC +Wf

SCREF

)

− SCREF2

400· exp

(−20 · SC +Wf

SCREF

)](3.298)

3.6.2 Calculation of parameter modifications

The calculation of Kvthowe and Kuowe is given in Section 3.2 (global model) or 3.3 (binning model).

VFB = VFBref +Kvthowe · (SCA + WEB · SCB + WEC · SCC) (3.299)

BETN = BETNref · [1 +Kuowe · (SCA + WEB · SCB + WEC · SCC)] (3.300)

VFBEDGE = VFBEDGEref +Kvthowe · (SCA + WEB · SCB + WEC · SCC) (3.301)

BETNEDGE = BETNEDGEref · [1 +Kuowe · (SCA + WEB · SCB + WEC · SCC)] (3.302)



3.7 Asymmetric junctions

From PSP 102.3 onwards, asymmetric junction can be modeled in PSP. This includes asymmetric source-bulkand drain-bulk junctions, GIDL/GISL, overlap gate currents, overlap capacitances and outer fringe capaci-tances. The asymmetric junction model can be switched on by means of the parameter SWJUNASYM. Notethat if SWJUNASYM = 1, the new parameters for the drain side are used all together. Those whose valuesare not explicitly specified in the model card are set to their default value, not to their counterparts for thesource side. In other words, it is not possible to activate the parameters for the drain side on a one-by-one basis.The physical scaling and binning rules to calculate the related local parameters for the drain side are given inSection 3.2 and 3.3.

If SWJUNASYM = 0, the related parameters for the drain side are ignored. Effectively, the following assign-ments are applied before evaluation of the calculations described in Section 4.

If SWJUNASYM = 0:

TOXOVD = TOXOV (3.303)

NOVD = NOV (3.304)

AGIDLD = AGIDL (3.305)

BGIDLD = BGIDL (3.306)

STBGIDLD = STBGIDL (3.307)

CGIDLD = CGIDL (3.308)

IGOVD = IGOV (3.309)

CGOVD = CGOV (3.310)

CFRD = CFR (3.311)

RSHD = RSH (3.312)



Section 4

PSP Model Equations

4.1 Internal Parameters (including Temperature Scaling)

In this section, bias-independent internal parameters will be calculated, including temperature scaling. Theseparameters are computed from local parameters. Local parameters are (as usual) denoted by capital charactersin bold font, whereas the internal parameters are denoted by symbols in bold font.

Transistor temperature

TKR = T0 + TR (4.1)

TKA = T0 + TA + DTA (4.2)

TKD = TKA + Vdt (4.3)

∆T = TKD − TKR (4.4)

∆TA = TKA − TKR (4.5)

φT =kB · TKD

q(4.6)

φTA=kB · TKA

q(4.7)

Local process parameters

V FB = VFB + STVFB ·∆T · (1 + ST2VFB ·∆T ) + DELVTO (4.8)

Eg/q = 1.179− 9.025 · 10−5 · TKD − 3.05 · 10−7 · TKD2 (4.9)

rT =(1.045 + 4.5 · 10−4 · TKD

)·(0.523 + 1.4 · 10−3 · TKD − 1.48 · 10−6 · TKD

2)

(4.10)

ni = 2.5 · 1025 · rT3/4 · (TKD/300)

3/2 · exp

(− Eg/q

2 · φT

)(4.11)

φclB,dc = MAX (DPHIB + 2 · φT · ln [NEFF/ni] , 0.05) (4.12)



Neff,ac = MIN[MAX(FACNEFFAC · NEFF, 1020), 1026] (4.13)

φclB,ac = MAX (DPHIB + DELVTAC + 2 · φT · ln [Neff,ac/ni] , 0.05) (4.14)

εox = EPSROX · ε0 (4.15)

Cox = εox/TOX (4.16)

εSi = εr,Si · ε0 (4.17)

γ0,dc =√

2 · q · εSi · NEFF/Cox (4.18)

γ0,ac =√

2 · q · εSi ·Neff,ac/Cox (4.19)

Gcl0,dc = γ0,dc/

√φT (4.20)

Gcl0,ac = γ0,ac/

√φT (4.21)

Interface states parameter

CT = CT · (TKR/TKD)STCT (4.22)

CTG = CTG · (TKD/TKR) (4.23)

Polysilicon depletion parameter

kP =

if NP = 0kP = 0

if NP > 0

NP1 = MAX(NP, 8 · 107/TOX2)

NP2 = MAX(NP1, 5 · 1024)

kP = 2 · φT · C2ox/(q · εSi ·NP2)

(4.24)

Quantum-mechanical correction parameters

qlim = 10 · φT (4.25)

qq =

0.4 ·QMC ·QMN · C

2/3ox for NMOS

0.4 ·QMC ·QMP · C2/3ox for PMOS

(4.26)

qb0,dc = γ0,dc ·√φcl

B,dc (4.27)

qb0,ac = γ0,ac ·√φcl

B,ac (4.28)

φB,dc = φclB,dc + 0.75 · qq · q

2/3b0,dc (4.29)

φB,ac = φclB,ac + 0.75 · qq · q

2/3b0,ac (4.30)

G0,dc = Gcl0,dc ·

(1 + qq · q

−1/3b0,dc

)(4.31)

G0,ac = Gcl0,ac ·

(1 + qq · q

−1/3b0,ac

)(4.32)



VSB-clipping parameters

φX,dc = 0.95 · φB,dc (4.33)

φX,ac = 0.95 · φB,ac (4.34)

aφ,dc = 2.5 · 10−3 · φ2B,dc (4.35)

aφ,ac = 2.5 · 10−3 · φ2B,ac (4.36)

bφ,dc = 2.5 · 10−3 · φ2B,dc (4.37)

bφ,ac = 2.5 · 10−3 · φ2B,ac (4.38)

φ*X,dc = MINA

(φX,dc − 0.5 ·

√bφ,dc, 0, aφ,dc

)(4.39)

φ*X,ac = MINA

(φX,ac − 0.5 ·

√bφ,ac, 0, aφ,ac

)(4.40)

NUD parameters

us1 =√

VSBNUD + φB,dc −√φB,dc (4.41)

us21 =√

DVSBNUD + φB,dc −√φB,dc − us1 (4.42)

Local process parameters in gate overlap regions

γov =√

2 · q · εSi · NOV · TOXOV/εox (4.43)

γdov =√

2 · q · εSi · NOVD · TOXOVD/εox (4.44)

Gov = γov/√φT (4.45)

Gdov = γdov/√φT (4.46)

εov = 3.1 ·Gov + 8.5 (4.47)

aov =

64/Gov for 1/Gov < 0.06

22/Gov + 3 for 0.06 ≤ 1/Gov ≤ 0.45

−7.2/Gov + 15.5 for 0.45 < 1/Gov ≤ 1.6

Gov for 1/Gov > 1.6

(4.48)

δov =εov

2+G2

ov2−Gov ·

√εov

2+G2

ov4

+ aov (4.49)

εdov = 3.1 ·Gdov + 8.5 (4.50)



adov =

64/Gdov for 1/Gdov < 0.06

22/Gdov + 3 for 0.06 ≤ 1/Gdov ≤ 0.45

−7.2/Gdov + 15.5 for 0.45 < 1/Gdov ≤ 1.6

Gdov for 1/Gdov > 1.6

(4.51)

δdov =εdov

2+G2

dov2−Gdov ·

√εdov

2+G2

dov4

+ adov (4.52)

Mobility parameters

β = FACTUO · BETN · Cox · (TKR/TKD)STBET (4.53)

θµ = THEMU · (TKR/TKD)STTHEMU (4.54)

µE = MUE · (TKR/TKD)STMUE (4.55)

Xcor = XCOR · (TKR/TKD)STXCOR (4.56)

CS = CS · (TKR/TKD)STCS (4.57)

θcs = THECS · (TKR/TKD)STTHECS (4.58)

Eeff0 = 10−8 · Cox/εSi (4.59)

ηµ =

1/2 · FETA for NMOS

1/3 · FETA for PMOS

(4.60)

ηµ,ac =

1/2 for NMOS

1/3 for PMOS

(4.61)

Series resistance parameter

Rs = RS · (TKR/TKD)STRS (4.62)

θR = 2 · β ·Rs (4.63)

Velocity saturation parameter

θsat = THESAT · (TKR/TKD)STTHESAT (4.64)

Gate current parameters

IGINV = IGINV · (TKA/TKR)STIG (4.65)

IGOV = IGOV · (TKA/TKR)STIG (4.66)



IGOVD = IGOVD · (TKA/TKR)STIG (4.67)

B =4

3· TOX

~·√

2 · q ·m0 · CHIB = 6.830909 · 109 · TOX ·√

CHIB (4.68)

Bov = B · TOXOV/TOX (4.69)

Bovd = B · TOXOVD/TOX (4.70)

GCQ =

−0.99 · GC2

2 ·GC3for GC3 < 0

0 for GC3 ≥ 0

(4.71)

αb =Eg/q + φB,dc

2(4.72)

Gate-induced drain leakage parameters

AGIDL = AGIDL ·(

2 · 10−9

TOXOV

)2

(4.73)

AGIDLD = AGIDLD ·(

2 · 10−9

TOXOVD

)2

(4.74)

BGIDL = BGIDL ·MAX ([1 + STBGIDL ·∆TA] , 0) ·(

TOXOV2 · 10−9

)(4.75)

BGIDLD = BGIDLD ·MAX ([1 + STBGIDLD ·∆TA] , 0) ·(

TOXOVD2 · 10−9

)(4.76)

Noise parameter

NT = FNT · 4 · kB · TKD (4.77)


V FB,edge = VFBEDGE + STVFBEDGE ·∆T + DELVTOEDGE (4.78)

βedge = FACTUOEDGE · BETNEDGE · Cox · (TKR/TKD)STBETEDGE (4.79)

φ∗T0,edge = φT ·(

1 + CTEDGE · TKR

TKD

)(4.80)

φB,edge = MAX(DPHIBEDGE + 2 · φ∗T0,edge · ln [NEFFEDGE/ni] , 0.05

)(4.81)

γedge =√

2 · q · εSi · NEFFEDGE/Cox (4.82)

Gedge = γedge/√φT (4.83)

φX,edge = 0.95 · φB,edge (4.84)



aφ,edge = 2.5 · 10−3 · φ2B,edge (4.85)

bφ,edge = 2.5 · 10−3 · φ2B,edge (4.86)

φ∗X,edge = MINA

(φX,edge −

√bφ,edge

2, 0, aφ,edge

)(4.87)

NT,edge = FNTEDGE · 4 · kB · TKD (4.88)

Impact-ionization parameter

a2 = A2 · (TKD/TKR)STA2 (4.89)

Self heating

RTH = RTH ·(TKA

·TKR

)STRTH

(4.90)

Additional internal parameters

x1 = 1.25 (4.91)



4.2 Current Model

In this section, the current model equations of the PSP-model are given. Use is made of the applied termi-nal bias values VGS, VDS and VSB, the local parameters listed in Section 2.5.2 and the internal parametersintroduced in Section 4.1. Local parameters are denoted by capital characters in bold font, whereas internal(bias-independent) parameters are denoted by symbols in bold font.

The definitions of the auxiliary functions MINA(.), MAXA(.), χ(.) and σ1,2(.) can be found in Appendix A.

Depending on the value of the parameters SWNUD and SWDELVTAC, the surface potential (at source- anddrain-side of the channel) and associated computations, i.e., Eqs. (4.103)–(4.202), may be evaluated twice:once for the dc-characteristics and a second time for the ac-characteristics of the model. Details are givenbelow.

4.2.1 Conditioning of Terminal Voltages

Vdsx =V 2

DS√VDS

2 + 0.01 + 0.1(4.92)

φV,dc = MINA (VSB, VSB + VDS, bφ,dc) + φX,dc (4.93)

φV,ac = MINA (VSB, VSB + VDS, bφ,ac) + φX,ac (4.94)

V ∗SB,dc = VSB −MINA (φV,dc, 0, aφ,dc) + φ*X,dc (4.95)

V ∗SB,ac = VSB −MINA (φV,ac, 0, aφ,ac) + φ*X,ac (4.96)

Nonuniform doping effect. Eqs. (4.97)–(4.102) are only evaluated when SWNUD 6= 0 and GFACNUD 6= 1:

VmB = V ∗SB + 0.5 · (VDS − Vdsx) (4.97)

us =√VmB + φB −

√φB (4.98)

p = 2 · us − us1

us21− 1 (4.99)

us,nud = us − 0.25 · (1−GFACNUD) · us21 ·p+

√p2 + [ln(2)]

2

(4.100)

VmB,nud =(us,nud + 2 ·

√φB

)· us,nud (4.101)

V ∗SB,dc = VmB,nud − 0.5 · (VDS − Vdsx) (4.102)

The surface potential (at source- and drain-side of the channel) and associated computations, i.e., Eqs. (4.103)–(4.202), are evaluated using V ∗SB = V ∗SB,dc, φB = φB,dc, andG0 = G0,dc.

If SWNUD = 1 or SWDELVTAC = 1, Eqs. (4.103)–(4.202) are evaluated a second time using V ∗SB = V ∗SB,ac,φB = φB,ac, andG0 = G0,ac.

V ∗DB = VDS + V ∗SB (4.103)

Vsbx = V ∗SB +VDS − Vdsx

2(4.104)



4.2.2 Short Channel effects

Drain-induced barrier lowering:

V ∗ds =

Vdsx for CFD < 10−10

2 ·(√

1.0 + CFD · Vdsx − 1)/CFD for CFD ≥ 10−10

(4.105)

∆VG = CF · V ∗dsx · (1 + CFB · Vsbx) (4.106)

V ∗GB = VGS + V ∗SB + ∆VG − V FB (4.107)

Subthreshold slope degradation induced by short channel effects:

nSCE = 1 + PSCE · (1 + PSCED · Vdsx) · (1 + PSCEB · Vsbx) (4.108)

4.2.3 Bias-Dependent Body Factor

Dnsub = DNSUB ·MAXA(0, VGS + VSB − VNSUB, NSLP

)(4.109)

G = G0 ·√

1 +Dnsub (4.110)

4.2.4 Interface States Including Bias Dependences

xg,ct = V ∗GB/φT (4.111)

xs0,ct =1

2·(G2 + 2 · xg,ct −G ·

√MAXA ((G2 + 4 · xg,ct) , 0, 5)

)(4.112)

xb,ct =φB + Vsbx

φT(4.113)

xs,ct = MINA (xs0,ct, (xb,ct + 2) , 5) (4.114)

CT,eff = CT · exp

(CTG ·

(xs,ct − (1 + CTB) ·

(xb,ct −

φB2 · φT

)))(4.115)

φ∗T = φT · nSCE · (1 + CT,eff) (4.116)

xg = V ∗GB/φ∗T (4.117)

4.2.5 Surface Potential at Source Side and Related Variables

ξ = 1 +G/√

2 (4.118)

xns =φB + V ∗SB

φ∗T(4.119)

∆ns = exp (−xns) (4.120)

xmrg = 10−5 · ξ (4.121)



if xg < −xmrg

yg = −xg

z = 1.25 · yg/ξ

η =[z + 10−

√(z − 6)2 + 64

]/2

a = (yg − η)2

+G2 · (η + 1)

c = 2 · (yg − η)−G2

τ = −η + ln(a/G2

)y0 = σ1(a, c, τ, η)

∆0 = exp (y0)

p = 2 · (yg − y0) +G2 · [∆0 − 1 + ∆ns · (1− χ′(y0)− 1/∆0)]

q = (yg − y0)2

+G2 · [y0 −∆0 + 1 + ∆ns · (1 + χ(y0)− 1/∆0 − 2 · y0)]

xs = −y0 −2 · q

p+√p2 − 2 · q · 2−G2 · [∆0 + ∆ns · (1/∆0 − χ′′(y0))]

(4.122)

if |xg| ≤ xmrg

xs =

xg

ξ·[1 +G · xg ·

1−∆ns

ξ2 · 6 ·√

2

](4.123)

if xg > xmrg

xg1 = x1 +G ·√

exp(−x1) + x1 − 1

x =xg

ξ·[1 + xg · (ξ · x1 − xg1)/x2

g1

]x0 = xg +G2/2−G ·

√xg +G2/4− 1 + exp(−x)

bx = xns + 3

η = MINA(x0, bx, 5)−(bx −

√b2x + 5

)/2

a = (xg − η)2 −G2 · [exp(−η) + η − 1−∆ns · (η + 1 + χ(η))]

b = 1−G2/2 · [exp(−η)−∆ns · χ′′(η)]

c = 2 · (xg − η) +G2 · [1− exp(−η)−∆ns · (1 + χ′(η))]

τ = xns − η + ln(a/G2

)y0 = σ2(a, b, c, τ, η)

∆0 = exp (y0)

p = 2 · (xg − y0) +G2 · [1− 1/∆0 + ∆ns · (∆0 − 1− χ′(y0))]

q = (xg − y0)2 −G2 · [y0 + 1/∆0 − 1 + ∆ns · (∆0 − y0 − 1− χ(y0))]

xs = y0 +2 · q

p+√p2 − 2 · q · 2−G2 · [1/∆0 + ∆ns · (∆0 − χ′′(y0))]

(4.124)

Eqs. (4.125)-(4.127) are only calculated for xg > 0.

Es = exp (−xs) (4.125)



Ds = [1/Es − xs − 1− χ(xs)] ·∆ns (4.126)

Ps = xs − 1 + Es (4.127)

xgs =

xg − xs for xg ≤ 0

G ·√Ds + Ps for xg > 0

(4.128)

ψss = φ∗T · xs (4.129)

4.2.6 Drain Saturation Voltage


qis =G2 · φ∗T ·Ds

xgs +G ·√Ps

(4.130)

αs = 1 +G · (1− Es)

2 ·√Ps

(4.131)

qbs = φ∗T ·G ·√Ps (4.132)

ρb =

1 + RSB · Vsbx for RSB ≥ 0

1

1− RSB · Vsbxfor RSB < 0

(4.133)

ρg,s =

1

1 + RSG · qisfor RSG ≥ 0

1− RSG · qis for RSG < 0

(4.134)

ρs = θR · ρb · ρg,s · qis (4.135)

µx =1 +Xcor · Vsbx

1 + 0.2 ·Xcor · Vsbx(4.136)

Eeff,s = Eeff0 ·(qbs + ηµ · qis

)(4.137)

Gmob,s =

1 + (µE · Eeff,s)θµ +CS ·

(qbs

qis + qbs

)θcs+ ρs

µx(4.138)

ξtb =

1 + THESATB · Vsbx for THESATB ≥ 0

1

1− THESATB · Vsbxfor THESATB < 0

(4.139)

wsat,s =100 · qis · ξtb100 + qis · ξtb

(4.140)



θ∗sat,s =

θsat

Gmob,s· (1 + THESATG · wsat,s) for THESATG ≥ 0

θsat

Gmob,s· 1

1− THESATG · wsat,sfor THESATG < 0

(4.141)

φ∞ = qis/αs + φ∗T (4.142)

ysat =

θ∗sat,s · φ∞/

√2 for NMOS

θ∗sat,s · φ∞/√

2√1 + θ∗sat,s · φ∞/

√2

for PMOS(4.143)

za =2

1 +√

1 + 4 · ysat(4.144)

φ0 = φ∞ · za ·[1 + 0.86 · za · ysat ·

1− z2a · ysat

1 + 4 · z3a · y2

sat

](4.145)

asat = xgs +G2/2 (4.146)

φ2 =φ∗T · 0.98 ·G2 ·Ds

asat +√a2

sat − 0.98 ·G2 ·Ds

(4.147)

φsat =2 · φ0 · φ2

φ0 + φ2 +

√(φ0 + φ2)

2 − 3.96 · φ0 · φ2

(4.148)

Vdsat = φsat − φ∗T · ln

[1 +

φsat · (φsat − 2 · asat · φ∗T)

G2 ·Ds · φ∗T2

](4.149)

Vdse =VDS[

1 + (VDS/Vdsat)AX]1/AX (4.150)

4.2.7 Surface Potential at Drain Side and Related Variables


xnd =φB + V ∗SB + Vdse

φ∗T(4.151)

kds = exp (−Vdse/φ∗T) (4.152)

∆nd = ∆ns · kds (4.153)

if xg ≤ xmrg

xd =

xg

ξ·[1 +G · xg ·

1−∆nd

ξ2 · 6 ·√

2

](4.154)



if xg > xmrg

bx = xnd + 3.0

η = MINA(x0, bx, 5)−(bx −

√b2x + 5

)/2

a = (xg − η)2 −G2 · [exp(−η) + η − 1−∆nd · (η + 1 + χ(η))]

b = 1−G2/2 · [exp(−η)−∆nd · χ′′(η)]

c = 2 · (xg − η) +G2 · [1− exp(−η)−∆nd · (1 + χ′(η))]

τ = xnd − η + ln(a/G2

)y0 = σ2(a, b, c, τ, η)

∆0 = exp (y0)

p = 2 · (xg − y0) +G2 · [1− 1/∆0 + ∆nd · (∆0 − 1− χ′(y0))]

q = (xg − y0)2 −G2 · [y0 + 1/∆0 − 1 + ∆nd · (∆0 − y0 − 1− χ(y0))]

xd = y0 +2 · q

p+√p2 − 2 · q · 2−G2 · [1/∆0 + ∆nd · (∆0 − χ′′(y0))]

(4.155)

xds = xd − xs (4.156)

if xds < 10−10

p = 2 · xgs +G2 · [1− Es + ∆nd · (1/Es − 1− χ′(xs))]

q = G2 · (1− kds) ·Ds

ξ = 1−G2/2 · [Es + ∆nd (1/Es − χ′′(xs))]

xds =2 · q

p+√p2 − 4 · ξ · q

xd = xs + xds

(4.157)

Ed = exp (−xd) (4.158)

Dd = (1/Ed − xd − 1− χ(xd)) ·∆nd (4.159)

∆ψ = φ∗T · xds (4.160)

ψsd = φ∗T · xd (4.161)

4.2.8 Mid-Point Surface Potential and Related Variables

if xg > 0

xm = (xs + xd) /2

Em =√Es · Ed

D = (Ds +Dd) /2

Dm = D + x2ds/8 ·

(Em − 2/G2

)Pm = xm − 1 + Em

xgm = G ·√Dm + Pm

(4.162)



if xg ≤ 0

xm = xs

xgm = xg − xs

(4.163)

4.2.9 Polysilicon Depletion

Eqs. (4.164)-(4.178) are only calculated for kP > 0 and xg > 0 (otherwise ηp = 1):

x(0)m = xm, x

(0)ds = xds, D(0)

m = Dm, E(0)m = Em, (4.164)

d0 = 1− E(0)m + 2 · xgm/G

2 (4.165)

ηp = 1/√

1 + kP · xgm (4.166)

xpm = kP ·[ηp · xgm

1 + ηp

]2

· D(0)m

D(0)m + Pm

(4.167)

p = 2 · (xgm − xpm) +G2 ·(

1− E(0)m +D(0)

m

)(4.168)

q = xpm · (xpm − 2 · xgm) (4.169)

ξp = 1−G2/2 ·(E(0)

m +D(0)m

)(4.170)

up =p · q

p2 − ξp · q(4.171)

xm = x(0)m + up (4.172)

Em = E(0)m · exp (−up) (4.173)

Dm = D(0)m · exp (up) (4.174)

Pm = xm − 1 + Em (4.175)

xgm = G ·√Dm + Pm (4.176)

xds = x(0)ds ·

exp (up) ·[D + d0

]1− Em + 2 · xgm · ηp/G2 + exp (up) · D

(4.177)

∆ψ = φ∗T · xds (4.178)

4.2.10 Potential Mid-Point Inversion Charge and Related Variables


qim =G2 · φ∗T ·Dm

xgm +G ·√Pm

(4.179)

αm = ηp +G · (1− Em)

2 ·√Pm

(4.180)



q∗im = qim + φ∗T · αm (4.181)

qbm = φ∗T ·G ·√Pm (4.182)

Series resistance:

ρg =

1

1 + RSG · qimfor RSG ≥ 0

1− RSG · qim for RSG < 0

(4.183)

ρs = θR · ρb · ρg · qim (4.184)

Mobility reduction:

Eeff = Eeff0 ·(qbm + ηµ · qim

)(4.185)

qeff1 = qbm + ηµ,ac · qim (4.186)

Gmob =1 + (µE · Eeff)

θµ +CS ·(

qbmqim+qbm

)θµ+ ρ

µx(4.187)

4.2.11 Drain-Source Channel Current

Eqs. (4.188)-(4.199) are only calculated for xg > 0:

Channel length modulation:

R1 = qim/q∗im (4.188)

R2 = φ∗T · αm/q∗im (4.189)

T1 = ln

1 +VDS −∆ψ

VP

1 +Vdse −∆ψ

VP

(4.190)

T2 = ln

(1 +

Vdsx

VP

)(4.191)

∆L/L = ALP · T1 (4.192)

G∆L =1

1 + ∆L/L+ (∆L/L)2(4.193)

∆L1/L =

[ALP +

ALP1q∗im

·R1

]· T1 + ALP2 · qbm ·R2

2 · T2 (4.194)

F∆L =[1 + ∆L1/L+ (∆L1/L)2

]·G∆L (4.195)

Velocity saturation:

wsat =100 · qim · ξtb100 + qim · ξtb

(4.196)



θ∗sat =

θsat

Gmob,s ·G∆L· (1 + THESATG · wsat) for THESATG ≥ 0

θsat

Gmob,s ·G∆L· 1

1− THESATG · wsatfor THESATG < 0

(4.197)

zsat =

(θ∗sat ·∆ψ)

2 for NMOS

(θ∗sat ·∆ψ)2

1 + θ∗sat ·∆ψfor PMOS

(4.198)

Gvsat =Gmob ·G∆L

2·(1 +√

1 + 2 · zsat

)(4.199)

Auxiliary Variables for Calculation of Intrinsic Charges and Gate Current. Eqs. (4.200)-(4.202) are only calcu-lated for xg > 0.

Voxm = φ∗T · xgm (4.200)

α′m = αm ·

[1 +

zsat

2·(Gmob ·G∆L

Gvsat

)2]

(4.201)

H =Gmob ·G∆L

Gvsat· q∗im

α′m(4.202)

In the remainder of this document, some variables (e.g., xg) are labeled ’dc’ or ’ac’ (e.g., xg,dc or xg,ac).Variables labeled ‘dc’ result from the first evaluation of Eqs. (4.103)–(4.202). For variables labeled ’ac’, thereare two possibilities. If SWNUD = 1 or SWDELVTAC = 1, their values result from the second evaluation ofEqs. (4.103)–(4.202). In any other case, their value is equal to their ’dc’-counterpart.This applies to the following variables: xg, qeff1, Voxm, qim, q∗im, αm , ∆ψ, G∆L, F∆L, H , ηp, Gvsat, Vdse,Gmob, xm, G, xgm, θ∗sat.

Drain-Source channel current:

IDS =

0 for xg,dc ≤ 0

β · F∆L,dc ·q∗im,dc

Gvsat,dc·∆ψdc for xg,dc > 0

(4.203)

4.2.12 Surface Potential in Gate Overlap Regions

xsov (xg) =

x′g =

(xg +

√x2

g + ε2ov

)/2

xsov = −x′g −G2ov/2 +Gov ·

√x′g +G2

ov/4 + aov + δov

(4.204)

xdov (xg) =

x′g =

(xg +

√x2

g + ε2dov

)/2

xdov = −x′g −G2dov/2 +Gdov ·

√x′g +G2

dov/4 + adov + δdov

(4.205)

ψsov = −φTA· xsov

(−VGS

φTA

)(4.206)



ψdov = −φTA· xdov

(−VGS − VDS

φTA

)(4.207)

Vov0 = VGS − ψsov (4.208)

VovL= VGS − VDS − ψdov (4.209)

4.2.13 Gate Current

The equations in this Section are only calculated when SWIGATE = 1.

Source/Drain gate overlap current:

IGSov(VGX, ψov, Vov) =

V ∗ov =√V 2

ov + 10−6

zg =

MINA

(V ∗ov

CHIB, GCQ, 10−6

)for GC3 < 0

V ∗ov

CHIBfor GC3 ≥ 0

FS1 =3.0 · φTA

+ ψov

φTA

FS2 = −3.0−GCO

FS3 = 30 · VGX

FSov = MXE (FS2, MNE (FS1, FS3, 0.9) , 0.3)

IGov = IGOV · FSov·

exp

(Bov ·

[−3

2+ zg · (GC2 + GC3 · zg)

])

(4.210)

IGDov(VGX, ψov, Vov) =

V ∗ov =√V 2

ov + 10−6

zg =

MINA

(V ∗ov

CHIB, GCQ, 10−6

)for GC3 < 0

V ∗ov

CHIBfor GC3 ≥ 0

FS1 =3.0 · φTA

+ ψov

φTA

FS2 = −3.0−GCO

FS3 = 30 · VGX

FSov = MXE (FS2, MNE (FS1, FS3, 0.9) , 0.3)

IGov = IGOVD · FSov·

exp

(Bovd ·

[−3

2+ zg · (GC2 + GC3 · zg)

])

(4.211)

IGSov = IGSov (VGS, ψsov, Vov0) (4.212)



IGDov = IGDov (VGS − VDS , ψdov, VovL) (4.213)

Gate-channel current:

Vm = V ∗SB,dc + φ∗T ·[xds,dc

2− ln

(1 + exp(xds,dc − Vdse,dc/φ

∗T

2

)](4.214)

Dch = GCO · φ∗T (4.215)

ψt = MINA (0, Voxm,dc +Dch, 0.01) (4.216)

V ∗oxm =√V 2

oxm,dc + 10−6 (4.217)

zg =

MINA

(V ∗oxm

CHIB, GCQ, 10−6

)for GC3 < 0

V ∗oxm

CHIBfor GC3 ≥ 0

(4.218)

∆Si = exp

(xm,dc −

αb + Vm − ψt

φ∗T

)(4.219)

FS = ln

1 + ∆Si

1 + ∆Si · exp

(−VGS + V ∗SB,dc − Vm

φ∗T

) (4.220)

IGCO = IGINV · FS · exp (B · [−3/2 + zg · (GC2 + GC3 · zg)]) (4.221)

if xg,dc > 0

u0 = CHIB/ [B · (GC2 + 2 ·GC3 · zg)]

x = ∆ψdc/ (2 · u0)

b = u0/Hdc

Bg = b · (1− b) /2

Ag = 1/2− 3 ·Bg

pgc = (1− b) · sinh(x)

x+ b · cosh(x)

pgd =pgc

2−Bg · sinh(x)−Ag ·

sinh(x)

x·[coth(x)− 1

x

]

(4.222)

if xg,dc ≤ 0

pgc = 1

pgd = 1/2(4.223)

Sg =1

2·

1 +xg,dc√

x2g,dc + 10−6

(4.224)

IGC = IGCO · pgc · Sg (4.225)



IGCD = IGCO · pgd · Sg (4.226)

IGCS = IGC − IGCD (4.227)

IGB = IGCO · pgc · (1− Sg) (4.228)

4.2.14 Gate-Induced Drain/Source Leakage Current

The equations in this section are only calculated when SWGIDL = 1.

Igisl(Vov, V ) =

Vtov =√V 2

ov + CGIDL2 · V 2 + 10−6

t = V · Vtov · Vov

Igisl =

−AGIDL · t · exp

(−BGIDL

Vtov

)for Vov < 0

0 for Vov ≥ 0

(4.229)

Igidl(Vov, V ) =

Vtov =√V 2

ov + CGIDLD2 · V 2 + 10−6

t = V · Vtov · Vov

Igidl =

−AGIDLD · t · exp

(−BGIDLD

Vtov

)for Vov < 0

0 for Vov ≥ 0

(4.230)

Igisl = Igisl(Vov0, VSB) (4.231)

Igidl = Igidl(VovL, VDS + VSB) (4.232)

4.2.15 Edge Transistor Current

The equations in this Section are only calculated when SWEDGE = 1 and BETNEDGE > 0.

φV,edge = MINA (VSB, VSB + VDS, bφ,edge) + φX,edge (4.233)

V ∗SB,edge = VSB −MINA (φV,edge, 0, aφ,edge) + φ∗X,edge (4.234)

Vsbx,edge = V ∗SB,edge + 0.5 · (VDS − Vdsx) (4.235)

nSCE,edge = 1 + PSCEEDGE · (1 + PSCEDEDGE · Vdsx) · (1 + PSCEBEDGE · Vsbx,edge) (4.236)

φ∗T,edge = φ∗T0,edge · nSCE,edge (4.237)

V ∗ds,edge =

Vdsx for CFDEDGE < 10−10

2 ·(√

1.0 + CFDEDGE · Vdsx − 1)/CFDEDGE for CFDEDGE ≥ 10−10

(4.238)

∆VG,edge = CFEDGE · V ∗ds,edge · (1 + CFBEDGE · Vsbx,edge) (4.239)



V ∗GB,edge = VGS + V ∗SB,edge + ∆VG,edge − V FB,edge (4.240)

xg,edge = V ∗GB,edge/φ∗T,edge (4.241)

xb,edge = φB,edge/φ∗T,edge (4.242)

∆xth,edge = 2 · ln(xb,edge

Gedge+√xb,edge

)(4.243)

Inversion charge at the source side:

xn,edge,s = V ∗SB,edge/φ∗T,edge (4.244)

xsth,edge,s = xb,edge + xn,edge,s

xth0,edge,s = xsth,edge,s +Gedge ·√xsth,edge,s

xth,edge,s = xth0,edge,s + ∆xth,edge

nedge,s = 1 +Gedge

2·√xsth,edge,s

xgt,edge,s = xg,edge − xth,edge,s

xgt0,edge,s = xgt,edge,s + ln(G2

edge)− 1

x∗gt0,edge,s = 12 ·(xgt0,edge,s +

√x2

gt0,edge,s + 10)

qi0si,edge,s = xgt,edge,s − nedge,s · ln(x∗gt0,edge,s

)+ ln

(G2

edge)

qi0,edge,s = 12 ·(qi0si,edge,s +

√q2i0si,edge,s + 2

)∆0,edge,s =

(G2

edge · exp (xgt,edge,s − qi0,edge,s))1/nedge,s

qieff,edge,s = qi0,edge,s − nedge,s·(√n2edge,s+(2·(qi0,edge,s+nedge,s)−∆0,edge,s)·∆0,edge,s−nedge,s

∆0,edge,s− 1

)

(4.245)

Inversion charge at the drain side:

xn,edge,d =(Vdse + V ∗SB,edge

)/φ∗T,edge (4.246)

if qieff,edge,s < 10−3 and Vdse < 10−6

qieff,edge,ds = qieff,edge,s · (exp (xn,edge,s − xn,edge,d)− 1)

qieff,edge,d = qieff,edge,ds + qieff,edge,s

(4.247)



else

xsth,edge,d = xb,edge + xn,edge,d

xth0,edge,d = xsth,edge,d +Gedge ·√xsth,edge,d

xth,edge,d = xth0,edge,d + ∆xth,edge

nedge,d = 1 +Gedge

2·√xsth,edge,d

xgt,edge,d = xg,edge − xth,edge,d

xgt0,edge,d = xgt,edge,d + ln(G2

edge)− 1

x∗gt0,edge,d = 12 ·(xgt0,edge,d +

√x2

gt0,edge,d + 10)

qi0si,edge,d = xgt,edge,d − nedge,d · ln(x∗gt0,edge,d

)+ ln

(G2

edge)

qi0,edge,d = 12 ·(qi0si,edge,d +

√q2i0si,edge,d + 2

)∆0,edge,d =

(G2

edge · exp (xgt,edge,d − qi0,edge,d))1/nedge,d

qieff,edge,d = qi0,edge,d − nedge,d·(√n2edge,d+(2·(qi0,edge,d+nedge,d)−∆0,edge,d)·∆0,edge,d−nedge,d

∆0,edge,d− 1

)

(4.248)

Drain to source current:

qieff,edge,ds = qieff,edge,d − qieff,edge,s (4.249)

qieff,edge,m =qieff,edge,d + qieff,edge,s

2(4.250)

αmb,edge = 1− 1

2· Gedge√

xg,edge − qieff,edge,m + 14 ·G

2edge

(4.251)

IDS,edge = −βedge · φ∗2T,edge

Gmob· (αmb,edge · qieff,edge,m + 1) · qieff,edge,ds (4.252)

4.2.16 Impact Ionization or Weak-Avalanche

The equations in this Section are only calculated when SWIMPACT = 1 and xg > 0.

a∗2 = a2 ·[1 + A4 ·

(√V ∗SB,dc + φB −

√φB

)](4.253)

∆Vsat = VDS − A3 ·∆ψdc (4.254)

Mavl =

0 for ∆Vsat ≤ 0

A1 ·∆Vsat · exp

(− a∗2

∆Vsat

)for ∆Vsat > 0

(4.255)

Iavl = Mavl · (IDS + IDS,edge) (4.256)



4.2.17 Total Terminal Currents

ID = IDS + IDS,edge + Iavl − IGDov − IGCD + Igidl (4.257)

IS = −IDS − IDS,edge − IGSov − IGCS + Igisl (4.258)

IG = IGC + IGB + IGDov + IGSov (4.259)

IB = −Iavl − IGB − Igidl − Igisl (4.260)



4.3 Charge Model

In this section, the charge model equations of the PSP-model are given. Use is made of the applied termi-nal bias values VGS, VDS and VSB, the local parameters listed in Section 2.5.2 and the internal parametersintroduced in Section 4.1. Local parameters are denoted by capital characters in bold font, whereas internal(bias-independent) parameters are denoted by symbols in bold font.

The definitions of the auxiliary functions MINA(.), MAXA(.), χ(.) and σ1,2(.) can be found in Appendix A.

4.3.1 Quantum-Mechanical Corrections

qeff,ac =

Voxm,ac for xg,ac ≤ 0

qeff1,ac for xg,ac > 0

(4.261)

CqmOX =

COX for qq = 0

COX1 + qq/(qeff,ac

2 + qlim2)1/6

for qq > 0

(4.262)

4.3.2 Intrinsic Charge Model

if xg > 0

Fj = ∆ψac/ (2 ·Hac)

q∆L = (1−G∆L,ac) · (qim,ac − αm,ac ·∆ψac/2)

q∗∆L = q∆L,ac · (1 +G∆L,ac)

Q(i)G = Cqm

OX ·[Voxm,ac +

ηp,ac ·∆ψac

2·(G∆L,ac

3· Fj +G∆L,ac − 1

)]

Q(i)I = −Cqm

OX ·[G∆L,ac ·

(qim,ac +

αm,ac ·∆ψac

6· Fj

)+ q∆L,ac

]

Q(i)D = −

CqmOX

2·

[G2

∆L,ac ·

(qim,ac +

αm,ac ·∆ψac

6·

[F 2

j

5+ Fj − 1

])+ q∗∆L

]

(4.263)

if xg ≤ 0

Q

(i)G = Cqm

OX · Voxm,ac

Q(i)I = 0

Q(i)D = 0

(4.264)

Q(i)S = Q

(i)I −Q

(i)D (4.265)

Q(i)B = −Q(i)

I −Q(i)G (4.266)

4.3.3 Extrinsic Charge Model

The charges of the source and drain overlap regions:

Qsov = CGOV · (VGS − ψsov) (4.267)



Qdov = CGOVD · (VGS − VDS − ψdov) (4.268)

The charge of the bulk overlap region

Qbov = CGBOV · (VGS + VSB) (4.269)

Outer fringe charge:

Qofs = CFR · VGS (4.270)

Qofd = CFRD · (VGS − VDS) (4.271)

4.3.4 Total Terminal Charges

QG = Q(i)G +Qsov +Qdov +Qofs +Qofd +Qbov (4.272)

QS = Q(i)S −Qsov −Qofs (4.273)

QD = Q(i)D −Qdov −Qofd (4.274)

QB = Q(i)B −Qbov (4.275)



4.4 Noise Model

Eqs. (4.312)-(4.302) are only calculated for xg > 0. In these equations fop represents the operation frequencyof the transistor and j =

√−1.

4.4.1 Flicker noise

N∗ =Cox

q· αm,dc · φT (4.276)

N∗m =Cox

q· q∗im,dc (4.277)

∆N =Cox

q· αm,dc ·∆ψdc (4.278)

Sfl =q · φ2

T · β · IDS

(fop)EF · Cox ·Gvsat,dc ·N∗

·

[(NFA− NFB ·N∗ + NFC ·N∗ 2) · ln

(N∗m + ∆N/2

N∗m −∆N/2

)

+(

NFB + NFC · [N∗m − 2 ·N∗])·∆N

](4.279)

4.4.2 Thermal noise

Intrinsic thermal noise

H0 =q∗im,dc

αm,dc(4.280)

t1 =qim,dc

q∗im,dc

(4.281)

t2 =

(∆ψdc

12 ·H0

)2

(4.282)

R =H0

H− 1 (4.283)

lc = 1− 12 · t2 ·R (4.284)

gideal =β · q∗im,dc

Gvsat,dc· F∆L,dc (4.285)

CGeff =

(Gvsat,ac

Gmob,ac ·G∆L,ac

)2

· CqmOX · ηp,ac (4.286)

mid,int =gideal

l2c· [t1 + 12 · t2 − 24 · (1 + t1) · t2 ·R] (4.287)

mig,int =1

l2c · gideal·[t112− t2 ·

(t1 +

1

5− 12 · t2

)− 8

5· t2 · (t1 + 1− 12 · t2) ·R

](4.288)

migid,int =

√t2l2c·[1− 12 · t2 −

(t1 +

96

5· t2 − 12 · t1 · t2

)·R]

(4.289)



Excess thermal noise

For short (sub-100-nm) devices, it has been shown that the conventional local source for thermal noise gets afield dependent extra term [7, 8] and changes from

〈i2n〉 = 4 · k · T · g

to

〈i2n〉 = 4 · k · T · g ·[1 + 3 · (q · E · τ)2

m∗ · k · T

]= 4 · k · T · g + 12 · g ·m∗ · µ2 · E2.

Here, g denotes the local channel conductance. Integration along the channel (following the improved Klaassen-Prins method) leads to expressions for the drain-current noise, induced gate noise, and correlation.

Excess thermal noise equations:

θ∗sat,exc =

θsat

Gmob,dc· (1 + THESATG · wsat) for THESATG ≥ 0

θsat

Gmob,dc· 1

1− THESATG · wsatfor THESATG < 0

(4.290)

zsat,exc =

(θ∗sat,exc ·∆ψdc

)2for NMOS

(θ∗sat,exc ·∆ψdc

)21 + θ∗sat,exc ·∆ψdc

for PMOS

(4.291)

Gvsat,exc =Gmob,dc

2·(1 +

√1 + 2 · zsat,exc

)(4.292)

gfac =Gmob,dc

Gvsat,exc · lc(4.293)

mid,exc =FNTEXC ·m0

4 · kB · TKD· g2

fac · IDS · Vdse,dc (4.294)

mig,exc = mid,exc ·1 + 12 · t212 · g2

ideal

(4.295)

migid,exc = −mid,exc ·√t2 · (1 +R)

gideal(4.296)

Total thermal noise

mid = mid,int +mid,exc (4.297)

mig = mig,int +mig,exc (4.298)

migid = migid,int +migid,exc (4.299)

Sid = NT ·mid (4.300)

Sig = NT ·(2 · π · fop · CGeff)2 ·mig

1 + (2 · π · fop · CGeff ·mig)2(4.301)

Sigid = NT ·2 · π · j · fop · CGeff ·migid

1 + 2 · π · j · fop · CGeff ·mig(4.302)



Thermal noise for parasitic resistances (see Fig. 3.2)

SRG = 4 · kB · TKD/Rgate (4.303)

SRBULK= 4 · kB · TKD/Rbulk (4.304)

SRWELL= 4 · kB · TKD/Rwell (4.305)

SRJUNS = 4 · kB · TKD/Rjuns (4.306)

SRJUND= 4 · kB · TKD/Rjund (4.307)

4.4.3 Shot noise

Gate current shot noise:

Sigs = 2 · q · (IGCS + IGSov) (4.308)

Sigd = 2 · q · (IGCD + IGDov) (4.309)

Avalanche current shot noise:

Savl = 2 · q · (1 +Mavl) · Iavl (4.310)

4.4.4 Edge transistor noise

The equations in this Section are only calculated when SWEDGE = 1 and BETNEDGE > 0 and xg,edge > 0.Flicker noise:

αnoise,edge =

√4

G2edge· (xg,edge − qieff,edge,m) + 1√

4G2

edge· (xg,edge − qieff,edge,m) + 1.1− 1

(4.311)

N∗edge =Cox

q· φT · αnoise,edge (4.312)

N∗m,edge =Cox

q· φT · (qieff,edge,m + αnoise,edge) (4.313)

∆Nedge = −Cox

q· φT · αnoise,edge · αmb,edge · qieff,edge,ds (4.314)

Sfl,edge =q · φ2

T · βedge · IDS,edge

(fop)EFEDGE · Cox ·Gvsat,dc ·N∗edge

·

[(NFAEDGE− NFBEDGE ·N∗edge

+ NFCEDGE ·N∗2edge) · ln

(N∗m,edge + ∆Nedge/2

N∗m,edge −∆Nedge/2

)

+(

NFBEDGE + NFCEDGE · [N∗m,edge − 2 ·N∗edge])·∆Nedge

](4.315)



Thermal noise:

H0,edge = φT ·(qieff,edge,m

αnoise,edge+ 1

)(4.316)

t1,edge =φ∗TφT· qieff,edge,m

qieff,edge,m + αnoise,edge(4.317)

t2,edge =

(φT · αmb,edge · qieff,edge,ds

12 ·H0,edge

)2

(4.318)

Redge =αnoise,edge ·H0,edge

αm ·H− 1 (4.319)

lc,edge = 1− 12 · t2,edge ·Redge (4.320)

gideal,edge =βedge · φT · (qieff,edge,m + αnoise,edge)

Gvsat,dc· F∆L,dc (4.321)

mid,edge =gideal,edge

l2c,edge

· [t1,edge + 12 · t2,edge − 24 · (1 + t1,edge) · t2,edge ·Redge] (4.322)

Sid,dge = NT,edge ·mid,edge (4.323)



4.5 Self heating

Fig. 4.1 shows the simple thermal network that is implemented in PSP. The current that reflects the powerdissipation is given by

Pdiss = IDS · VDS + Iimpact · (VDS + VSB) +V 2

SIS

Rsource+

V 2DID

Rdrain. (4.324)

If RTH < 10−3, Pdiss = 0. This can be used to switch off self heating.

The built-in thermal network of PSP can be bypassed (e.g., to replace it with an externally connected thermalnetwork) by setting CTH = 0 and assigning a very large value to RTH.

RTH

CTH

Pdiss

Vdt

Figure 4.1: Internal thermal network of PSP



Section 5

Non-quasi-static RF model

5.1 Introduction

For high-frequency modeling and fast transient simulations, a special version of the PSP model is available,which enables the simulation of non-quasi-static (NQS) effects, and includes several parasitic resistances.

5.2 NQS-effects

In the PSP-NQS model, NQS-effects are introduced by applying the one-dimensional current continuity equa-tion (∂I/∂y ∝ −∂ρ/∂t) to the channel. A full numerical solution of this equation is too inefficient for compactmodeling, therefore an approximate technique is used. The channel is partitioned into N + 1 sections of equallength by assigning N equidistant collocation points. The charge density (per unit channel area) along thechannel is then approximated by a cubic spline through these collocation points, assuring that both the chargeand its first and second spatial derivatives are continuous along the channel. Within this approximation, thecurrent continuity equation reduces to a system of N coupled first order ordinary differential equations, fromwhich the channel charge at each collocation point can be found:

dQ1

dt= f1(Q1, . . . , QN )

......

dQNdt

= fN (Q1, . . . , QN )

(5.1)

Here, Qi is the charge density at the i-th collocation point and fi are functions, which contain the completePSP-charge model. These equations are implemented by the definition of appropriate subcircuits (see left partof Fig. 5.1) and solved by the circuit simulator. Finally, the four terminal charges are calculated from thechannel charges, using the Ward-Dutton partitioning scheme for the source and drain charges.

A full description of the PSP-NQS model is given in Section 5.3. More background information can be foundin literature [9, 10].

5.3 NQS Model Equations

In this section, several symbols and notations are used which were defined in Section 4. Moreover, y denotesthe (normalized) position along the channel (y = 0 is source side, y = 1 is drain side), while x denotes thesurface potential (normalized to φ∗T) at a certain position.



RNQS

CNQS

Ii

Vi

Figure 5.1: The subcircuit used to solve one of the differential equations of Eq. (5.1). The current is set toIi = CNQS · f(V1, . . . , VN ), where the voltage Vi represents the charge density Qi at the i-th collocationpoint and is solved by the circuit simulator. N of these circuits are defined and they are coupled through thedependence of Ii on the voltages of the other circuits. The resistanceRNQS has a very large value and is presentonly for convergence purposes. Right: The full network of parasitic elements in the PSP-NQS model. The largefull dots indicate the five additional internal nodes.

5.3.1 Internal constants

Eqs. (5.2)–(5.7) are independent of bias conditions and time. Consequently, they have to be computed onlyonce.

Note: In PSP only SWNQS = 0, 1, 2, 3, 5, 9 are allowed!

n = SWNQS + 1 (5.2)

h = 1/n (5.3)

The matrix A is a square (n + 1) × (n + 1)-matrix with elements Ai,j (0 ≤ i, j ≤ n), which are used inEq. 5.25. They are computed using the following algorithm (adapted from [11]):

1. Initial values:

Ai,j = 0 for 0 ≤ i, j ≤ n (5.4)

vi = 0 for 0 ≤ i ≤ n (5.5)

2. First loop:

p = 2 + vi−1/2

vi = −1/(2 · p)

Ai,i−1 = 1/h

Ai,i = −2/h

Ai,i+1 = 1/h

Ai,j =1

p· (3 ·Ai,j/h−Ai−1,j/2)

for j = 0 . . . n

for i = 1 . . . (n− 1) (5.6)



3. Second loop (back substitution):

Ai,j = vi ·Ai+1,j +Ai,j for j = 0 . . . n

for i = (n− 1) . . . 0 (5.7)

5.3.2 Position independent quantities

The following quantities depend on the bias conditions, but are constant along the channel:

if xg,ac > 0

ym =1

2·(

1 +∆ψac

4 ·Hac

)

pd =xgm,ac

xg,ac − xm,ac

Gp = Gac/pd

(5.8)

if xg,ac ≤ 0

ym = 1/2

pd = 1

Gp = Gac

(5.9)

ap = 1 +Gp/√

2 (5.10)

pmrg = 10−5 · ap (5.11)

5.3.3 Position dependent surface potential and charge

Interpolated (quasi-static) surface potential along the channel:

Ψ(y) = xm,ac +Hac

φ∗T·

(1−

√1− 2 ·∆ψac

Hac· (y − ym)

)(5.12)

Normalized bulk-charge and its first two derivatives as functions of surface potential:

qb(x) = −sgn(x) ·Gp ·√

exp(−x) + x− 1 (5.13)

q′b(x) =G2

p · [1− exp(−x)]

2 · qb(x)(5.14)

q′′b(x) = −q′b(x)−q′b(x)2 −G2

p/2

qb(x)(5.15)



Surface potential as a function of normalized inversion charge (note that these equations are identical toEq. (4.204), despite the different notation and physical background):

Π(xg) =

if xg < −pmrg

yg = −xg

z = 1.25 · yg/ap

η =[z + 10−

√(z − 6)2 + 64

]/2

a = (yg − η)2

+G2p · (η + 1)

c = 2 · (yg − η)−G2p

τ = −η + ln(a/G2

p

)y0 = σ1(a, c, τ, η)

∆0 = exp(y0)

ξ = 1−G2p ·∆0/2

p = 2 · (yg − y0) +G2p · (∆0 − 1)

q = (yg − y0)2

+G2p · (y0 −∆0 + 1)

Π = −y0 −2 · q

p+√p2 − 4 · q · ξ

if |xg| ≤ pmrg

Π =

xg

ap

if xg > pmrg

xg1 = x1 +Gp ·√

exp(−x1) + x1 − 1

x =xg

ap· [1 + xg · (x1 · ap/xg1 − 1)/xg1]

x0 = xg +G2p/2−Gp ·

√xg +G2

p/4− 1 + exp(−x)

∆0 = exp(−x0)

ξ = 1−G2p ·∆0/2

p = 2 · (xg − x0) +G2p · (1−∆0)

q = (xg − x0)2 −G2p · (x0 + ∆0 − 1)

Π = x0 +2 · q

p+√p2 − 4 · q · ξ

(5.16)

X(xg, qinv) = Π(xg + qinv/pd) (5.17)

Auxiliary functions:

q(x) = −pd · (xg − x)− qb(x) (5.18)

ψ(q, qx1) =q

qx1− 1 (5.19)

φ(q, qx1, qx2) =

(1− q · qx2

q2x1

)/qx1 (5.20)



Normalized right-hand-side of continuity equation:

f(xg, q, q′, q′′) =

xz = X(xg, q)

qx1 =∂q

∂x(xz) = pd − q′b(xz)

qx2 =∂2q

∂x2(xz) = q′′b(xz)

f0 = ψ(q, qx1) · q′′ + φ(q, qx1, qx2) · q′2

xy1 =∂xz

∂y= q′/qx1

zsat =

(θ∗sat,ac · φ∗T · xy1

)2for NMOS

(θ∗sat,ac · φ∗T · xy1

)21 + θ∗sat,ac ·∆ψac

for PMOS

ζ =√

1 + 2 · zsat

Fvsat = 2/(1 + ζ)

f = Fvsat ·[f0 − Fvsat ·

zsat

ζ· ψ(q, qx1) · (q′′ + x2

y1 · q′′b(xz))

]

(5.21)

Normalization constant:

Tnorm =MUNQS · φ∗T · β

CqmOX

·Gmob,ac ·G∆L,ac (5.22)

5.3.4 Cubic spline interpolation

Using cubic spline interpolation, the spatial derivatives ∂qi∂y (t) and ∂2qi

∂y2 (t) can be expressed as functions of theqi(t).

q′′0 = 0 (5.23)

q′′n = 0 (5.24)

q′′i =

n∑j=0

Ai,j · qi for 1 ≤ i ≤ n− 1 (5.25)

q′i =qi+1 − qi

h− h

6· (2 · q′′i + q′′i+1) for 1 ≤ i ≤ n− 1 (5.26)

5.3.5 Continuity equation

Initial value for the qi (0 ≤ i ≤ n). These values are used for the DC operating point.

xi,0 = Ψ(i · h) (5.27)

qi,0 = q(xi,0) (5.28)

Note: x0,0 = xs and xn,0 = xd. Moreover, these values coincide with those in the quasi-static part of PSP.



The core of the NQS-model is the solution of q(y, t) from the charge continuity equation along the channel.By approximating the y-dependence by a cubic spline through a number of collocation points, the problem isreduced to solving the qi(t) from the following set of coupled differential equations.

∂qi∂t

(t) + Tnorm · f(xg,ac, qi(t),

∂qi∂y

(t),∂2qi∂y2

(t)

)= 0

qi(0) = qi,0

for 1 ≤ i ≤ n− 1 (5.29)

Note that the boundary points q0(t) = q(xs) = qis and qn(t) = q(xd) = qid remain fixed to their quasi-staticvalues; they are not solved from the equation above.

The set of differential equations defined above is solved by the circuit simulator via the subcircuits shown inthe left part of Fig. 5.1.

5.3.6 Non-quasi-static terminal charges

Once the qi are known, the NQS terminal charges can be computed:

S0 =

n−1∑i=1

qi (5.30)

S2 =

n−1∑i=1

q′′i (5.31)

qNQSI =

∫ 1

0

q(y) dy = h · S0 +h

2· (u0 + un)− h3

12· S2 (5.32)

U0 =

n−1∑i=1

i · qi (5.33)

U2 =

n−1∑i=1

i · q′′i (5.34)

qNQSD =

∫ 1

0

y · q(y) dy = h2 · U0 +h2

6· [q0 + (3n− 1)un]− h4

12· U2 (5.35)

qNQSS = qNQS

I − qNQSD (5.36)

Currently, only SWNQS = 0, 1, 2, 3, 5, 9 are allowed. For odd values of SWNQS the gate charge is integratedalong the channel using “Simpson’s rule”. If SWNQS = 2, “Simpson’s 3/8-rule” is used.

• If SWNQS is odd (that is, n is even):

qNQSG = pd ·

[xg,ac −

h

3·(X(xg,ac, q0) + 4 ·

n/2∑i=1

X(xg,ac, q2i−1)+

2 ·n/2−1∑i=1

X(xg,ac, q2i) +X(xg,ac, qn)

)](5.37)



• If SWNQS = 2 (that is, n = 3):

qNQSG = pd·

[xg,ac −

3 · h8· (X(xg,ac, q0) + 3 ·X(xg,ac, q1) + 3 ·X(xg,ac, q2) +X(xg,ac, q3))

](5.38)

Convert back to conventional units:

QNQSS = Cqm

OX · φ∗T · q

NQSS (5.39)

QNQSD = Cqm

OX · φ∗T · q

NQSD (5.40)

QNQSG = Cqm

OX · φ∗T · q

NQSG (5.41)

QNQSB = −(QNQS

S +QNQSD +QNQS

G ) (5.42)



Section 6

Embedding

6.1 Model selection

Circuit simulators have different ways for the user to determine which model must be used for simulation.Typically, model selection is either done by name or by assigning a value to the parameter LEVEL. Themethod to be used is prescribed by the circuit simulator vendor. If selection is done by name, the value ofthe parameter LEVEL is generally ignored. When Verilog-A code is used, model selection is always done byname.

For the SiMKit and the Verilog-A code provided by the PSP model developers, the method and values to beused are given in the table below. For other implementations, the method/value provided by the circuit simulatorvendor is to be used.

From PSP 103.0 onwards, the global, local and binning models are unified. All three models are called by thesame name or LEVEL. Model flavor selection is done by setting parameter SWGEO.

Simulator Model selection by Global (geom.) Global (binning) Local

Spectre psp103

SWGEO = 1 SWGEO = 2 SWGEO = 0Pstar LEVEL = 103

ADS psp103

Verilog-A PSP103VA

6.2 Case of parameters

Throughout this document, all parameter names are printed in uppercase characters. Similarly, in the Verilog-Acode provided by the PSP model developers, the parameters are in upper case characters. However, in otherPSP implementations a different choice can be made. For example, the parameter names may be in lowercasecharacters (possibly first character capitalized) if this is conform the conventions of the circuit simulator.

6.3 Embedding PSP in a Circuit Simulator

In CMOS technologies both n- and p-channel MOS transistors are supported. It is convenient to use thesame set of equations for both types of transistor instead of two separate models. This is accomplished bymapping a p-channel device with its bias conditions and parameter set onto an equivalent n-channel devicewith appropriately changed bias conditions (i.e. currents, voltages and charges) and parameters. In this wayboth types of transistor can be treated internally as an n-channel transistor. Nevertheless, the electrical behavior



of electrons and holes is not exactly the same (e.g., the mobility and tunneling behavior), and consequentlyslightly different equations have to be used in case of n- or p-type transistors.

Designers are used to the standard terminology of source, drain, gate and bulk. Therefore, in the context ofa circuit simulator it is traditionally possible to address, say, the drain of MOST number 17, even if in realitythe corresponding source is at a higher potential (n-channel case). More strongly, most circuit simulatorsprovide for model evaluation values for VDS, VGS, and VSB based on an a priori assignment of source, drain,and bulk, independent of the actual bias conditions. Since PSP assumes that saturation occurs at the drainside of the MOSFET, the basic model cannot cope with bias conditions that correspond to VDS < 0. Againa transformation of the bias conditions is necessary. In this case, the transformation corresponds to internallyreassigning source and drain, applying the standard electrical model, and then reassigning the currents andcharges to the original terminals. In PSP care has been taken to preserve symmetry with respect to drain andsource at VDS = 0. In other words, no singularities will occur in the higher-order derivatives at VDS = 0.

In detail, for correct embedding of PSP into a circuit simulator, the following procedure—illustrated in Fig. 6.1—is followed. It is assumed that the simulator provides the nodal potentials V eD, V eG, V eS and V eB based on an apriori assignment of drain, gate, source and bulk.

Step 1 The voltages V ′DS, V ′GS, and V ′SB are calculated from the nodal potentials provided by the circuit simu-lator. In the same step, the value of the parameter TYPE is used to deal with the polarity of the device.From here onwards, all transistors can be treated as n-channel devices.

Step 2 Depending on the sign of V ′DS, ‘source-drain interchange’ is performed. At this level, the voltagescomply to all the requirements for input quantities of PSP.

Step 3 All the internal output quantities (i.e. channel current, weak-avalanche current, gate current, nodalcharges, and noise-power spectral densities) are evaluated using the standard PSP equations (Section 4)and the internal voltages.

Step 4 The internal output quantities are corrected for a possible source-drain interchange.

Step 5 External output are corrected for a possible p-channel transformation and MULT is applied. The quan-tities of the intrinsic MOSFET and the junctions are combined.

In general, separate parameter sets are used for n- and p-channel transistors, which are distinguished by thevalue of TYPE. As a consequence, the changes in the parameter values necessary for a p-channel type transistorare normally already included in the parameter sets on file. The changes should therefore not be included inthe simulator.

6.3.1 Selection of device type

In the SiMKit-based and built-in version of PSP in certain circuit simulators, the selection of device type (nmosor pmos) is done using a different parameter, or using different parameter values. The correct values for somecircuit simulators are given in the table below.

Simulator Parameter Value NMOS value PMOS

Spectre type n p

Pstar type 1 −1

ADS gender 1 0

Verilog-A TYPE 1 −1



yes no

yes no

Figure 6.1: Schematic overview of source-drain interchange and handling of TYPE and MULT. Note thatTYPE and MULT are included in the JUNCAP2 model equations.



G

S D

B

G

S D

B

Figure 6.2: Topology of the PSP model. Left: n-channel MOSFET; Right: p-channel MOSFET. In PSP, thecorrect diode polarity is automatically chosen via the TYPE-parameter.

6.4 Integration of JUNCAP2 in PSP

Introduction

The JUNCAP2 model 200.3 is an integral part of PSP 102.2. In addition, it is available as a stand-alonemodel. A complete description of the JUNCAP2-model (including all model equations) can be found in thedocumentation of JUNCAP2’s stand alone version [12]. In this section, only the integration of JUNCAP2 inPSP is described.

Topology

In a MOS transistor, there are two junctions: one between source and bulk, and one between drain and bulk. Incase of an n-channel MOSFET, the junction anode corresponds to the MOSFET bulk terminal, and the junctioncathodes correspond to the source and the drain. In case of a p-channel MOSFET, it is the other way around:now the junction cathode corresponds to the MOSFET bulk terminal, and the junction anodes correspond tothe source and the drain. The connections are schematically given in Fig. 6.2. In PSP, this change of junctionterminal connections in case of a p-MOSFET is handled automatically via the TYPE parameter.

In most cases, the MOSFET is operated in such a way that the junctions are either biased in the reverse modeof operation or not biased at all. In some applications, however, the source-bulk junction has a small forwardbias. This is also the case in partially depleted SOI (PDSOI).

As indicated in Fig. 6.1, the interchange of source and drain for VDS < 0 (as explained above for the intrinsicMOS model) does not apply to the junctions. For example, ABDRAIN always refers to junction between thebulk and the terminal known as ‘drain’ to the simulator, independent of the sign of VDS.

Global and local model level

As explained in the introduction, the PSP model has a local and a global level. The JUNCAP2 model is ageometrically scaled model, i.e. it is valid for a range of junction geometries (as described by the geometricalparameters AB, LS, and LG). It has turned out that it is very unnatural to create a local parameter set forJUNCAP2, valid for one particular junction geometry: such a parameter set would have as many parametersas the global parameter set, and would be of no use. (Note that, in contrast, the local model for the intrinsicMOSFET is very useful in, e.g., parameter extraction; this is not the case for JUNCAP2.)

Therefore, the JUNCAP2 model is connected in exactly the same way to both the local and global model levelsof PSP. That means that the resulting PSP local model is valid for a MOSFET with one particular channel width



and length, but with arbitrary junction geometry.

Parameters

Both junctions in the MOSFET are modeled with the same set of JUNCAP2 parameters. In the PSP model, thegeometrical parameters AB, LS, and LG need to be specified for both source and drain. They will be denotedas ABSOURCE, LSSOURCE, and LGSOURCE for the source junction, and ABDRAIN, LSDRAIN, andLGDRAIN for the drain junction. For compatibility with BSIM instance parameters, there is also an optionto use AS, AD, PS, and PD. The complete list of instance parameters (PSP and JUNCAP2) can be found inSection 2.5.1.

The parameter MULT is merged with the parameter MULT of the intrinsic MOSFET model. In other words,both intrinsic currents, charges, and noise as well as junction currents, charges and noise are multiplied byone single parameter MULT. Beside MULT, also the parameters DTA and TYPE are shared by the intrinsicMOSFET model and the junction model. For clarity, we mention here that the reference temperatures of theintrinsic MOSFET model and junction model are not merged; they each have their own value and name (TRand TRJ, respectively). The currents, charges and spectral noise densities of the source and drain junctions arelabeled Ij,S, Qj,S, Sj,S, Ij,D, Qj,D, and Sj,D in Fig. 6.1.

6.5 Verilog-A versus C

As mentioned in Section 1.3, two implementations of the PSP-model are distributed: in Verilog-A language andin C-language (as part of the SiMKit). The C-version is automatically generated from the Verilog-A versionby a software package called ADMS [1]. This procedure guarantees that the two implementations containidentical model equations.

Nevertheless, there are a few minor differences between the two, which are due to certain limitations of eitherthe Verilog-A language or the circuit simulators supported in the SiMKit-framework. These differences aredescribed below.

6.5.1 Implementation of GMIN

In both implementations, there is an additional term in Eqs. (4.257) and (4.258), resulting in

ID = IDS + IDS,edge + Iavl − IGDov − IGCD + Igidl +Gmin · VDS (6.1)

and

IS = −IDS − IDS,edge − IGSov − IGCS + Igisl −Gmin · VDS. (6.2)

In the SiMKit, Gmin is a variable which is accessible by the circuit simulator. This allows the circuit simulatorto improve the convergence properties of a circuit by making use of so-called ‘Gmin-stepping’.

In the Verilog-A version of PSP, Gmin is set to a fixed value Gmin = 1 · 10−15 S.1

6.5.2 Implementation of parasitic resistances

From PSP 102.2 and PSP 103.0 onwards, a network of parasitic resistors has been inserted around the intrinsicMOSFET. If the user sets one or more of these resistance values to zero, the associated internal node(s) couldbe shorted to one of its neighbors, reducing the size of the matrix in the circuit simulator. This phenomenon iscalled ‘node collapse’ and is supported by most major circuit simulators.

1If supported by the circuit simulator, Verilog-A version 2.2 allows the value of Gmin to be accessed by the circuit simulator. Oncethis feature is generally available in Verilog-A compilers, it will be included in PSP as well.



Figure 6.3: Definition of noise currents.

Flexible topology (and thus node collapse) is presently supported by most Verilog-A compilers. As a result,node collapse is functional in the official PSP Verilog-A in the majority of today’s circuit simulators.

From SiMKit 3.0 onwards, the SiMKit architecture allows for flexible topologies and therefore supports nodecollapse in PSP. This functionality is therefore available in circuit simulations with that can work with SiMKit.Besides, many circuit simulators that have a native implementation of PSP support node collapse.

6.5.3 Implementation of the noise-equations

Definition of noise model

Eqs. (4.300), (4.301), and (4.302) describe the noise power spectral density of the thermal noise. In this section,the relationship between the quantities Sid, Sig, and Sigid (as calculated in these equations) and noise sourcesin the model is defined.

Fig. 6.3 shows a schematic representation of a noiseless transistor (model) and three noise sources. The small-signal noise currents of these noise current sources are indicated by ids, igs, and igd. The two noise sourcesconnected to G are fully correlated. Moreover, each of them is partly correlated with the noise source betweenS and D. More precisely, the noise powers and correlations associated with these sources are given by

〈ids · i∗ds〉 = Sid

〈igd · i∗ds〉 = Sigid/2

〈igs · i∗ds〉 = Sigid/2

〈igd · i∗gd〉 = Sig/4

〈igs · i∗gd〉 = Sig/4

〈igs · i∗gs〉 = Sig/4

(6.3)

The non-listed elements follow from the fact that this is a complex correlation matrix and therefore self-adjoint.This defines the noise model of PSP.

For completeness, we will give the noise correlation matrix associated with the terminal currents id, ig and is,because it is closer related to the numbers that are obtained in a circuit simulation. Because id = ids − igs,



ig = igs + igd and is = igs − ids, we find by straightforward substitution and some basic arithmetic

〈id · i∗d〉 = Sid + Sig/4− Re(Sigid)

〈ig · i∗d〉 = Sigid − Sig/2

〈is · i∗d〉 = −Sid + Sig/4− Im(Sigid)

〈ig · i∗g〉 = Sig

〈is · i∗g〉 = −S∗igid − Sig/2

〈is · i∗s 〉 = Sid + Sig/4 + Re(Sigid)

(6.4)

Verilog-A

In Verilog-A it is not possible to define noise sources that are frequency dependent (except for 1/f -noise), noris it possible to directly define correlations between noise sources. Instead, the desired model must be createdby using controlled sources and the frequency transfer of passive elements.2

The goal is to create the three noise sources shown in Fig. 6.3 with the noise powers (including frequencydependence and correlation) as described by Eq. (6.3).

To simplify notation, we rewrite Eqs. (4.301) and (4.302) as

Sig =NT

mig· |T |2 (6.5)

and

Sigid =NT

mig·migid · T, (6.6)

where

T =j · ω · τ

1 + j · ω · τ, (6.7)

τ = mig · CGeff and ω is the operating frequency.

Correlation between noise sources in verilog-A can be created by making linear combinations of independentsources. Therefore, we start with two independent white noise sources with current noise spectral densities S1

and S2 and noise currents i1 and i2. If we set

igs = igd =1

2· α1 · i1 (6.8)

ids = β1 · i1 + β2 · i2, (6.9)

where α1, β1, and β2 are certain (complex) coefficients, we get

Sig = 4 · 〈igd · i∗gd〉 = |α1|2 · 〈i1 · i∗1〉= |α1|2 · S1 (6.10)

Sid = 〈ids · i∗ds〉 = |β1|2 · 〈i1 · i∗1〉+ β1 · β∗2 · 〈i1 · i∗2〉+ |β2|2 · 〈i2 · i∗2〉= |β1|2 · S1 + |β2|2 · S2 (6.11)

Sigid = 2 · 〈igd · i∗ds〉 = α1 · β∗1 · 〈i1 · i∗1〉+ α1 · β∗2 · 〈i1 · i∗2〉= α1 · β∗1 · S1. (6.12)

Here we used that the noise currents i1 and i2 are independent, such that 〈i1 ·i∗2〉 = 0. We need to choose propervalues for the coefficients α1, β1 and β2, as well as S1 and S2, such that Sig, Sid, and Sigid get the correct value.

2Although this appears to be a limitation, it is in fact very helpful to ensure that the resulting noise model is consistent with time-domainsimulations.



NOI

11

VNOIR

S D

G

Figure 6.4: The subcircuit used in PSP’s Verilog-A implementation to model the correct frequency dependenceof induced gate noise and its correlation with the channel thermal noise.

There is some freedom in choosing the numbers; the values that are used in the verilog-A implementation ofPSP are:

α1 = T (6.13)β1 = migid (6.14)β2 = 1 (6.15)S1 = NT/mig (6.16)S2 = NT · (1− C2

igid) ·mid, (6.17)

where

Cigid =migid√mig ·mid

, (6.18)

and mid, mig, and migid are given by Eqs. (4.297), (4.298), and (4.299), respectively.

Compared with previous version of PSP, the verilog-A code of PSP103.4 and later, a single equivalent circuitis used to implement frequency dependence. This subcircuit, shown in Fig. 6.4, contains a parallel connectionof a white noise source with a resistor R1 and a capacitance C1. The parameters of these components are givenby:

S1 = 〈i1 · i∗1〉 = NT (6.19)R1 = 1 Ω (6.20)C1 = mig · CGeff (6.21)

where the values of CGeff is given by Eqs. (4.286).

The two noise sources connected to the gate in Fig. 6.4 are as two voltage-controlled current sources with:

igd = igs =1

2· T · VNOI (6.22)

The third source in Fig. 6.3 (between source and drain) is realized by putting two elements in parallel, asillustrated in Fig. 6.4:

• A current-controlled current source ix controlled by INOII;

• A white noise source with current power spectral density S2 = NT · (1− C2igid) ·mid.



Where the current ix is given by:

ix = Cigid ·√mid · INOII (6.23)

To complete the model, we remark that from Fig. 6.3 it is clear that source-drain interchange only affects thesign of ids.

In summary, the relevant portion of the verilog-A implementation is given by (mult-scaling and labels are notincluded for clarity):

electrical NOI;

branch (NOI) NOII;branch (NOI) NOIR;branch (NOI) NOIC;

// subcircuitI(NOII) <+ white_noise((nt / mig));I(NOIR) <+ V(NOIR) / mig;I(NOIC) <+ ddt(CGeff * V(NOIC));

// noise sources ids, igs, and igdI(GP,SI) <+ -ddt(sqrt(MULT_i) * 0.5 * CGeff * V(NOIC));I(GP,DI) <+ -ddt(sqrt(MULT_i) * 0.5 * CGeff * V(NOIC));I(DI,SI) <+ sigVds * sqrt(MULT_i) * migid * I(NOII);I(DI,SI) <+ white_noise(MULT_i * sqid * sqid * (1.0 - c_igid * c_igid));

It is straightforward to verify that this implementation of PSP’s noise model in Verilog-A naturally yields thedesired correlations and frequency dependence. However, it requires two additional internal nodes.

SiMKit C-code

Contrary to the limitation of Verilog-A language, most circuit simulators are able to directly deal with cor-related and frequency dependent noise—without the use of additional internal nodes. In order to minimizethe simulation time of the model, C-implementations should therefore avoid the use of such internal nodeswhenever possible.

In SiMKit, the frequency dependence and correlation of the noise sources indicated in Fig. 6.3 are implementeddirectly according to Eq. (6.3). The result is therefore equivalent to the verilog-A implementation.

In summary, even though the SiMKit-implementation of the noise model in PSP is different from that in verilog-A (as it does not make use of additional internal nodes) the result of noise noise simulations will be identical.

6.5.4 Clip warnings

From SiMKit 3.7 onwards, it is possible to set the level of clip-warning information through the value of theparameter PARAMCHK. This functionality is available for most SiMKit models. It is not available in theverilog-A version of PSP.

If the value of PARAMCHK is

< 0 All clip warnings are suppressed.

≥ 0 (default) Clip warnings for instance parameters.

≥ 1 Clip warnings for model parameters.

≥ 2 Clip warnings for internally computed local parameters during model initialization.

≥ 3 Clip warnings for internally computed local parameters during model evaluation.



This works in an accumulative manner: if a higher value of PARAMCHK is used, the warnings associatedwith lower levels are still included. Note that the highest level is of interest only for self heating models, whereelectrical parameters may change dependent on temperature. Also note that the default value (0) results in lessclip warnings than in earlier versions of the model.





Section 7

Parameter extraction

The parameter extraction strategy for PSP consists of four main steps:

1. Measurements

2. Extraction of local parameters at room temperature

3. Extraction of temperature scaling parameters

4. Extraction of geometry scaling (global) parameters

The above steps will be briefly described in the following sections. Note that the description of the extractionprocedure is not ‘complete’ in the sense that only the most important parameters are discussed and in cases athand it may be advantageous (or even necessary) to use an adapted procedure.

Throughout this section, bias and current conditions are given for an n-channel transistor only; for a p-channeltransistor, all voltages and currents should be multiplied by −1.

As explained in the introduction, the hierarchical setup of PSP (local and global level) allows for the two-step parameter extraction procedure described in this section; this is the recommended method of operation.Nevertheless, it is possible to skip the first steps and start extracting global parameters directly. This procedureis not described here, but the directions below may still be useful.

7.1 Measurements

The parameter extraction routine consists of six different DC-measurements (two of which are optional) andtwo capacitance measurements.1 Measurement V and VI are only used for extraction of gate-current, avalanche,and GIDL/GISL parameters.

• Measurement I (“idvg”): ID vs. VGS

VGS = 0 . . . Vsup (with steps of maximum 50 mV).VDS = 25 or 50 mVVBS = 0 . . .− Vsup (3 or more values)

• Measurement II (“idvgh”): ID vs. VGS

VGS = 0 . . . Vsup (with steps of maximum 50 mV).VDS = Vsup

VBS = 0 . . .− Vsup (3 or more values)

1The bias conditions to be used for the measurements are dependent on the supply voltage of the process. Of course it is advisable torestrict the range of voltages to this supply voltage Vsup. Otherwise physical effects atypical for normal transistor operation—and thereforeless well described by PSP—may dominate the characteristics.



• Measurement III (“idvd”): ID vs. VDS

VGS = 0 . . . Vsup (3 or more values)VDS = 0 . . . Vsup (with steps of maximum 50 mV).VBS = 0 V

• Measurement IV (“idvdh”, optional):ID vs. VDS

VGS = 0 . . . Vsup (3 or more values)VDS = 0 . . . Vsup (with steps of maximum 50 mV).VBS = −Vsup

• Measurement V (“igvg”): IG and IB vs. VGS

VGS = −Vsup . . . Vsup (with steps of maximum 50 mV).VDS = 0 . . . Vsup (3 or more values)VBS = 0 V

• Measurement VI (“igvgh”, optional): IG and IB vs. VGS

VGS = −Vsup . . . Vsup (with steps of maximum 50 mV).VDS = 0 . . . Vsup (3 or more values)VBS = −Vsup

• Measurement VII (“cggvg”): CGG vs. VGS

VGS = −Vsup . . . Vsup (with steps of maximum 50 mV).VDS = 0 VVBS = 0 V

• Measurement VIII (“ccgvg”): CCG vs. VGS

VGS = −Vsup . . . Vsup (with steps of maximum 50 mV).VDS = 0 VVBS = 0 V

For the extraction procedure, the transconductance gm (for Measurement I and II) and the output conduc-tance gDS (for Measurement III and IV) are obtained by numerical differentiation of the measured I-V -curves.Furthermore, Imin is the smallest current which can reliably measured by the system (noise limit) and IT isdefined as 10% of the largest measured value of |ID| in Measurement I. The latter will be used to make a roughdistinction between the subthreshold and superthreshold region.

The channel-to-gate capacitance CCG in Measurement VIII is the summation of the drain-to-gate capaci-tance CDG and the source-to-gate capacitance CSG (i.e., source and drain are short-circuited); it is neededto extract overlap capacitance parameters.

The local parameter extraction measurements I through VI have to be performed at room temperature for everydevice. In addition, capacitance measurements VII and VIII need to be performed for at least a long/wide anda short/wide (i.e., L = Lmin) transistor (at room temperature). Furthermore, for the extraction of temperaturescaling parameters measurements I, III, and V have to be performed at different temperatures (at least two extra,typically −40 C and 125 C) for at least a long wide and a short wide transistor.

7.2 Extraction of local parameters at room temperature

General remarks

The simultaneous determination of all local parameters for a specific device is not advisable, because the valueof some parameters can be wrong due to correlation and suboptimization. Therefore it is more practical to



split the parameters into several small groups, where each parameter group can be determined using specificmeasurements. In this section, such a procedure will be outlined.

The extraction of local parameters is performed for every device. In order to ensure that the temperature scalingrelations do not affect the behavior at room temperature, the reference temperature TR should be set equal toroom temperature.

Before starting the parameter extraction procedure, one should make sure that SWIGATE, SWIMPACT,SWGIDL, SWJUNCAP, and TYPE are set to the desired value. Moreover, QMC should be set to 1, in orderto include quantum mechanical corrections in the simulations.

It is not the case that all local parameters are extracted for every device. Several parameters are only extractedfor one or a few devices, while they are kept fixed for all other devices. Moreover, a number of parameterscan generally be kept fixed at their default values and need only occasionally be used for fine-tuning in theoptimization procedure. Details are given later in this section.

As a special case, it is generally not necessary to extract values for AX. In stead, they can be calculated fromEq. (3.74), using AXO ∼ 18 and AXL ∼ 0.25. It may be necessary to tune the latter value such that the valueof AX is between 2 and 3 for the shortest channel in the technology under study.

It is recommended to start the extraction procedure with the long(est) wide(st) device, then the shortest devicewith the same width, followed by all remaining devices of the same width in order of decreasing length. Thenthe next widest-channel devices are extracted, where the various lengths are handled in the same order. In thisway, one works ones way down to the narrowest channel devices.

AC-parameters

Some parameters (such as TOX and NP) that do affect the DC-behavior of a MOSFET can only be extractedaccurately from C-V -measurements.2 This should be done before the actual parameter extraction from DC-measurements is started. In Tables 7.1 and 7.2 the extraction procedure for the AC-parameters is given.

Table 7.1: AC-parameter extraction procedure for a long channel MOSFET.

Step Optimized parameters Fitted on Abs./Rel. Conditions

1 VFB,NEFF, DPHIB, NP, COX VII: CGG Relative –2 Repeat Step 1

Table 7.2: AC-parameter extraction procedure for a short channel MOSFET. The val-ues of VFB and NP are taken from the long-channel case.


1 NEFF, DPHIB, COX VII: CGG Relative –2 CGOV, NOV VIII: CCG Relative VGS < 0

3 Repeat Steps 1 and 2

Starting from the default parameter set and setting TOX to a reasonable value (as known from technology),VFB, NEFF, DPHIB, COX, and NP can be extracted from CGG in Measurement VII for a long, wide device.

Next, NOV and CGOV can be extracted from CCG in Measurement VIII for a short, wide device (see alsoTable 7.1), where VFB and NP are taken from the long channel case. In general, one can assume TOXOV =TOX.

The value of TOX can be determined from COX = εox · L ·W/TOX. If the device is sufficiently long andwide, drawn length and width can be used in this formula. Even better, if Measurement VII is available for a

2Although parameter NOV can be determined from overlap gate current, it is nonetheless more accurately determined from Measure-ment VIII.



few short/wide devices of different lengths, one can extract TOX and ∆L from a series of extracted values ofCOX vs. Ldraw.

Some remarks:

• If C-V -measurements are not available, one could revert to values known from the fabrication process.Note that TOX and TOXOV are physical oxide thicknesses; poly-depletion and quantum-mechanicaleffects are taken care of by the model. If the gate dielectric is not pure SiO2, one should manuallycompensate for the deviating dielectric constant.

• In general, VFB and NP can be assumed independent of channel length and width (so, the long/wide-channel values can be used for all other devices as well). Only if no satisfactory fits are obtained,one could allow for a length dependence (for NP) or length and width dependence (for VFB). Then,one should proceed by extracting VFB and/or NP from capacitance measurements for various channelgeometries, fit Eq. (3.13) / Eq. (3.34) to the result and use interpolated values in the DC parameterextraction procedure.

• The value of parameter TOX profoundly influences both the DC- and AC-behavior of the PSP-model andthus the values of many other parameters. It is therefore very important that this parameter is determined(as described above) and fixed before the rest of the extraction procedure is started.

If desired (e.g., for RF-characterization), parameters for several parasitic capacitances (gate-bulk overlap, fringecapacitance, etc.) can be extracted as well (CGBOV and CFR). However, this requires additional capacitancemeasurements.

The obtained values of VFB, TOX, TOXOV, NP, and NOV can now be used in the DC-parameter extractionprocedure. The above values of NEFF and DPHIB can be disregarded; they will be determined more accuratelyfrom the DC-measurements.

In devices with strong lateral non-uniform doping, the threshold voltage in AC-measurements may deviatesignificantly from that in DC-measurements. If that is the case, values for NEFF and DPHIB obtained fromDC-measurements may not be satisfactory to describe AC-measurements. Then, one has the option to setSWDELVTAC = 1, DELVTAC = DPHIBac − DPHIBdc, and FACNEFFAC = NEFFac/NEFFdc to get agood description of both the DC and the AC measurements.

DC-parameters

Before the optimization is started a reasonably good starting value has to be determined, both for the parametersto be extracted and for the parameters which remain constant. For most parameters to be extracted for along channel device, the default values from local parameters in Section 2.5.2 can be taken as initial values.Exceptions are given in Table 7.3. Starting from these values, the optimization procedure following the schemebelow is performed. This method yields a proper set of parameters after the repetition indicated as the finalstep in the scheme. Experiments with transistors of several processes show that repeating those steps more thanonce is generally not necessary.

For an accurate extraction of parameter values, the parameter set for a long-channel transistor has to be deter-mined first. In the long-channel case most of the mobility related parameters (i.e. MUE and THEMU) andthe gate tunneling parameters (GCO, GC2, and GC3) are determined and subsequently fixed for the shorter-channel devices.

In Table 7.4 the complete DC extraction procedure for long-channel transistors is given. The magnitude ofthe simulated ID and the overall shape of the simulated ID-VGS-curve is roughly set in Step 1. Next theparameters NEFF, DPHIB, and CT—which are important for the subthreshold behavior—are optimized inStep 2, neglecting short-channel effects such as drain-induced barrier-lowering (DIBL). After that, the mobilityparameters are optimized in Step 3, neglecting the influence of series-resistance. In Step 4 a preliminary valueof the velocity saturation parameter is obtained, and subsequently the conductance parameters ALP, ALP1,ALP2, and VP are determined in Step 5. A more accurate value of THESAT can now be obtained using Step6. The gate current parameters are determined in Steps 7 and 8, where it should be noted that GCO shouldonly be extracted if the influence of gate-to-bulk tunneling is visible in the measurements. This is usually the



Table 7.3: Initial values for local parameter extraction for a long-channel device. Forparameters which are not listed in this table, the default value (as given inSection 2.5.2) can be used as initial value.

Parameter Initial value

BETN 0.03 ·W/LRS 0THESAT 0.1AX 12A1 0

Table 7.4: DC-parameter extraction procedure for a long-channel MOSFET. The pa-rameters VFB, TOX, TOXOV, NP, and NOV must be taken from C-V -measurements. The optimization is either performed on the absolute or rel-ative deviation between model and measurements, as shown in the table.


1 NEFF, BETN, MUE, THEMUa I: ID Absolute –2 NEFF, DPHIB, CT, GFACNUD I: ID Relative Imin < ID < IT

3 MUE, THEMUa, CS, THECS, XCOR, BETN I: ID, gm Absolute –4 THESAT III: ID Absolute –5 ALP, ALP1, ALP2, VPa, (AX) III: gDS Relative –6 THESAT II: ID Absolute –7 IGINV, GC2a, GC3a V: IG Relative IG > Imin

8 IGOV, (GCOa) V: IG Relative VGS < 0 V, IG < −Imin

9 A1, A2a, A3 V: IB Relative VGS > 0 V, IB < −Imin

10 A4 VI: IB Relative VGS > 0 V, IB < −Imin

11 AGIDL, BGIDLa V: IB Relative VGS < 0 V, IB < −Imin

12 CGIDLa VI: IB Relative VGS < 0 V, IB < −Imin

13 Repeat Steps 2 – 12

aOnly extracted for the widest long channel device and fixed for all other geometries.

case if Vsup & |VFB|. This is followed by the weak-avalanche parameters in Step 9 and (optionally) 10, andfinally, the gate-induced leakage current parameters are optimized in Step 11 and (optionally) 12.

After completion of the extraction for the long-channel device, it is recommended to first extract parametersfor the shortest-channel device (of the same width). The mobility-reduction parameters (MUE, THEMU) andthe gate tunneling probability factors (GCO, GC2, GC3) found from the corresponding long-channel deviceshould be used. The extraction procedure as given in Table 7.5 should be used.

Once the value for RS has been found from the shortest device, it should be copied into the long-channelparameter set and steps 2–3 (Table 7.4) should be repeated, possibly leading to some readjustment of MUEand THEMU. If necessary, this procedure must be repeated. Similarly—once the value of THESATG andTHESATB have been determined from the shortest widest channel device—steps 4, 5, and 6 of the long-channel extraction procedure (Table 7.4) must be repeated to obtain updated values for THESAT, ALP, ALP1,and ALP2.

If consistent parametersets have been found for the longest and shortest channel device, the extraction procedure



Table 7.5: DC-parameter extraction procedure for a short-channel MOSFET. Parame-ters MUE, THEMU, VP, GCO, GC2, GC3, A2, A4, BGIDL, and CGIDLare taken from the corresponding long-channel case. The optimization iseither performed on the absolute or relative deviation between model andmeasurements, as indicated in the table.


1 NEFF, DPHIB, BETN, RSa I: ID Absolute –2 NEFF, DPHIB, CT, GFACNUD, VSB-

NUDb, DVSBNUDbI: ID Relative Imin < ID < IT

3 BETN, RSa, XCOR I: ID, gm Absolute –4 THESAT III: ID Absolute –5 ALP, ALP1, ALP2, CF, (AX) III: gDS Relative –6 CFBb IV: gDS Relative –7 THESAT, THESATGb, THESATBb II: ID, gm Absolute –8 IGINV, IGOV V: IG Relative |IG| > Imin

9 A1, A3 V: IB Relative VGS > 0 V, IB < −Imin

10 AGIDL V: IB Relative VGS < 0 V, IB < −Imin

11 Repeat Steps 2 – 10

aOnly extracted for the shortest channel of each width and fixed for all other geometries.bOnly extracted for the shortest widest device and fixed for all other geometries.

as given in Table 7.5 can be executed for all intermediate channel lengths. The extracted parameter values ofthe next-longer device can be used as initial values.

Finally, the parameters GFACNUD, VSBNUD, and DVSBNUD should only be used if the description of thebody effect is not satisfactory otherwise. For this, the NUD-model must be invoked by setting SWNUD = 1.

7.3 Extraction of Temperature Scaling Parameters

For a specific device, the temperature scaling parameters can be extracted after determination of the localparameters at room temperature. In order to do so, measurements I, II and IV need to be performed at varioustemperature values (at least two values different from room temperature, typically−40 C and 125 C), at leastfor a long wide device and a short wide device. If the reference temperature TR has been chosen equal to roomtemperature (as recommended in Section 7.2), the modeled behavior at room temperature is insensitive to thevalue of the temperature scaling parameters. As a first-order estimate of the temperature scaling parametervalues, the default values as given by local parameters in Section 2.5.2 can be used. Again the parameterextraction scheme is slightly different for the long-channel and for the short-channel case.

For an accurate extraction, the temperature scaling parameters for a long-wide-channel device have to be de-termined first. In the long-wide-channel case the carrier mobility parameters can be determined, and they aresubsequently fixed for all other devices. In Table 7.6 the appropriate extraction procedure is given. In Step1 the subthreshold temperature dependence is optimized, followed by the optimization of mobility reductionparameters in Step 2. Next the temperature dependence of velocity saturation is optimized in Step 3. In the sub-sequent steps, parameters for the temperature dependence of the gate current, the impact ionization current andgate-induced drain leakage are determined. The determined values of the mobility reduction temperature scal-ing parameters (i.e., STMUE, STTHEMU, STCS, STTHECS and STXCOR) are copied to all other devicesand kept fixed during the remainder of the temperature-scaling parameter extraction procedure. Step 1 and 2could then be performed on one or more long narrow devices as well (for STVFB, STBETN, and STTHESATonly).

Next the extraction procedure as given in Table 7.7 is carried out for several short devices of different widths.



Table 7.6: Temperature scaling parameter extraction procedure for a long wide chan-nel MOSFET. This scheme only makes sense if measurements have beenperformed at one or (preferably) more temperatures which differ from roomtemperature.


1 STVFBa I: ID Relative ID < IT

2 STBETNa, STMUE, STTHEMU, I: ID Absolute –STCS, STTHECS, STXCOR

3 STTHESATa II: ID Absolute –4 STIG V: IG Relative |IG| > Imin

5 STA2 V: IB Relative VGS > 0 V, IB < −Imin

6 STBGIDL V: IB Relative VGS < 0 V, IB < −Imin

aAlso extracted for one or more long narrow devices.

Table 7.7: Temperature scaling parameter extraction procedure for short-channelMOSFETs (both wide and narrow). This scheme only makes sense if mea-surements have been performed at one or (preferably) more temperatureswhich differ from room temperature.


1 STVFB I: ID Relative VGS < VT

2 STBETN, STRSa I: ID Absolute VGS > VT

3 STTHESAT II: ID Absolute –

aOnly extracted for a short narrow device and fixed for all other geometries.

Preferably, the extraction is done first for a short narrow device, such that the determined value of STRS canbe used during the extraction of the wider devices.

7.4 Extraction of Geometry Scaling Parameters

The aim of the complete extraction procedure is the determination of the geometry scaling parameters (globalparameters), i.e., a single set of parameters (see Section 2.5.2) which gives a good description of the MOSFET-behavior over the full geometry range of a CMOS technology.

Determination of ∆L and ∆W

An extremely important part of the geometry scaling extraction scheme is an accurate determination of ∆Land ∆W , see Eqs. (3.7) and (3.8).3 Since it affects the DC-, the AC- as well as the noise model and, moreover,it can heavily influence the quality of the resulting global parameter set, it is very important that this step iscarried out with care.

Traditionally, ∆W can be determined from the extrapolated zero-crossing in BETN versus mask width W . Ina similar way ∆L can be determined from 1/BETN versus mask length L. For modern MOS devices withpocket implants, however, it has been found that the above ∆L extraction method is no longer valid [13, 14].Another, more accurate method is to measure the gate-to-bulk capacitance CGB in accumulation for different

3Note that ∆LPS and ∆WOD are expected to be known from the fabrication process. So, in fact, only LAP and WOT are extractedfrom the electrical measurements.



channel lengths [14, 15]. In this case the extrapolated zero-crossing in theCGB versus mask length L curve willgive ∆L. Similarly, the extracted values for COX (from the procedure in Table 7.1 and 7.2) vs. mask length Lmay be used for this purpose. Unfortunately for CMOS technologies in which gate current is non-negligible,capacitance measurements may be hampered by gate current [16]. In this case gate current parameter IGINVplotted as a function of channel length L may be used to extract ∆L [16]. If possible, ∆L extraction fromC-V -measurements is the preferred method.

Finally, LOV can be obtained from (a series of) extracted values of CGOV from one or more short devices.

From local to global

First of all, the global parameters TYPE, QMC, and the ‘switch’-parameters should be set to the appropriatevalue. Next, parameters for which no geometrical scaling rules exist must be taken directly from the local set(this applies to TR, TOXO, VNSUBO, NSLPO, DNSUBO, TOXOVO, NOVO, CFBO, STMUEO, THE-MUO, STTHEMUO, STCSO, STTHECSO,STXCORO, FETAO, STRSO, RSBO, RSGO, THESATBO,THESATGO, VPO, A2O, STA2O, GCOO, STIGO, GC2O, GC3O, CHIBO, BGIDLO, STBGIDLO,CGIDLO, and DTA). Generally, these parameters have been left at their default values or they have beenextracted for one device only and subsequently fixed for all other devices. The parameters LVARO, LVARL,LVARW, WVARO, WVARL, and WVARW should be known from technology.

Once the values of ∆L and ∆W are firmly established (as described above), LAP and WOT can be set and theactual extraction procedure of the geometry scaling parameters can be started. It consists of several independentsub-steps (which can be carried out in random order), one for each geometry dependent local parameter.

To illustrate such a sub-step, the local parameter CT is taken as an example. The relevant geometry scalingequation from Section 3.2 is Eq. (3.39), from which it can be seen that CTO, CTL, CTLEXP, and CTW arethe global parameters which determine the value of CT as a function of L and W . First, the extracted CT ofeach device in a length-series of measured (preferably wide) devices are considered as a function of L. In thiscontext CTO, CTL, and CTLEXP are optimized such that the fit of Eq. (3.39) to the extracted CT-values isas good as possible, while keeping CTW fixed at 0. Then CTW is determined by considering the extractedCT-values from a length-series of measured narrow devices. Finally, the four global parameters may be fine-tuned by optimizing all four parameters to all extracted CT-values simultaneously. The default values given inSection 2.5.2 are good initial values for the optimization procedure.

All other parameters can be extracted in a similar manner. The local parameters BETN and NEFF have quitecomplicated scaling rules, particularly due to the non-uniform doping profiles employed in modern CMOStechnologies. Therefore, a few additional guidelines are in place.

• The optimization procedure for BETN is facilitated if not BETN, but BETNsqdef= BETN · LE/WE is

considered.

• Starting from the default values, first UO, FBET1, LP1, FBET2, and LP2 should be determined from alength-series of wide devices. Then BETW1, BETW2, and WBET should be determined from a width-series of long devices. Finally, FBET1W and LP1W can be found by considering some short narrowdevices.

• Starting from the default values, first extract FOL1, FOL2, NSUBO, NPCK, and LPCK from a length-series of wide devices. Here, NSUBO determines the long-channel value of NEFF. Moreover, NPCKand LPCK determine the increase of NEFF for shorter channels (reverse short channel effect), whileFOL1 and FOL2 are used to describe the decrease of NEFF for very short channels (short channeleffect).

• Then NSUBW and WSEG can be determined form a width-series of long devices. Finally, NPCKW,LPCKW and WEGP are determined from a width-series of short devices.

• Especially for BETN and NEFF it is advisable—after completing the procedure described above—to finetune the global parameters found by considering all extracted values of BETN (or NEFF) simultaneously.



Note that in many cases it may not be necessary to use the full flexibility of PSP’s parameter scaling, e.g.,for many technologies NP and VFB may be considered as independent of geometry. If such a geometry-independence is anticipated, the corresponding local parameter should be fixed during local parameter extrac-tion. Only if the resulting global parameter set is not satisfactory, the parameter should be allowed to varyduring a subsequent optimization round.

Fine tuning

Once the complete set of global parameters is found, the global model should give an accurate description ofthe measured I-V -curves and capacitance measurements. Either for fine tuning or to facilitate the extractionof global parameters for which the geometry scaling of the corresponding extracted local parameters is notwell-behaved, there are two more things that can be done.

• Local parameters for which the fitting of global parameters was completed satisfactorily could be re-placed by the values calculated from the geometrical scaling rules and fixed. Then one could redo (partsof) the local parameter extraction procedure for the remaining local parameters, making them less sensi-tive for cross-correlations.

• Small groups of global parameters may be fitted directly to the measurements of a well-chosen series ofdevices, using the global model.

7.5 Summary – Geometrical scaling

Summarizing, for the determination of a full parameter set, the following procedure is recommended.

1. Determine local parameter sets (VFB, NEFF, . . .) for all measured devices, as explained in Section 7.2and 7.3.

2. Find ∆L and ∆W .

3. Determine the global parameters by fitting the appropriate geometry scaling rules to the extracted localparameters.

4. Finally, the resulting global can be fine-tuned, by fitting the result of the scaling rules and current equa-tions to the measured currents of all devices simultaneously.

7.6 Extraction of Binning Parameters

In this section, expressions will be given for the parameters in the binning scaling rules, POYYY, PLYYY,PWYYY, and PLWYYY, as given in Section 3.3. These coefficients will be expressed in terms of parametervalues at the corners of bin (see Fig. 7.1). These expressions can be easily found by substituting the parametervalues at the bin corners into the binning scaling rules and inverting the resulting four equations. Note oncemore that this results in a separate parameter set for each bin.

In the expression below, the value of parameter YYY at bin corner (Li,Wj) is denoted by Yij (i = 1, 2,j = 1, 2). Moreover, ∆L = L2 − L1, ∆W = W2 −W1, A = 1/(∆L ·∆W ).

1. Coefficients for type I scaling

POYYY = A · (L1 ·W1 · Y11 − L1 ·W2 · Y12 − L2 ·W1 · Y21 + L2 ·W2 · Y22) (7.1)

PLYYY = A · L1 · L2

LEN· (−W1 · Y11 +W2 · Y12 +W1 · Y21 −W2 · Y22) (7.2)



Figure 7.1: Schematic view of a bin, showing the coordinates of the four corners. Note that L1, L2, W1, andW2 denote the effective length and width (LE and WE) at the bin corners.

PWYYY = A · W1 ·W2

WEN· (−L1 · Y11 + L1 · Y12 + L2 · Y21 − L2 · Y22) (7.3)

PLWYYY = A · L1 · L2 ·W1 ·W2

LEN ·WEN· (Y11 − Y12 − Y21 + Y22) (7.4)

2. Coefficients for type II scaling

POYYY = A · (L2 ·W2 · Y11 − L2 ·W1 · Y12 − L1 ·W2 · Y21 + L1 ·W1 · Y22) (7.5)

PLYYY = A · LEN · (−W2 · Y11 +W1 · Y12 +W2 · Y21 −W1 · Y22) (7.6)

PWYYY = A ·WEN · (−L2 · Y11 + L2 · Y12 + L1 · Y21 − L1 · Y22) (7.7)

PLWYYY = A · LEN ·WEN · (Y11 − Y12 − Y21 + Y22) (7.8)

3. Coefficients for type III scaling

POYYY = A · (−L1 ·W2 · Y11 + L1 ·W1 · Y12 + L2 ·W2 · Y21 − L2 ·W1 · Y22) (7.9)

PLYYY = A · L1 · L2

LEN· (W2 · Y11 −W1 · Y12 −W2 · Y21 +W1 · Y22) (7.10)

PWYYY = A ·WEN · (L1 · Y11 − L1 · Y12 − L2 · Y21 + L2 · Y22) (7.11)

PLWYYY = A · L1 · L2 ·WEN

LEN· (−Y11 + Y12 + Y21 − Y22) (7.12)

Note: For L1, L2, W1, and W2 in the formulas above one must take the effective length and width (LE andWE) as defined in Section 3.2.

7.6.1 Binning of BETN

From PSP 103.0 onwards, the binning rule of BETN is changed to better match its typical scaling behavior.

• Extract the parameters POBETN, PLBETN, PWBETN, and PLWBETN for type I binning by applyingEq. (7.1)-(7.4) to (LE/WE) · BETN (i.e., not to BETN itself).



Section 8

DC Operating Point Output

The DC operating point output facility gives information on the state of a device at its operation point. Besideterminal currents and voltages, the magnitudes of linearized internal elements are given. In some cases mean-ingful quantities can be derived which are then also given (e.g., fT). The objective of the DC operating pointfacility is twofold:

• Calculate small-signal equivalent circuit element values

• Open a window on the internal bias conditions of the device and its basic capabilities.

All accessible quantities are described in the table below. The symbols in the ‘value’ column are defined inSection 4. Besides, the following notation is used: PD = 1 + kp ·G/4, where kp is defined in Eq. (4.24).

Important note: For all operating point output the signs are such as if the device is an NMOS. Moreover,whenever there is a reference to the ‘drain’, this is always the terminal which is acting as drain for the actualbias conditions. This is even true for variables such as vds (which is therefore always nonnegative) and thejunction-related variables. The output variable sdint shows whether or not this ‘drain’ is the same as theterminal which was named ‘drain’ in the simulator.

No. Name Unit Value Description

0 ctype – 1 for NMOS, −1 for PMOS Flag for channel-type1 sdint – 1 if V ′DS ≥ 0, − 1 otherwise Flag for source-drain interchange

Current components

2 ise A IS − IJS Total source current3 ige A IG Total gate current4 ide A ID − IJD Total drain current5 ibe A IB + IJS + IJD Total bulk current6 ids A IDS Drain current, excl. avalanche and

tunnel currents7 idb A Iavl + Igidl − IJD Drain-to-bulk current8 isb A Igisl − IJS Source-to-bulk current9 igs A IGCS + IGSov Gate-source tunneling current

10 igd A IGCD + IGDov Gate-drain tunneling current11 igb A IGB Gate-bulk tunneling current12 idedge A IDS,edge Drain current of edge transistor






13 igcs A IGCS Gate-channel tunneling current(source component)

14 igcd A IGCD Gate-channel tunneling current(drain component)

15 iavl A Iavl Substrate current due to weak-avalanche

16 igisl A Igisl Gate-induced source leakage cur-rent

17 igidl A Igidl Gate-induced drain leakage current

Junction currents

18 ijs A IJS Total source junction current19 ijsbot A IJS,bot Source junction current, bottom

component20 ijsgat A IJS,gat Source junction current, gate-edge

component21 ijssti A IJS,sti Source junction current, STI-edge

component22 ijd A IJD Total drain junction current23 ijdbot A IJD,bot Drain junction current, bottom

component24 ijdgat A IJD,gat Drain junction current, gate-edge

component25 ijdsti A IJD,sti Drain junction current, STI-edge

component

Voltages

26 vds V VDS Drain-source voltage27 vgs V VGS Gate-source voltage28 vsb V VSB Source-bulk voltage29 vto V VFB + PD · (φB + 2 · φ∗T) + G ·√

φ∗T · (φB + 2 · φ∗T)Zero-bias threshold voltage

30 vts V VFB+PD ·(V nudSB +φB +2 ·φ∗T)−V nud

SB +

G ·√φ∗T · (V nud

SB + φB + 2 · φ∗T)

Threshold voltage including back-bias effects

31 vth V vts−∆VG Threshold voltage including back-bias and drain-bias effects

32 vgt V vgs− vth Effective gate drive voltage includ-ing drain- and back-bias effects

33 vdss V Vdsat Drain saturation voltage at actualbias

34 vsat V VDS − Vdsat Saturation limit

(Trans-)conductances

35 gm A/V ∂ide/∂VGS Transconductance36 gmb A/V −∂ide/∂VSB Substrate-transconductance37 gds A/V ∂ide/∂VDS Output conductance






38 gjs A/V −∂ijs/∂VSB Source junction conductance39 gjd A/V −(∂ijd/∂VDS + ∂ijd/∂VSB) Drain junction conductance

Capacitances

40 cdd F ∂Q(i)D /∂VDS Drain capacitance

41 cdg F −∂Q(i)D /∂VGS Drain-gate capacitance

42 cds F cdd− cdg− cdb Drain-source capacitance43 cdb F ∂Q

(i)D /∂VSB Drain-bulk capacitance

44 cgd F −∂Q(i)G /∂VDS Gate-drain capacitance

45 cgg F ∂Q(i)G /∂VGS Gate capacitance

46 cgs F cgg− cgd− cgb Gate-source capacitance47 cgb F ∂Q

(i)G /∂VSB Gate-bulk capacitance

48 csd F −∂Q(i)S /∂VDS Source-drain capacitance

49 csg F −∂Q(i)S /∂VGS Source-gate capacitance

50 css F csg + csd + csb Source capacitance51 csb F ∂Q

(i)S /∂VSB Source-bulk capacitance

52 cbd F −∂Q(i)B /∂VDS Bulk-drain capacitance

53 cbg F −∂Q(i)B /∂VGS Bulk-gate capacitance

54 cbs F cbb− cbd− cbg Bulk-source capacitance55 cbb F −∂Q(i)

B /∂VSB Bulk capacitance56 cgsol F ∂(Qsov +Qofs)/∂VGS Total gate-source overlap capaci-

tance57 cgdol F ∂(Qdov +Qofd)/∂VDS Total gate-drain overlap capaci-

tance

Junction capacitances

58 cjs F CJS Total source junction capacitance59 cjsbot F CJS,bot Source junction capacitance, bot-

tom component60 cjsgat F CJS,gat Source junction capacitance, gate-

edge component61 cjssti F CJS,sti Source junction capacitance, STI-

edge component62 cjd F CJD Total drain junction capacitance63 cjdbot F CJD,bot Drain junction capacitance, bottom

component64 cjdgat F CJD,gat Drain junction capacitance, gate-

edge component65 cjdsti F CJD,sti Drain junction capacitance, STI-

edge component

Miscellaneous

66 weff m WE Effective channel width for geomet-rical models

67 leff m LE Effective channel length for geo-metrical models






68 u - gm/gds Transistor gain69 rout Ω 1/gds Small-signal output resistance70 vearly V |ide|/gds Equivalent Early voltage71 beff A/V2 2 · |ide|/vgt2 Gain factor72 fug Hz gm/[2 · π · (cgg + cgsol + cgdol)] Unity gain frequency at actual bias73 rg Ω RG Gate resistance

Noise

74 sfl A2/Hz Sfl(1 Hz) Flicker noise current spectral den-sity at 1 Hz

75 sqrtsff V/√

Hz√Sfl(1 kHz)/gm Input-referred RMS white noise

voltage spectral density at 1 kHz76 sqrtsfw V/

√Hz

√Sid/gm Input-referred RMS white noise

voltage spectral density77 sid A2/Hz Sid Channel thermal noise current spec-

tral density78 sig A2/Hz Sig(1 kHz) Induced gate noise current spectral

density at 1 kHz79 cigid –

migid√mig ·mid

Imaginary part of correlation coef-ficient between Sig and Sid

80 fknee Hz 1Hz · Sfl(1Hz)/Sid Cross-over frequency above whichwhite noise is dominant

81 sigs A2/Hz Sigs Gate-source current noise spectraldensity

82 sigd A2/Hz Sigd Gate-drain current noise spectraldensity

83 siavl A2/Hz Savl Impact ionization current noisespectral density

84 ssi A2/Hz SS,I Total source junction current noisespectral density

85 sdi A2/Hz SD,I Total drain junction current noisespectral density

86 sfledge A2/Hz Sfl,edge(1 Hz) Flicker noise current spectral den-sity of edge transistor at 1 Hz

87 sidedge A2/Hz Sid,edge Channel thermal noise current spec-tral density of edge transistor

Self heating

88 tk K TKD Device temperature89 pdiss W Pdiss Power dissipation90 dtsh K TKD − TKA Temperature rise due to self heating



From PSP 103.0 onwards, the values of local parameters are provided in the operating point output. They arelisted in the table below.

No. Name Unit Description

Process Parameters

0 lp_vfb V Local parameter VFB after T-scaling and clipping1 lp_stvfb V/K Local parameter STVFB after clipping2 lp_st2vfb K−1 Local parameter ST2VFB after clipping3 lp_tox m Local parameter TOX after clipping4 lp_epsrox – Local parameter EPSROX after clipping5 lp_neff m−3 Local parameter NEFF after clipping6 lp_facneffac – Local parameter FACNEFFAC after clipping7 lp_gfacnud – Local parameter GFACNUD after clipping8 lp_vsbnud V Local parameter VSBNUD after clipping9 lp_dvsbnud V Local parameter DVSBNUD after clipping

10 lp_vnsub V Local parameter VNSUB after clipping11 lp_nslp V Local parameter NSLP after clipping12 lp_dnsub V−1 Local parameter DNSUB after clipping13 lp_dphib V Local parameter DPHIB after clipping14 lp_delvtac V Local parameter DELVTAC after clipping15 lp_np m−3 Local parameter NP after clipping16 lp_toxov m Local parameter TOXOV after clipping17 lp_toxovd m Local parameter TOXOVD after clipping18 lp_nov m−3 Local parameter NOV after clipping19 lp_novd m−3 Local parameter NOVD after clipping


20 lp_ct – Local parameter CT after clipping21 lp_ctg V−1 Local parameter CTG after clipping22 lp_ctb V−1 Local parameter CTB after clipping23 lp_stct – Local parameter STCT after clipping

DIBL Parameters

24 lp_cf – Local parameter CF after clipping25 lp_cfb V−1 Local parameter CFB after clipping26 lp_cfd V−1 Local parameter CFD after clipping


27 lp_psce – Local parameter PSCE after clipping28 lp_psceb V−1 Local parameter PSCEB after clipping29 lp_psced V−1 Local parameter PSCED after clipping

Mobility Parameters

30 lp_betn m2/V/s Local parameter BETN after T-scaling and clipping31 lp_stbet – Local parameter STBET after clipping32 lp_mue m/V Local parameter MUE after T-scaling and clipping






33 lp_stmue – Local parameter STMUE after clipping34 lp_themu – Local parameter THEMU after T-scaling and clipping35 lp_stthemu – Local parameter STTHEMU after clipping36 lp_cs – Local parameter CS after T-scaling and clipping37 lp_stcs – Local parameter STCS after clipping38 lp_thecs – Local parameter THECS after clipping39 lp_stthecs – Local parameter STTHECS after clipping40 lp_xcor V−1 Local parameter XCOR after T-scaling and clipping41 lp_stxcor – Local parameter STXCOR after clipping42 lp_feta – Local parameter FETA after clipping


43 lp_rs Ω Local parameter RS after T-scaling and clipping44 lp_strs – Local parameter STRS after clipping45 lp_rsb V−1 Local parameter RSB after clipping46 lp_rsg V−1 Local parameter RSG after clipping


47 lp_thesat V−1 Local parameter THESAT after T-scaling and clipping48 lp_stthesat – Local parameter STTHESAT after clipping49 lp_thesatb V−1 Local parameter THESATB after clipping50 lp_thesatg V−1 Local parameter THESATG after clipping

Saturation Voltage Parameters

51 lp_ax – Local parameter AX after clipping


52 lp_alp – Local parameter ALP after clipping53 lp_alp1 V Local parameter ALP1 after clipping54 lp_alp2 V−1 Local parameter ALP2 after clipping55 lp_vp V Local parameter VP after clipping


56 lp_a1 – Local parameter A1 after clipping57 lp_a2 V Local parameter A2 after T-scaling and clipping58 lp_sta2 – Local parameter STA2 after clipping59 lp_a3 – Local parameter A3 after clipping60 lp_a4 1/

√V Local parameter A4 after clipping


61 lp_gco – Local parameter GCO after clipping62 lp_iginv A Local parameter IGINV after T-scaling and clipping63 lp_igov A Local parameter IGOV after T-scaling and clipping64 lp_igovd A Local parameter IGOVD after T-scaling and clipping65 lp_stig – Local parameter STIG after clipping






66 lp_gc2 – Local parameter GC2 after clipping67 lp_gc3 – Local parameter GC3 after clipping68 lp_chib V Local parameter CHIB after clipping

Gate-Induced Drain Leakage Parameters

69 lp_agidl A/V3 Local parameter AGIDL after clipping70 lp_agidld A/V3 Local parameter AGIDLD after clipping71 lp_bgidl V Local parameter BGIDL after T-scaling and clipping72 lp_bgidld V Local parameter BGIDLD after T-scaling and clipping73 lp_stbgidl V/K Local parameter STBGIDL after clipping74 lp_stbgidld V/K Local parameter STBGIDLD after clipping75 lp_cgidl – Local parameter CGIDL after clipping76 lp_cgidld – Local parameter CGIDLD after clipping


77 lp_cox F Local parameter COX after clipping78 lp_cgov F Local parameter CGOV after clipping79 lp_cgovd F Local parameter CGOVD after clipping80 lp_cgbov F Local parameter CGBOV after clipping81 lp_cfr F Local parameter CFR after clipping82 lp_cfrd F Local parameter CFRD after clipping

Noise Model Parameters

83 lp_fnt – Local parameter FNT after clipping84 lp_fntexc – Local parameter FNTEXC after clipping85 lp_nfa 1/V/m4 Local parameter NFA after clipping86 lp_nfb 1/V/m2 Local parameter NFB after clipping87 lp_nfc V−1 Local parameter NFC after clipping88 lp_ef – Local parameter EF after clipping

Edge Transistor Parameters

89 lp_vfbedge V Local parameter VFBEDGE after T-scaling and clipping90 lp_stvfbedge V/K Local parameter STVFBEDGE after clipping91 lp_dphibedge V Local parameter DPHIBEDGE after clipping92 lp_neffedge m−3 Local parameter NEFFEDGE after clipping93 lp_ctedge – Local parameter CTEDGE after clipping94 lp_betnedge m2/V/s Local parameter BETNEDGE after T-scaling and clip-

ping95 lp_stbetedge – Local parameter STBETEDGE after clipping96 lp_psceedge – Local parameter PSCEEDGE after clipping97 lp_pscebedge V−1 Local parameter PSCEBEDGE after clipping98 lp_pscededge V−1 Local parameter PSCEDEDGE after clipping99 lp_cfedge – Local parameter CFEDGE after clipping

100 lp_cfdedge V−1 Local parameter CFDEDGE after clipping101 lp_cfbedge V−1 Local parameter CFBEDGE after clipping






102 lp_fntedge – Local parameter FNTEDGE after clipping103 lp_nfaedge 1/V/m4 Local parameter NFAEDGE after clipping104 lp_nfbedge 1/V/m2 Local parameter NFBEDGE after clipping105 lp_nfcedge V−1 Local parameter NFCEDGE after clipping106 lp_efedge – Local parameter EFEDGE after clipping

Parasitic Resistance Parameters

107 lp_rg Ω Local parameter RG after clipping108 lp_rse Ω Local parameter RSE after clipping109 lp_rde Ω Local parameter RDE after clipping110 lp_rbulk Ω Local parameter RBULK after clipping111 lp_rwell Ω Local parameter RWELL after clipping112 lp_rjuns Ω Local parameter RJUNS after clipping113 lp_rjund Ω Local parameter RJUND after clipping

Self Heating Parameters

114 lp_rth K/W Local parameter RTH after T-scaling and clipping115 lp_cth J/K Local parameter CTH after clipping116 lp_strth – Local parameter STRTH after clipping

Junction Parameters

117 cjosbot F Bottom component of total zero-bias source junction ca-pacitance at device temperature

118 cjossti F STI-edge component of total zero-bias source junctioncapacitance at device temperature

119 cjosgat F Gate-edge component of total zero-bias source junctioncapacitance at device temperature

120 vbisbot V Built-in voltage of source-side bottom junction at devicetemperature

121 vbissti V Built-in voltage of source-side STI-edge junction at de-vice temperature

122 vbisgat V Built-in voltage of source-side gate-edge junction at de-vice temperature

123 idsatsbot A Total source-side bottom junction saturation current124 idsatssti A Total source-side STI-edge junction saturation current125 idsatsgat A Total source-side gate-edge junction saturation current126 cjosbotd F Bottom component of total zero-bias drain junction ca-

pacitance at device temperature127 cjosstid F STI-edge component of total zero-bias drain junction ca-

pacitance at device temperature128 cjosgatd F Gate-edge component of total zero-bias drain junction ca-

pacitance at device temperature129 vbisbotd V Built-in voltage of drain-side bottom junction at device

temperature130 vbisstid V Built-in voltage of drain-side STI-edge junction at device

temperature






131 vbisgatd V Built-in voltage of drain-side gate-edge junction at devicetemperature

132 idsatsbotd A Total drain-side bottom junction saturation current133 idsatsstid A Total drain-side STI-edge junction saturation current134 idsatsgatd A Total drain-side gate-edge junction saturation current

NQS Parameters

135 lp_munqs – Local parameter MUNQS after clipping



References

[1] L. Lemaitre, C. C. McAndrew, and S. Hamm ,“ADMS – Automatic Device Model Synthesize”, Proc.IEEE CICC, 2002. See also http://sourceforge.net/projects/mot-adms

[2] G. Gildenblat et al., “From BSIM3/4 to PSP: Translation of Flicker Noise and Junction Parameters”, avail-able for download at http://www.nxp.com/models/simkit/mos-models/model-psp.html

[3] X. Xi et al., BSIM4.4.0 MOSFET Model, User’s Manual, 2004, available for download at http://www-device.eecs.berkeley.edu/bsim/?page=BSIM4_Arc

[4] T.B. Hook et al., “Lateral Ion Implant Straggle and Mask Proximity Effect,” IEEE Trans. on ElectronDevices, Vol. 50, No. 9, pp. 1946-1951, 2003.

[5] X. Xi et al., BSIM4.5.0 MOSFET Model, User’s Manual, 2005, available for download at http://www-device.eecs.berkeley.edu/bsim/?page=BSIM4_Arc

[6] M. Basel, J. Watts et al., Guidelines for Extracting Well Proximity Instance Parameters, December 2006,available for download at http://www.si2.org/cmc_index.php

[7] R. Landauer, “Solid-state shot noise”, Phys. Rev. B, vol. 47, no. 24, pp. 16427–16432, 1993.

[8] G.D.J. Smit et al., “Experimental Demonstration and Modeling of Excess RF Noise in Sub-100-nmCMOS Technologies”, Electron Dev. Lett., vol. 31, no. 8, pp. 884–886, 2010.

[9] H. Wang, T.-L. Chen, and G. Gildenblat, “Quasi-static and Nonquasi-static Compact MOSFET ModelsBased on Symmetric Linearization of the Bulk and Inversion Charges,” IEEE trans. Electron Dev. 50(11),pp. 2262-2272, 2003.

[10] H. Wang et al., “Unified Non-Quasi-Static MOSFET Model for Large-Signal and Small-Signal Simula-tions,” CICC 2005.

[11] W. H. Press et al., “Numerical recipes in C”, 2nd edition, Cambridge University Press (1993), availablefor download at http://apps.nrbook.com/c/index.html

[12] A.J. Scholten et al., “JUNCAP2, version 200.3”, available for download at http://psp.ewi.tudelft.nl/

[13] M. Minondo, G. Gouget, and A. Juge, “New Length Scaling of Current Gain Factor and CharacterizationMethod for Pocket Implanted MOSFET’s,” Proc. ICMTS 2001, pp. 263-267, 2001.

[14] A.J. Scholten, R. Duffy, R. van Langevelde, and D.B.M. Klaassen, “Compact Modelling of Pocket-Implanted MOSFETs,” Proc. ESSDERC 2001, pp. 311-314, 2001.

[15] T.S. Hsieh, Y.W. Chang, W.J. Tsai, and T.C. Lu, “A New Leff Extraction Approach for Devices withPocket Implants,” Proc. ICMTS 2001, pp. 15-18, 2001.

[16] R. van Langevelde et al., “Gate Current: modelling, ∆L Extraction and Impact on RF Performance,”IEDM 2001 Tech. Digest, pp. 289-292, 2001.



Appendix A

Auxiliary Equations

In this Appendix, some auxiliary functions which are used in the model equations are defined.

The MINA-smoothing function:

MINA (x, y, a) =1

2·[x+ y −

√(x− y)

2+ a

](A.1)

The MAXA-smoothing function:

MAXA (x, y, a) =1

2·[x+ y +

√(x− y)

2+ a

](A.2)

The MNE- and MXE-smoothing functions:

MNE (x, y, ε) =2

A

[x+ y −

√(x+ y)

2 −A · xy]

(A.3)

MXE (x, y, ε) =2

A

[x+ y +

√(x+ y)

2 −A · xy]

(A.4)

A = 4− ε; ε ∈ (0, 1) (A.5)

The functions χ(y), its derivatives, σ1, and σ2, which are used in the explicit approximation of surface potential:

χ(y) =y2

2 + y2(A.6)

χ′(y) =4y

(2 + y2)2(A.7)

χ′′(y) =8− 12y2

(2 + y2)3(A.8)

ν = a+ c (A.9)

µ1 =v2

τ+c2

2− a (A.10)

σ1 (a, c, τ, η) =a · ν

µ1 + (c2/3− a) · c · ν/µ1+ η (A.11)



µ2 =v2

τ+c2

2− a · b (A.12)

σ2 (a, b, c, τ, η) =a · ν

µ2 + (c2/3− a · b) · c · ν/µ2+ η (A.13)



Appendix B

Layout parameter calculation

In post-layout simulations, various PSP instance parameters should be supplied either manually or by a layoutextraction tool. In this appendix, it is shown how these parameters should be calculated.

Note: These equations are not part of the PSP model.

B.1 Stress parameters

B.1.1 Layout effects for irregular shapes

For irregular shapes the following effective values for SA and SB are to be used (see Fig B.1).

1

SAeff + 0.5 · L=

n∑i=1

SWi

W· 1

SAi + 0.5 · L(B.1)

1

SBeff + 0.5 · L=

n∑i=1

SWi

W· 1

SBi + 0.5 · L(B.2)

B.2 Well proximity effect parameters

The values of the instance parameters SCA, SCB and SCC can be calculated from layout parameters using theequations below.

fA(u) =SCREF2

u2(B.3)

fB(u) =u

SCREF· exp

(−10 · u

SCREF

)(B.4)

fC(u) =u

SCREF· exp

(−20 · u

SCREF

)(B.5)

Acorner =

m+k∑i=m+1

(L

2·∫ SCXi+SCYi+W

SCXi+SCYi

fA(u) du

)

+

n+k∑i=n+1

(W

2·∫ SCXi+SCYi+L

SCXi+SCYi

fA(u) du

)(B.6)



Bcorner =

m+k∑i=m+1

(L

2·∫ SCXi+SCYi+W

SCXi+SCYi

fB(u) du

)

+

n+k∑i=n+1

(W

2·∫ SCXi+SCYi+L

SCXi+SCYi

fB(u) du

)(B.7)

Ccorner =

m+k∑i=m+1

(L

2·∫ SCXi+SCYi+W

SCXi+SCYi

fC(u) du

)

+

n+k∑i=n+1

(W

2·∫ SCXi+SCYi+L

SCXi+SCYi

fC(u) du

)(B.8)

SCA =1

W · L·

[n∑i=1

(Wi ·

∫ SCi+L

SCi

fA(u) du

)

+

n+m∑i=n+1

(Li ·

∫ SCi+W

SCi

fA(u) du

)+Acorner

](B.9)

SCB =1

W · L·

[n∑i=1

(Wi ·

∫ SCi+L

SCi

fB(u) du

)

+

n+m∑i=n+1

(Li ·

∫ SCi+W

SCi

fB(u) du

)+Bcorner

](B.10)

SCC =1

W · L·

[n∑i=1

(Wi ·

∫ SCi+L

SCi

fC(u) du

)

+

n+m∑i=n+1

(Li ·

∫ SCi+W

SCi

fC(u) du

)+ Ccorner

](B.11)

Here, m and n are the number of projections of the well edge along the length and width of the devices,respectively. Moreover, k is the number of corners selected to account for the ‘corner’ effects.



W

L

SW1SA1 SB1

SA2

SW3 SA3

SW2

SB3

SB2

Figure B.1: A typical layout of MOS devices with more instance parameters (SWi, SAi and SBi) in additionto the traditional L and W .

L

SC3

W4

W3

W1

W

SC6

SC5

SC1

SC2 SC4W2

SC7

L6

L5

Figure B.2: A typical layout of MOS devices with WPE instance parameters



SCX1

SCX2

SCX3SCX4

SCY1SCY2

SCY4

L

W

SCY3

Figure B.3: A layout of MOS devices for corner terms calculation


Documents

PSP 103 - CEA · 2018-01-15 · PSP 103.6 December 2017 — NXP / CEA-Leti to local and POGFACNUD, PLGFACNUD, PWGFACNUD, PLWGFACNUD, POVSBNUD and PODVSBNUD to binning models. Added