Module 5:Advanced Analog Design

2

PSoC’s enhanced analog features allow users to interface with the outside world, the analog world. This can take place through a variety of signal processing and sensor interface possibilities.

Examples:Signal Processing

Signals and Sensors

Amplitude detectionFrequency detectionModulation/DemodulationFilteringAnalog MultipliersFSK

Sensor InterfacingThermistorsPassive Infrared DetectorsUltrasonic ReceiversThermocouplesPressure sensorsStrain Gauges

This tele-training module will equip you with the tools to begin utilizing PSoC’s powerful analog resources.

3

Fundamentals

0εenclosedQSdE =⋅∫

0=⋅∫ SdB

dtdILdB EΦ

+=⋅∫ 000 εµµ

dtdLdE BΦ

=⋅∫

Every electrical interaction is governed by a simple set of equations:

Maxwell's Equations

and, because we're a Silicon company, particle movement is governed by:

The Schrödinger Wave Equation[ ] )()(

2

222

2

xxUEhm

dxd ϕ

π

ϕ−

⎟⎠⎞

⎜⎝⎛

−=

Don't Panic, it's not that hard.

4

Fundamental Fundamentals

Replace Maxwell and Schrödinger with simple laws:

RIE ⋅=Ohm's Law

Kirchoff's Law

Simple Algebra

Simple Physics

Nyquist Criterion

0=∑ I

bxmy +⋅=

RCf dB π21

3 =−

signalsample ff ⋅≥ 2

5

Op-amp AlgebraOp-amp behavior follows

two simple rules

1. Inputs draw no current.

2. The output will do whatever is necessary to make the voltage difference between the inputs equal to zero.

6

Op-amp Negative Gain

Simple op-amp algebra

VINV is 0 only whenVIN/Ri = -VOUT/Rf

VOUT/VIN = -Rf/Ri

RfRi

Vout

Vin VINVf

OUTINV

i

INVIN

RVV

RVV −

=−

7

Op-amp Positive Gain

Inputs draw no current, soVneg=Vout * Ri/(Ri+Rf)

Inputs can only be equal when

Vin=Vout*(Ri/(Ri+Rf)

Vout/Vin = 1 + Rf/Ri

RiRf

Vin

Vout

8

Sine Wave

Examine signal examples

Sine waveSingle frequencyZero intentional harmonics

9

Square Wave

Square waveHarmonics amplitude 1/n

10

Triangle WaveTriangle wave

Harmonic amplitude 1/n2

Sampling dataHarmonics may add in

and distort the resultAliases at sample rate add

image terms

11

Sampling

Whether its ADCs or filters, when we think of analog user modules we think of signals and sampling

-1

-0.5

0

0.5

1

1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5

t

V(t)

12

SamplingSampling the signal

Quantize the Signal Amplitude

Definitions:Range := The allowable input voltage.Resolution := Range/ Number of Quantization Steps

For a “n” bit Converter:Number of Quantization Steps := 2n

Resolution also known as “LSB” or “∆”

-1

-0.5

0

0.5

1

1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5

t

V(t)

13

SamplingSampling the signal

Quantize the Signal Amplitude

Quantize the Time Domain

Definitions:Sample Rate “fs”Expressed as samples per second “sps”. Not Hz!

-1

-0.5

0

0.5

1

1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5

n

V(n)

14

Time Domain QuantizationNyquist in a Nutshell

The Output Signal Frequenciesall map in the range of :

20 s

outff ≤≤

This upper bound is know as the Nyquist limit.

Any input frequencies meetingthis requirement are accuratelyreproduced.

( )20, sfininout fff ≤≤=

3KHz Signal Sampled at 10ksps

15

Time Domain QuantizationNyquist in a Nutshell

Input frequencies greater than the Nyquist limit result in output frequencies that map (alias) into the 0 to Nyquist limit range.

Given a sample rate of 10ksps, input signal with frequencies of 1kHz, 9kHz,11kHz,19kHz. & 21kHz are all going to map to an output frequency of 1kHz.

( )( )⎩

⎨⎧

≤−≤−≤−≤−

=2

2

)(0,)(0,

s

s

finsin

finsins

out ffffffff

fαα

αα

With the whole spectrum mapped into a small bandwidth, a filter is required to select the desired input frequency. It is referred toas an “anti alias” filter.

7KHz Signal Sampled at 10kspsOutput mapped to 3kHz

16

Sampled Sine Wave IExample shown using BPF, but results

are same for LPF or DAC generated signal

Filtered waveform example is sampled approx 7 times per cycle

PSoC filter adds 0.025% distortion (-72 dB) at 2nd harmonic

Sampling process adds first alias at fsample-fsignal = -16 dBSampling process adds other images

Sampling image

2nd Harmonic

17

Sampled Sine Wave II

Filtered waveform is sampled approx 17 times per cycle

Harmonic distortion same as waveform with Over-Sample Ratio (OSR) = 7

First alias reduced by 9 dBSubsequent aliases are smaller

Alias images occur as sin(x)/xIncreased OSR moves sin(x)/x

function closer to null and lowers image level -- (simple algebra)

Sampling alias2nd harmonic

18

ReconstructionFor output waveform, add R-C filter

(simple physics)Set R-C corner at half of sample

frequencyReduces first alias image by 10 dB

(factor of 3)Reduces subsequent alias images

even moreTechnique applies to either filter or DAC

Not necessary when signal is being digitized for internal use

Sampling alias

2nd Harmonic

19

PSoC Design Fundamentals

What is THE essential element of PSoC analog design?• Power Consumption?• Accuracy?• Frequency Response?• Signal to Noise Ratio?

wrong

TopologyHook it up first.Then worry about how well it works

20

Analog Block Organization4 Continuous Time (CT) Blocks8 Switched-Cap (SC) BlocksProgrammable I/O

4 input mux per column1 of 8 mux in two columns

Selectable clocksClock mux per columnDigital block or system clock source

Buffered out each columnComparator bus each columnSelectable references

AnalogSC C

AnalogSC D

AnalogSC C

AnalogSC C

AnalogSC C

AnalogSC D

AnalogSC D

AnalogSC D

AnalogCT

AnalogCT

AnalogCT

AnalogCT

CBus0 CBus1 CBus2 CBus3

ABuf0 ABuf1 ABuf2 ABuf3

21

Building Blocks:Analog User ModulesProgrammable controls are SRAM register based

CT: 4 registers per blockSC:4 registers per block

Functionality controlled by SRAM-based registersRapidly updated via software

Turn slow PGA into fast comparator in less than 1 microsecondAllows for Dynamic ReconfigurationMultiple configurations supported in design tool

Multiple blocks combine to form complex functionsAmplifiersMultiple byte DACsFiltersADC (with timer and counter)

22

Continuous Time Analog

CT Block configured from op-amp, resistors and switch array

DC open loop gain > 80 dBOp-amp Unity GBW > 9 MHzOp-amp slew rate to 8 V/usResistor matching < 0.5%

VDD

CBUS

RES

ISTO

RM

ATR

IX

References

OUT

ABUS

23

PGA TopologyBasic Gain Equation

A

B

IN

OUT

RR

VV

+=1

but, Ground isn't necessarily Zero

( ) GNDa

bGNDINO V

RR

VVV +⎟⎟⎠

⎞⎜⎜⎝

⎛+⋅−= 1

PGA ref selectable (Choose in globals – Ref Mux)

AGNDVSS (real Zero)

RB

RA

VOUT

VIN

GNDRef

24

PGA Gain Range

Gain referenced to AGNDUsed for

AC signals

RB

RA

VOUT

VIN

AGND (2.6V)

Gain referenced to VssUsed for

Low-side current measurementsGround referenced signals

RB

RA

VOUT

VIN

Vss (0.0V)

0

1

2

3

4

5

6

0 1 2 3 4 5V(in)

V(out)

G=8G=2

0

1

2

3

4

5

6

0 1 2 3 4 5V(in)

V(out)

G=8G=2

25

PGA Bandwidth

PGA bandwidth determined byOp-amp open loop gainShunt feedback cap (CF = 1 pF)

and feedback resistor

RB

RA

VOUT

VIN

AGND

CF

PGA Freq Response, Power=High, Bias=High

-5

0

5

10

15

20

25

30

35

1 10 100 1000 10000Freq (kHz)

Gai

n (d

B)

G=48G=24G=16G=8G=4G=2

26

INSAMP (2 op-amp)Differential gain

High input impedance

Common mode rejection > 59 dB

RaRb

RbRa

Reference

+ IN

- IN

AGNDVss

SC Blk

A_Bus

Out

AbusOut

Vin Range: Vcc=5V, AGND=2*Vbg

0

1

2

3

4

5

2.00

2.29

2.67

3.20

4.00

5.33

8.00

16.0

0

Gain

Max Vin

Agnd

Min Vin

( ) REFa

bININOUT V

RRVVV +⎟⎟

⎠

⎞⎜⎜⎝

⎛+−= −+ 1

27

INSAMP (3 op-amp)

Input stage hasHigh differential gainUnity common mode gain

Improved performance over INSAMP(2 opamp)Slightly Improved CMRRWider input range

Synchronize with ADC

ASIGN

AGnd

Switchesomitted forclarity

AnalogOut

+ IN

- IN

0.01

0.1

1

10

1.00

2.00

3.20

4.00

8.00

16.0

0

24.0

0

48.0

0

Gain

Vdiff

in m

ax

Vcm=2.53.03.54.04.5

( ) AGNDf

a

a

bININOUT V

CC

RRVVV +⎟⎟

⎠

⎞⎜⎜⎝

⎛+−= −+ 1

28

Comparators

CompBusVcc

Vin

CompBusAGND

Vin

Programmable thresholdRef to Vss for P/S current sense

Zero crossingFSK and doppler processing

Programmable hysteresisNoise rejection

CompBus

Vin

AGND

Vref

29

Switched Cap TechnologyResistor is replaced

φ1 φ2

CfR

S

1=

30

Switched Cap TutorialThe switched cap block has two discrete phases of operation:

φ1 Acquisition of signals

φ2 Transfer of charge

φ2

φ1

φ2

φ1

φ1

Vos

Vout

VinCi

Cf

31

Switched Cap TutorialDuring Phi 1, switches are closed to:

Place Vin on one side of CiShort the output to the negative input and place Voson Ci and Cf

Short the output side of Cf to ground

φ2

φ1

φ2

φ1

φ1

Vos

Vout

VinCi

CfVin

0

32

Switched Cap TutorialBetween Phase 1 and Phase 2

All switches are open.This stores

Vin - Vos on Ciand

-Vos on Cf

φ2

φ1

φ2

φ1

φ1

Vos

Vout

VinCi

CfVin

0

33

Switched Cap TutorialPhase 2 Transfer of Charge

With φ2 open, the input to Ci was at Vin

When φ2 is shorted, charge equal to Ci*Vin is pulled out of Ci

The output must supply an equal amount of charge to Cf, so:

Vout = (1/Cf)* Ci * Vin

Vout/Vin = Ci/Cf

φ2

φ1

φ2

φ1

φ1

Vos

Vout

VinCi

Cf

34

Switched Cap PSoC Block CProgrammable op-ampSupports ∆−Σ and Incremental ADCSupports differential ampConfigurable as input half of biquad filter

CA Inputs

REF Inputs

SN

OBUS

CBUS

A.IN

C.IN

CCInputs

CB Inputs

A.SIGNA.REF

B.IN

CC0-31 C

CB0-31 C

CA0-31 C

CF16-32 C

φ1*!AZφ2

φ2

φ2+AZ

φ1*AZ

φ1

(φ2+!AZ)*F.IN1

φ1*F.IN0

PWR

OS*φ2B

CS

φ1

35

Switched Cap PSoC Block D

Programmable op-ampSupports ∆−Σ and Incremental ADCConfigurable as output half of biquad filter

CA Inputs

REF Inputs

OBUS

CBUS

A.IN

CARR

CB Inputs

A.SIGNA.REF

B.IN

CC0-31 C

CB0-31 C

CA0-31 C

CF16-32 C

φ2

φ1*AZ

φ1 (φ2+!AZ)*F.IN1

φ1*F.IN0

PWR

OS*φ2B

CS

φ1*!AZ

φ2+AZ

φ1*B.SW

φ2+!B.SW

φ1*B.SW

φ2+!B.SW

36

Switched Cap DAC

Output is NOT rail to railDAC6 example

VAGND +/- VREF=VBG +/- VBG

VOUT(MAX) = VBG + VBG*31/32= 2.559V

VOUT(MIN) = VBG - VBG*31/32= 0.041V

Analog column output buffer will further limit output swing, see AN2089

φ1

φ2

CA

CF

φ1

φ2

VREF

VOUT

φ2

F

AREFAGNDOUT C

CVVV −+= /

37

SCBlock as ComparatorTwo Cap ComparatorWith feedback capacitor CFremoved Vout goes to either the high or low rail.

Vout goes high whenVinACA > VinBCB

Vout goes low whenVinACA < VinBCB

VinB is the inverting input input.

φ1

φ2

CA

φ1

φ1φ2

VinAVout

CB

VinB

38

PSoC ADCsThe PSoC offers flexible resources allowing the

construction of several types of ADCs.

Each project’s unique System Requirements:ResolutionBandwidthHardware Utilization (digital blocks)CPU loadingInterrupt loading

Determine which ADC (or ADCs) makes for thebest fit.

39

Choices, choices, choicesTrade-offs

ResolutionSample Rate% CPU UsageStart LatencyBlock CountPowerInterrupt LatencyGain ErrorsLinearity (INL, DNL) NoiseRAM ConsumptionFLASH Consumption

40

Realistic ADC Types

Three types of PSoC ADCsSAR (Successive Approximation Register)

Minimum block countSubject to aliasing errors

IncrementalIntegrates noise, slowEnables multiple instances (Dual, Triple)

Delta SigmaIntegrates noiseFast, continuous samplingUses decimator, "There can be only one . . ."

41

SAR (Successive Approximation Register)

Single Comparator & DACDAC resolution determines ADC

resolutionLogic determines how quickly DAC

zeros-in on input valueBinary search allows “n” bit DAC to

reach to best value in “n” attempts

The “Successive Approximation Register” (SAR) is a binary search algorithm

Comparator

DAC

Vin

logic

VDAC

42

Incremental ADC

φ2

φ1φ1*Reset

φ2

φ1

Ref+Ref-

CF

VinCA

SCBlock

÷4φ1,φ2

generator

φ1

φ2

Counter8

Timer8

DataClock

Enable Int

Int

To CPU

To CPU

DataBus

Constructed from:SCBlock Analog ModulatorTimer to set the number of

integration cyclesCounter to accumulate the number

of comparator high cycles

A 12 bit ADC needs12 bit counter12 bit timer÷4 Clock generator

ADCINCUses decimator instead of counter,

only one at a timeADCINCVR

Variable resolutionDual and triple available

43

Incremental ADCADCINC (12 bit)Not a 12 bit converter.

Average of 4096 single bit conversions .

Nyquist limit determined by the sampling frequency

(Remember fs =fdataclock/4).

Output RatefADCout= fdataclock /16640

Nyquist FrequencyfNyquist= fdataclock /8

Aliasing not a problem until nearNyquist rate

-3dB bandwidth = .44*Output Rate

DataClock =4*409600sps (100sps SampleRate)

-80

-60

-40

-20

0

25 50 100

200

400

800

1600

3200

6400

12800

25600

51200

102400

204800

409600Frequency (Hz)

dB

NyquistLimitOutput Rate

Sample Rate

-3 dB freq.

44

Delta Sigma ADCConstructed from:

SCBlock analog modulatorSingle digital blockOn-chip decimator replaces

counter in Incremental

Pipelined ADCOutput rate reduced for

multiplexed inputsOne decimator = one Delta

Sigma ADC per system

φ2

φ1φ1*Reset

φ2

φ1

Ref+Ref-

CF

VinCA

SCBlock

÷4φ1,φ2

generator

φ1

φ2

Decimator

Timer8

DataClock

Data

Out

DataBus

Decimator Latch

Int

45

Delta Sigma 2nd Order ModulatorEquivalent to a 2 pole filter

Lower noiseHigher allowed clock rateFaster conversion

φ1

Ref+ Ref-

Reset

φ2

φ1φ2

Vinφ1

Ref+ Ref-

Reset

φ2

φ1φ2 ∼φ2

Cmp

46

ADC Summary 26xxx, 24/27/29xxx

Sample Rate vs Resolution, clock = 8.0 MHz

100

1000

10000

100000

5 6 7 8 9 10 11 12 13 14 15Resolution

Max SPS

INC_1INC_2DS_1DS_2SAR29x only

INC_2, DS_2 (double modulator) not in 25/26xxx

INC_2 6,7,8 bit at 12 MHz clock (in addition to 8MHz)

47

ADC Summary 26xxx, 24/27/29xxxMax CPU Load (%) vs Resolution, FCPU=24 MHz

1

10

100

5 6 7 8 9 10 11 12 13 14 15Resolution

%

INC_1INC_2DS_1DS_2SAR29x only

Logically, longer sample times and fixed size data handling code mean lower % CPU usage

SAR stalls CPU

INC_2 6,7,8 bit at 12 MHz clock

29xxx decimator saves a lot of CPU overhead

48

Start LatencyDelta Sigma converters are pipelined

Data is smeared from adjacent samples by decimator

First two samples after start are in errorCuts multiplex rate by factor of 3

ADCINC also uses Decimator, butReset at start of conversion eliminates

smearing and start latencyDecimator serves counter function, saves a

block

49

Block Count/PowerAnalog and digital block usage listed in User Module

data sheetsADCINC uses decimator

Saves digital block compared to ADCINCVRNot available as dual or triple

ADCINCVR has adjustable rate, but more blocksMost of power consumption in analog blocksDouble modulator ADCs consume double power,

reasonable price to pay for:Higher speedLower noise

50

ADC NoiseQuantization noise = 0.288*Range/resolutionWhat's a half bit? . . . . A little higher noise

DelSig decimate by 64 listed as 7.5 bitsOutput is 8 bits with higher noise on LSB

DelSig decimate by 256 listed as 10.5 bitsOutput is 11 bits with higher noise on LSB

Double modulator ADCsLower noise than single modulator typesHigher non-linearity at ends of scale

51

Selection Process1. Select chip (25/26xxx or 24,27,29xxx)

Prefer 24/27/29xxx for MUCH lower noise

2. Select resolution

3. Select sample rate

4. Choose: continuous data or triggered dataContinuous data: DelSigTriggered data: ADCINCSlow signal, low resolution: SAR6

5. Verify CPU load and interrupt structure

6. Verify block availability

52

ADC PerformancePSoC ADCs are well characterized

Non-linearities generally lower than quantization noise when operated at specified clock rates

ADC Acquistion RatesConsistent with signal processing bandwidth of PSoC

Exact rates (e.g., 1.000 ksps)Achievable with ADCINCVRs by changing calculation timeADCINC not adjustable with internal clock

DelSig ADCs with non-integer divider clock ratesAchievable by changing PWMCauses slight gain error (seeAN2095 on u-Law example)

53

Clock Considerations

User Modules with both analog and digital blocks (ADCs and DACs) require same clock to all blocks.

Clock signal is divided by 4 in the mux to set sample rate

User Module datasheets’ “Parameters” section lists equations and explanations to help guide clock settings

54

Clock Limitations

User Module Column ClockDAC8, DAC9, MDAC8 ≤ 500 kHz

DAC6, MDAC6 ≤ 1 MHz

Switch-Cap Comparators ≤ 2 MHz

Filters ≤ 6 MHz

Delta Sigma ADCs ≤ 8 MHz

Incremental ADCs ≤ 8 MHz

55

DAC Clock ConsiderationsDAC User Module Datasheets specify that the Column

Clock is 4 times the output update rate.

DAC8, DAC9, and MDAC8Max output update rate = 125 ksps

DAC6 and MDAC6Max output update rate = 250 ksps

56

Clock ConsiderationsDelta Sigma ADCs ≤ 8.0 MHz

Linearity is improved for ADC clock ≤ 2.0 MHz

DELSIG8 DataClock = SampleRate × 256DELSIG11 DataClock = SampleRate × 1024

DELSIG8 ExampleMax Sample Rate = 31.25 ksps31,250 × 256 = 8 MHz

DELSIG11 ExampleMax Sample Rate = 7.8 ksps7,800 × 1024 ≈ 8 MHz

57

Clock Considerations

Incremental ADCs ≤ 8 MHz

Governing Equations:*

ADCINC12 DataClock = SampleRate × 65 × 256ADCINC14 and ADCINCVR DataClock specified as ≤8 MHz in User Module Data Sheets

ADCINC12 ExampleMax Sample Rate = 480 sps480 × 65 × 256 ≈ 8 MHz

* See User Module Data Sheets

58

Reference Structure

PSoC is Single Supply, so ...

Establish Artificial Ground (called "Analog Ground") at mid-supply

Establish Reference used for ADC, DAC

VBandGap = 1.300 +/- 0.02 V

Selectable ground and reference

VBandGap for absolute voltage systems

Vdd/2 for supply ratiometric systems

External VREF for increased flexibility

59

Ground + Reference ValuesPrecision Base Reference

VBandGap Tolerance1.5% worst case over tempExcellent P/S rejection

Reference Offsets< 50 mVSets system accuracy

References for "Real Signals"Scale 0.0 to 4.0V

Agnd= 2.0VRef=+/-2.0V

Scale 0.0 to 2.6VAgnd=VBG (1.3V)Ref=+/-VBG (1.3V) Vcc/2

+/-VBG

Vcc/2+/-

Vcc/2

Vcc/2+/-

Vcc/2

P2.4+/-

P2.6

2*VBG+/-VBG

+/-

Vcc = 5.00V

Vcc = 3.30V

Vcc/2+/-

P2.6

1.6*VBG+/-VBG

VBG 1.6*VBG

60

Reference / Ground Structure

There is no massive ground plane as in a normal good board designDistributed ground to eliminate crosstalkRequires careful system and power design

Ground buffer offset adds to error budget

VbandgapP2[6]

P2[4]Vdd/2

Vdd

Vss

P2[4] (External Cap)

RefHI toAnalogBlocks

RefLO toAnalogBlocks

AGND

2*Vbandgap

X1X

1.6X2

X1

61

Analog Ground BypassExternal cap connection

Bypass internal distributed ground

Reduces noise to ground buffers in analog blocks

Analog block ground buffer noise remains

ApplicationAudio to ultrasonic

signal processing

P2.6

P2.4

Vcc/2

Vcc

VssX12Ground Buffer ineach Analog Block

RefHI

DistributedGround

RefLO

AGND

VBG

P2.4i/o

40k 2k

VNAGND

Ext1 uF

100

1000

10000

0.001 0.01 0.1 1 10 100Freq (kHz)

dBV/rtHz

00.010.11.010

62

Filters: Application ExamplesTransmit Generation

FSK Generation per AN2095Coin Detector: 1-10 kHz swept BPF

Receive ProcessingIR: 38 kHz BPFVideo Sync Detector: 15 kHz BPFFish Finder: 180 kHz BPF, 20 kHz LPFPhone Modem: 1.8-2.2 kHz BPF4Power Line Modem: 133 kHz BPF4, 12 kHz BPF2, 3 kHz LPFU/S Motion Detector: 40 kHz BPF, 10 kHz LPFCoin Detector: Synchronous with transmit

63

Filters: Design PossibilitiesCurrently available User Modules:

Low Pass 2 poleBand Pass 1 pole-pair

Others in work include:Low Pass 4 poleBand Pass 2 pole-pairEllipticalNotchHigh Pass

Select filter design to meet attenuation requirements

Balance design goals with side effectsIn-band amplitude and phase performanceOut-of-band amplitude and phase performancePulse rise time and overshoot characteristic changesSampling alias/images

64

Continuous Time FiltersPSoC’s Analog System consists of both Switch Cap and Continuous

Time Blocks. There are filter options for both sets of blocks

Continuous Time Filters:

Implement standard Sallen + Key topologyProgrammable gain stage simplifies designDesign methodology well knownRequires 4 external passive componentsHPF and LPF design spreadsheets in app notes

Especially useful for anti-aliasing filters

65

Continuous Time Low Pass Filters

Use PGA as fixed gain block with passive R + C

Design equations VERY standardEvery analog IC company has

a filter design program

Primary use:Anti-alias filtersRemember aliases in signal

description?Aliases also occur in ADC,

adding to noise bandwidth --so it's important to suppress out-of-band noise

VinR1

C4

C3R2

Vout

+KC3

R2R1

C4

VoutVin

66

Continuous Time High Pass Filters

Preferred over switched-cap high pass filterWider upper frequency limitNo errors due to low samplingConsider switched-cap BPF

Filter shape is adjustableUses additional PGA UM

Additional ResourcesAN2030 - Adjustable Sallen and Key High-Pass FiltersAN2031 - Adjustable Sallen and Key Low-Pass FiltersAN2099 - Single-Pole IIR Filters

VinC1

R4

R3C2

Vout

AGND

+KR3

C2C1

R4

VoutVin

67

Switched Capacitor FiltersStandard Topologies

Low Pass, Band Pass, Notch, High PassRC Biquad maps to Switched Capacitor Blocks

Scalable, Programmable, Connectable

Vin Vout

R2

R1

C4

CB

R3

CA

1

1

φ2

φ2φ2

φ2

φ2 φ2φ1

φ1φ1φ1

Vin

Vout

C1C3

C4

CB

C2

CA

φ1

68

Filter PlacementLPF2

Input on A BlockOutput on B Block

BPF2Input on A BlockOutput on A BlockComparator to Bus

φ2

φ2

φ2

φ2 φ2

φ1

φ1

φ1φ1

Vin

Vout

C1

C3

C4

CB

C2

CA

φ1

AnalogBus

CompBus

φ2

φ2φ2

φ2

φ2 φ2φ1

φ1φ1φ1

Vin

Vout

C1C3

C4

CB

C2

CA

φ1

69

Filter Placement Input on A-cap

Allows use of modulatorEnables elliptical or notch filter (UM

delivered later)Input on B-cap

No modulatorInputs through Mux or direct on P2.x

BPF placements similarOutput on same block as inputChainable to BPF or LPF

Eliptical and Notch horizontal only

AB

US

(3)

P2.2

P2.1

AB

US

(1)

ASB20

ASA21

ASB22

ASA23

ACA00

ACA01

ACA02

ACA03

ASA10

ASA12

ASB13

ASB11

P2.2

ABU

S(3)

ABU

S(1)

P2.1

ASB20

ASA10

ASA12

ASB13

ASA21

ASA23

ASB22

ACA00

ACA02

ASB11

ACA01

ACA03

70

Low Pass Filter

⎟⎟⎠

⎞⎜⎜⎝

⎛−−

+

⎟⎟⎠

⎞⎜⎜⎝

⎛−−

+

⎟⎟⎠

⎞⎜⎜⎝

⎛−−

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛−

−

=

2

4

32

2

2

4

32

2

42

2

4

32

22

21

41

21

41

21

41

21

21

CC

CCCC

f

CC

CCCC

sfCC

s

CC

CCCC

ffs

CC

VinVout

BA

S

BA

S

BA

SS

Programmable -3 dB point and d

300 Hz to 150 kHzScaled to clock

φ2

φ2φ2

φ2

φ2 φ2φ1

φ1φ1φ1

Vin

Vout

C1C3

C4

CB

C2

CA

φ1

71

Band Pass Filter

φ2

φ2

φ2

φ2 φ2

φ1

φ1

φ1φ1

Vin

Vout

C1

C3

C4

CB

C2

CA

φ1

AnalogBus

CompBus

Programmable Q and fc300 Hz to 150 kHzScaled to clockZero-crossing output for

energy detector applications

⎟⎟⎠

⎞⎜⎜⎝

⎛−−

+

⎟⎟⎠

⎞⎜⎜⎝

⎛−−

+

⎟⎟⎠

⎞⎜⎜⎝

⎛−−

⎟⎟⎠

⎞⎜⎜⎝

⎛+

−

=

2

4

32

2

2

4

32

2

42

2

4

32

32

1

21

41

21

41

21

41

21

CC

CCCC

f

CC

CCCC

sfCCs

CC

CCCC

ffss

CC

CC

VinVout

BA

S

BA

S

BA

SSB

72

Elliptical Low Pass FilterNotch can be tuned above or below

low pass corner

Ratio of fzero to f-3dB limits above attenuation above fzero

Can be combined with additional sections

⎟⎟⎠

⎞⎜⎜⎝

⎛−−

+

⎟⎟⎠

⎞⎜⎜⎝

⎛−−

+

⎟⎟⎠

⎞⎜⎜⎝

⎛−−

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛−⎟⎟

⎠

⎞⎜⎜⎝

⎛+

−

=

2

4

32

2

2

4

32

2

42

2

4

32

2

31

2

21

41

21

41

21

41

41

21

21

CC

CCCC

f

CC

CCCC

sfCC

s

CC

CCCC

fCCCC

fs

CC

VinVout

BA

S

BA

S

BA

SAPP

S

φ2

φ2φ2

φ2

φ2 φ2φ1

φ1φ1φ1

Vin

Vout

C1C3

C4

CB

C2

CA

φ1

CPP

73

Notch FilterSpecial case of elliptical

low pass where: ωzero = ωpole

Band pass gain of Q in first stage limits maximum signal

⎟⎟⎠

⎞⎜⎜⎝

⎛−−

+

⎟⎟⎠

⎞⎜⎜⎝

⎛−−

+

⎟⎟⎠

⎞⎜⎜⎝

⎛−−

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛−⎟⎟

⎠

⎞⎜⎜⎝

⎛+

−

=

2

4

32

2

2

4

32

2

42

2

4

32

2

31

2

21

41

21

41

21

41

41

21

21

CC

CCCC

f

CC

CCCC

sfCC

s

CC

CCCC

fCCCC

fs

CC

VinVout

BA

S

BA

S

BA

SAPP

S

φ2

φ2φ2

φ2

φ2 φ2φ1

φ1φ1φ1

Vin

Vout

C1C3

C4

CB

C2

CA

φ1

CPP

74

Multi-Section FiltersTwo poles per block pairUp to 8 poles using all switched-cap, but leaves

nothing left for ADC or DACCan be combined with CT-based Sallen + Key

75

Design MethodsFilter Wizards included in PSoC Designer

Right click on a filter (once placed) to access the filter wizard

Available as LPF, BPF 2 and 4 pole versions .xls inCypress MicroSystems/PSoC Designer/Documentation/Filter Design

76

Filter Sampling Effects - WarpingSample rate causes a phase delay, lowers filter corner frequency

Corrected by biasing filter higher by 2*fS/fC*tan-1(πfC/fS)Over-sample ratios >20 add very little error

Compensation built into design .xls and wizards

1.00

1.05

1.10

1.15

1.20

1.25

1 10 100

77

Filter Sampling Effects - PeakingComplex zeros (in numerator of transfer function) peak the

response and limit the asymptotic attenuationCompensation built into design .xls and wizards

⎟⎟⎠

⎞⎜⎜⎝

⎛−−

+

⎟⎟⎠

⎞⎜⎜⎝

⎛−−

+

⎟⎟⎠

⎞⎜⎜⎝

⎛−−

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛−

−

=

2

4

32

2

2

4

32

2

42

2

4

32

22

21

41

21

41

21

41

21

21

CC

CCCC

f

CC

CCCC

sfCC

s

CC

CCCC

ffs

CC

VinVout

BA

S

BA

S

BA

SS

-80

-60

-40

-20

0

20

100 1000 10000 100000 1000000Freq (Hz)

dB

NominalNet, OSR=140

Net, OSR=70

Net, OSR=35

Net, OSR=10

Peak, OSR=140

Peak, OSR=70Peak, OSR=10

Peak,OSR=35

78

Switched Capacitor BlockFunctions: ExamplesGain Invert Block

Equivalent to MDAC

Invert Signal Polarity

When CA=CF then gain is -1 Both samples and outputs on

φ2.Can be strung together

Functions as a bus to route a signal from one side of the analog columns to the other.

System Gain Inversion

φ2

φ1

CA

CF

φ1

φ1

φ2

Vin

Vout

79

SCBlock Amplifier ExamplesBi-Directional Current SourceDiffAmp configured with gain of one.

CF=CB=CA=16Sign = Pos

External Resistor and DAC value sets current.

Independent of load.

•DAC6

DiffAmpBuf0

P0.3P2.1Vload

Vset

Vout

Rset

+A

-B

i = -Vset / Rset

Rload

x1

setloadout VVV −=

set

set

set

loadout

RV

RVVi −=

−=

80

SCBlock as IntegratorSCBlock IntegratorUses standard gain stage with the exception that the switch to discharge CF has been disabled.So:

φ1

φ2

CA

CF

φ1

φ2

Vin

VoutF

Ainoutout C

CVVVold+=

sCCf

VV

F

As

in

out 1⋅⎟⎟⎠

⎞⎜⎜⎝

⎛= 12 −= fs π

81

SCBlock as IntegratorSC Integrator(Doing an Op Amp’s Job)

Negative Gain Integrator closely resembles a positive input grounded open loop op amp.

( )s

GBWVV

Opampin

out 12π−≈⎟⎟⎠

⎞⎜⎜⎝

⎛

φ1

φ2CA

CF

φ1

φ2

Vin

Vout

Vin Vout

sCCf

VV

F

As

SCIntin

out 1⎟⎟⎠

⎞⎜⎜⎝

⎛−=⎟⎟

⎠

⎞⎜⎜⎝

⎛

82

SCBlock Integrator - Faux Op AmpSC IntegratorFaux Opamp

This circuit is an inverting amplifier and single pole low pass filter.

Its gain is determined with external resistors.

The bandwidth is determined withSwitched Capacitor Values.External ResistersSample Frequency

φ1

φ2CA

CF

φ1

φ2

Vin buf

Rf

Rin

Vin Vout

⎟⎟⎠

⎞⎜⎜⎝

⎛++

⎟⎟⎠

⎞⎜⎜⎝

⎛−=⎟⎟

⎠

⎞⎜⎜⎝

⎛

in

f

F

A

s

in

f

SCIntin

out

RR

CC

fsR

RVV

11

1

83

SCBlock - Opamp

Rin

Rf

100k

100k

Vout

Vin

CT Op Amp can be unstable in this mode

84

SCBlock - Peak DetectorDual Input SC Integrator

Feedback through diode and capacitor makes a Peak Detector.

φ1

φ2

CA

CF

φ1

φ2

Vin

Vout

φ1

φ2CB

buf

CextResetusingGPIO

Vpk

0

1

2

3

4

5

Volts

Vout

Vpk

Vin

85

SCBlock - High Current SourceDual Input SC IntegratorOr a Single Block Programmable High Power Current Source.

•

set

AHighsign

load R

AGNDCRefAI

+= 31

RefHiφ1

φ2

CA

CF

φ1

φ2

Vout

φ1

φ2CB

buf

Rset

V

iload

86

SC ModulatorModulator multiplies by a series +1…-1…+1…-1…Toggles Sign bit in A-cap input under logic control

Generates sum and difference frequenciesPLUS

Sum and difference from multiples of modulator frequency

∑=

=oddn n

tfntv )2sin()( modπ

87

SCBlock Analog ModulatorAnalog Modulator

ASC10, 12, 21, 23

Digital ConnectionsLow (no modulation)GOE[1]GOE[0]Row 0 Broadcast RowAnalog Column Comparator 0,1,2,3

Enables connection from BPF zero-crossing out to BPF or LPF modulator input for frequency shift or energy detector

φ2

φ1

CA

φ1

φ2

φ1

CF

Vin Vout

ASign

Row 0 Broadcast Bus

GOE[1]GOE[2]

low (no modulation)

AMod

Analog Column Comparator 0Analog Column Comparator 1Analog Column Comparator 2Analog Column Comparator 3

CBus0 CBus1 CBus2 CBus3

ABuf3ABuf0 ABuf1 ABuf2

ACB00 ACB01 ACB03ACB02

ASC10ASD11

ASC12ASD13

ASD20ASC21

ASD22ASC23

P2.3

P2.1A

A

B

P2.0

P2.2

A

B

AA

A

88

SCBlock Analog Modulator Heterodyne

HeterodyneMixing of two or more signals to

produce a different frequency.

Analog modulator heterodyne is built around the property that multiplying two sinusoids produces:

Output sinusoid with a frequency equal to the difference of the two input frequencies.

Output sinusoid with a frequency equal to the sum of the two input frequencies.

Low pass filter removes sum frequency

GlobalOut0

(Modulator)

LowPassFilter

PWMRef

VinVout

10kHz

)sin()sin( ba ff ⋅

2cos(

2) baba ffff )cos( +−

−

Removed withlow pass filter

=

89

SCBlock Analog Modulator Heterodyne

Heterodyne Example10kHz reference frequency is input

to the modulator bit of the low pass filter.

11 kHz Input Signal is converted to a 1kHz Output Signal.

Buffer1 Buf1P0.5P0.7

GlobalOut0

(Modulator)

PSoC

LowPassFilter

Buf0AGND

P0.3

Cin

10K

0.1µF

PWMRef

Rin

VinVout

10kHz

MHzF kColumnCloc 6≤

90

SCBlock Analog Modulator Full Wave Detector

Signal FlowSignal comes into PreampGoes to Gain Stage and

ComparatorComparator Output used to

control Gain Stagemodulator bit

Example:4 cycle 20 kHz burst

PreAmpComparator

Gain Stage (Full Wave Detector)

91

SCBlock Analog Modulator Amplitude Demodulator

ComparatorPreAmp

Low Pass Filter (AM Demodulator)

Signal FlowSignal comes into PreampGoes to Low Pass Filter and

ComparatorColumn Comparator 1 is used to

control Low Pass Filtermodulator bit

Example:10 cycle 50 kHz burst

92

Modulator: Analog or DigitalAnalog modulator

Implements function in SC block

Digital modulatorXOR is equivalent

Examine typical system design with modulator for non-amplitude based signals

93

Digital Modulator FSK Detector

FSK ExamplesHART Modem, Bell202 (Caller ID)

0 = 1200 Hz, 1 = 2200 HzPower Line Modem

0 = 131.850 kHz, 1 = 133.050 kHz

CorrelatorMultiplies signal by delayed replicaInteger cycle delay = positive outputInteger + 1/2 cycle delay = negativeImplemented in Modulator in LPF or in

XOR (in row LUT) followed by LPF

)))((2sin()( tffdatafVtv LHLP −+= π

TIME DELAY, d

sin(2πft)

sin(2πf(t+d))Delay Clock

-cos(2πfd)

0 500 1000 1500 2000

sinfl

sinfl delay

fl corr

f ilt f l corr

sinfh

sinfh delay

fh corr

f ilt fh corr

94

SC Analog ModulatorFSK Detector

Filter / ComparatorConvert to zero-crossing

Delay LineImplemented with Shift Register from PRS block

24 bitS/RDelay

Clock

LPFBPF

FSK In

HysteresisComparator

FSK Out

In Phase

5

Input Dig Data(1200 Baud1 bit Lo, 2 bits Hi)

FSK Modulated

Comparator Out

Shift Reg. OutDelayed Comp.

XOR Output(Correlator Out)

Filtered Correlator

Digital Data Out

Out of Phase

Detection Delay = 620 usec

6

7

Low Pass FilterBandwidth near baud rate

Comparator finds the data

`

PRS

S/R InS/R Out

DelayClock

Modulator Out

95

Measuring FSK PerformanceAn "eye pattern" shows transmission

of repetively sampled random data1: Input data2: FSK modulated data3: Correlator output4: Detected digital data

(Horizontal synced to input data)

"Openess" of the eye indicates quality of received data

Risetime determined by sum ofcorrelator delay and filter bandwidth.

Width of line determined by resolution of correlator delay clock and sharpness of filter

Finer resolution takes more blocksBetter filter takes more blocks.

96

FSK: Customer ExamplePSoC in phone application

Update from Call Waiting/Caller ID app note

98% Customer Design

PSoC (CY8C27443) ReplacedTL494 PWM P/S controllerMT8870 DTMF decoder80C52 processor93C46 EEPROM2 LM324 opampsAnalog filtersTLC555 timer + discretesLine voltage detect circuit

Enabled Zero Cost AdditionsDTMF DialerCaller IDTrue Sinusoidal Ring ToneImproved line voltage monitorImproved audible ringbackProgrammable ring voltage

97

Limited Slew AmplifierSlow Slew (Volts/sec) is Bad for fast

signals!

...but, there are applications for slow slew amplifiers

A comparator with and external R C simulates an opamp with programmable slew.

tVCi out

∆∆

=R

Vi cc 2≈

CRV

tV ccout

⋅≈

∆∆ 2

R & C determine Slew Rate.

R

C

Vout

98

Limited Slew Amplifier Example

Com+

Com-

Mains

Universal AC MotorVoltage across the Commutator is:

Mains power less the voltage drop across the field coils.

Inductive switching pulses for brush switching.Amplitude of pulses is:

Proportional to the voltage across thecommutator.

Frequency of pulse is:Dependent on rate of switch changes.Proportional to shaft speed. (RPM)

determined by commutator switching

If Mains power component can besuppressed, the pulses can easily beDigitized.

99

Limited Slew Amplifier Example

Amplifier allows low frequency signals (Mains Power) to pass.

Fast Slewing signals (Commutator Noise) are blocked, leaving only the pulses at the output of the Diff Amp.

Forms an effective phase neutral high pass filter.No distortion of PulsesNo Delay

Diff Amp

Vout

Vin

Slew LimitedOpAmp

Slew Rate Limited Pulse Separator

100

Limited Slew Amplifier ExamplePSoC Implementation of Slew

Rate Limited Pulse Separator

Presently implemented with:6 Analog Blocks2 Digital Blocks

For Production Implemented with:5 Analog Blocks1 Digital Block

Remaining Resources:58% of Analog Blocks87% of Digital Blocks100% of CPU

1k 1k

1M1M

27k

.1uF

SENSE-

Compare

VouttVoutAGND

SENSE+

InAmpOu

PulseDetect

101

Limited Slew Amplifier ExamplePSoC Implementation of Slew

Rate Limited Pulse Separator

Scope Traces show that the 60Hz signal is removed with no visible distortion of pulses.

Pulses can easily be digitized(and counted)

Demo’ed to customer!

102

1/f Noise

Noise exampleADCINCVR direct input from quiet source with

long term average subtractedScale is in ADC counts (300 µV per bit)

Note slow wander . . . . 1/fTHE dominant type of noise in most measurement systems

58

59

60

61

62RAW(SIG-AVG(REF)}

103

Start with a "nice, clean" signalStart with a clean signal:

3.0 mV DCExample: output of pitot tube

Differential pressure indicator of air speed

Add noise:10.0 mV 3.0 Hz sine wave

Representative (but much larger) of the low frequency noises in thePSoC

Representative of environmental noise

-0.010

-0.005

0.000

0.005

0.010

0.015

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Signal

-0.010

-0.005

0.000

0.005

0.010

0.015

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Signal

Signal+Noise

104

Get Rid of Noise by AveragingSample at 100 Hz

Take average of some number of ADC measurements, but ...

4 sample average does nearly nothing

16 sample average doesn't help much either

Logically, we must average much longer than the noise.

Filter for 3 Hz noise will take 10-12 seconds -- not useful

-0.010

-0.005

0.000

0.005

0.010

0.015

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

SignalSignal+NoiseAverage(4)

-0.010

-0.005

0.000

0.005

0.010

0.015

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Signal

Signal+Noise

Average(16)

105

Correlated Double Sample

Sample low frequency noiseShort the inputsMeasure INSAMP out Store

Sample noise + signalSwitch inputs to sourceMeasure INSAMP out

Compute differenceSubtract stored noise from noise

+ signal

13 bit ADCINSAMP

VSIGNAL

13 bit ADCINSAMP

VSIGNAL

Compute running average with easily implemented IIR filter

106

VoilaCorrelated Double Sampling

Removes common mode low frequency noise

IIR filter over 4 samples80% reduction in noise

IIR over 16 samples95% reduction in noise

-0.010

-0.005

0.000

0.005

0.010

0.015

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Signal

Signal+Noise

CDS:IIR(4)

-0.010

-0.005

0.000

0.005

0.010

0.015

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Signal

Signal+NoiseCDS:IIR(16)

107

CDS Antidote to 1/f Noise

Apply lessons of Correlated Double Sample (CDS)Short inputs, measure offset, subtract instantaneous offset from direct

inputBlue trace shows CDS signalAverage more constant, Std Dev (σ) remains the same

Now, add filtering

58

59

60

61

62 RAW(SIG-AVG(REF)}

RAW(SIG-REF)

108

CDS + IIR

Correlated Double Sample (CDS) removed most of 1/fInfinite Impulse Response (IIR) filter provides running

averageRaw Std Dev σ = .816 countsIIR (25%) on Non CDS σ = .518 counts IIR (25%) on CDS σ = .224 counts

58

59

60

61

62 N(avg)=4(SIG-AVG(REF))

N(avg)=4(SIG-REF)

109

CDS + more IIRLonger IIR filter provides longer running average

Raw Std Dev σ = .816 countsIIR (5%) on Non CDS σ = .465 counts IIR (5%) on CDS σ = .085 counts

IIR filters require simple computation, near zero RAMIIR (like any other filter) reduces data bandwidth Technique proven in customer applicationsApp Notes in process

58

59

60

61

62 N(avg)=20(SIG-AVG(REF))N(avg)=20(SIG-REF)

110

System Design Example:X-10 Receiver

Power line communications for consumer applications

Signal120 kHz 1 msec pulse at zero crossing

Rides on top of AC line (110 V)Level = 50 mV to 4 V p-p -- requires AGC Data encoded in presence/absence of pulse

111

X-10 Receiver Block Diagram

3 kHz LPF takes 120 kHz carrier out of zero x-ing sync3 kHz HPF takes 50/60 Hz line out of carrier pathDemo shows 120 kHz detection onlyLine connections left as exercise for studentZero x-ing detector and AGC to follow later

120 kHzBand Pass

Filter

10 kHzLow Pass

Filter

FullWave

Detector

3 kHz LPF

3 kHz HPF

Zero X-ingDetector

AGC (digital) GatedADC

COMP

PGA

COMP

DATA

Zero X-ing Detector and AGCleft as exercise fo the student

112

PSoC Topology

User modules dropped inParameters set from spreadsheet calculationsDigBuf used to route comparator output to port

113

Switched Cap Filter DesignLow Pass Filter

Common Clock with BPFHigh OSR is important to reject 2x

carrier in full wave detectorMod bit built into ASC A-cap

Band Pass FilterEnter parameters

Adjust C2 to align peakTighter bandwidth is possible4 pole filters are possible, but

consume blocks

Cypress MicroSystems 1 Pole Pair Band Pass Filter Design, Rev 2.1 Design ProcedureDesign Requirements Enter Filter Specification (data fields in yellow)Enter: Center Frequency (Hz) 120000.0 Enter C2 value ( range 1:31)Enter: Bandwidth (Hz) 10000.0 Verify C1-4 values in range 1:31Enter: Gain (dB) 0.00 Select Plot Resolution, adjust scales as necessaryEnter: Sample Frequency 1500000.0 Verify expected filter performance, adjust C2 and Sample Frequency

Transfer values for C1,C2,C3,C4,CA,CB to User Module Parameter TableSelect clock source and dividers (24V1,2 or dig block), set for div by n

Derived Filter Section RequirementsQ 12.000 Enter resolution 0 for Narrow Band, 1 for Wide Band 0.000osr 12.500f0 (with pre-warp) 122592.1318Gain (V/V) 1.000

User Module Design ParametersEnter: C2 ( to UM) 14

CA (default to UM) 32CB (default to UM) 32C3 (calculated) 17.74C3 ( to UM) 18C4 (calculated) 2.254C4 ( to UM) 2C1 (calculated) 1.125C1 ( to UM) 1

Calculated Q 13.541Required fs 1500000.000Divide by n (Calculated for 24 MHz clock) 4.00

Adjusted divide by n 4Sample Clock (Hz) 1500000.000Calculated Gain (V/V) 0.889

Band Pass Frequency Response

-7.0

-6.0

-5.0

-4.0

-3.0

-2.0

-1.0

0.0

1.0

100000 110000 120000 130000 140000 150000

Freq (Hz)

Gai

n (d

B)

Nominal Expected

Cypress MicroSystems 1 Pole Pair Low Pass Filter Design, Rev 2.1 Design ProcedureDesign Requirements Enter Data fields in yellowEnter: Corner Frequency (Hz) 11000.0 Verify calculated Cx parameters in range of 1:31Enter: Gain (dB) 0.00 Verify calculated "d" matches designed "d"

sample freq 1500000.00 Verify calculated corner frequency matches designed valueEnter 0 or 1: Type Butterworth 1 Adjust plot scales as necessaryEnter 0 or 1: .1 dB Cheb. 0 Transfer values for C1,C2,C3,C4,CA,CB User Module Parameter TableEnter 0 or 1: 1 dB Cheb. 0 Select clock source and dividers (24V1,2 or dig block), set for div by nEnter 0 or 1: Bessel 0Enter 0 or 1: Custom Complex Poles 0Enter 0 or 1: Custom Real Poles 0

Derived Filter Section Requirements Custom Complex PolesOSR 136.364 Enter Real Part of Pole Location 0.4d (damping ratio) 1.414 Enter Imaginary Part of Pole Location 0.7d compensated 1.445

With pre-warp allowance scaled f0 11001.95 Custom Real PolesGain (V/V) 1.000 Enter Plow scaled to corner freq. 0.037

User Module Design Parameters Enter Phigh scaled to corner freq 1If C2<1 reduce sample freq C2 (calculated) 1.020

C2 ( to UM) 1CA (default to UM) 32 re imCB (default to UM) 32 Bu 0.707107 0.707107

If C4>>31, reduce sample freq C4 (calculated) 31.368 .1Ch 0.6104 0.7106C4 ( to UM) 31 1 Ch 0.4508 0.7351C3 (calculated) 2.061 Bess 1.103 0.6368C3 ( to UM) 2 Custom 0.4 0.7C1 (calculated) 1.000C1 ( to UM) 1

Caculated d 1.392 real 0.037 1Required fs 1500000.000 selected 0.707107 0.707107Divide by n (Calculated for 24 MHz clock) 4.000

Adjusted Divide by n 4Sample Clock (Hz) 1500000.000Corner Frequency 10633.987

Gain Calculated (V/V) 1.00

Low Pass Frequency Response

-80

-70

-60

-50

-40

-30

-20

-10

0

10

1000 10000 100000 1000000Freq (Hz)

Gai

n (d

B)

NominalExpected

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Parameters and ResourcesSet User Module Parameters

Control LPF polarity in software

Set Global ParametersEasily limited to ref and clock selections

Set Pin-outs

Use modulator bit to generate full wave detectorPlacement limited to ASC10 blocks Comparator output routed through DigBufModulator built into LPF2 User Module

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Software;------------------------------------------------; X-10 Receiver Assembly main line;------------------------------------------------include "m8c.inc" ; part specific constants

; and macrosinclude "memory.inc" ; Constants & macros for

; SMM/LMM and Compilerinclude "PSoCAPI.inc" ; PSoC API definitions for

; all User Modulesexport _main

_main:

; Set UM power and startmov A, PGA_1_HIGHPOWERcall PGA_1_Startmov A, BPF2_1_HIGHPOWERcall BPF2_1_Startmov A, LPF2_1_HIGHPOWERcall LPF2_1_Startmov A, CMPPRG_1_HIGHPOWERcall CMPPRG_1_Start

; Enable Modulator in LPF2_1M8C_SetBank1mov reg[AMD_CR1], 04hM8C_SetBank0

.terminate:jmp .terminate

Start analog user modulesEnable modulator

AMD_CR1 is in Bank 1

CompileBuildSwitch to DebuggerConnect to ICEDownload program

RUN

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System Test

120 kHz carrier burst

Band Pass Filter output

Full Wave Detector/LPF output

Detected carrier output

Signal source: waveform generator in burst mode120 kHz, 1 msec at 120 Hz rate

Total design, program, build and test: 2.0 Hours ( + documentation)

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Advanced Analog Design Summary

PSoC offers flexible resources to accomplish sensor interfaces, signal processing, and system controls.

PSoC Designer quickly and easily unlocks the Analog functionality of PSoCFiltersReferencesAmplifiersClocking OptionsPower ConcernsADCs …and more