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PSMC Roadmap For Integrated Photonics ManufacturingRichard Otte Promex Industries Inc.Santa Clara California
For the Photonics Systems Manufacturing ConsortiumApril 21, 2016
Meeting the Grand Challenges in Integrated Silicon Photonics
Roadmap Participants as of December 13, 2015• 12 Countries• 481 Individuals• 185 organizations
Steps in PSMC Roadmapping Process
1.Scope and Analyze the Situation2.Identify the Grand Challenges and Needs3.Identify Paradigm Shifts and Strategic
Concerns4.Develop Strategic Recommendations for all
Stakeholders5.Provide these recommendations to AIM
Photonics to aid in focusing and prioritizing their Technical Plans for Research and Development
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Scope of this Presentation
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• This Presentation Covers the Grand Challenges identified by the PSMC TWGs.
• The Grand Technical Challenges:– Reducing Power per function– Reducing Cost– Decreasing Latency– Increasing physical bandwidth density
• More detailed guidance is available in the PSMC Written Roadmap.
Grand Challenges Identified by the PSMC Product Emulator Groups (PEGs)
• Data Center Applications• Internet of Things Applications
The Technology Needs Differ by PEG
Data Centers• The data center servers require
heterogeneous integration of memory, logic, power controllers and photonics in 3D-SiP package architecture to meet applications requirements in a controlled environment.
• The solution must also provide for packaging of replacements for existing “top of rack” components.
• These solutions must include SiP based traffic analysis supporting data path switching decisions, selecting between photonic and electronic data paths and between packet switching and circuit switching.
Internet of Things• The internet of things (IoT) will
require a package for heterogeneous integration of sensors, RF components, memory and photonics in 3D-SiP architectures.
• The package must enable a general purpose SiP IoT hub packaging for uncontrolled environments.
• This capability will include energy scavenging to power the IoT hub in many cases and redundancy to ensure long term service free reliability.
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Product“Emulators” areUsedToDriveTechnology Requirements
Grand Challenges Identified by the PSMC Technical Working Groups (TWGs)
• Monolithic Integration• Integrated Silicon Photonics Packaging• Interconnections• Assembly and Test
Monolithic Integration
Professor Lionel Kimerling
Key Attributes
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E-PHybrid
MatrixSwitch
Embedded
Embedded
Embedded
Comm/Comp/Sense/Image Embedded
$0.01/Gbps
128Tbps
SmallCommercialDemandforTechnicallyViableOpticalSolutions
NoTechnically ViableOpticalSolutionsExist
Function
TxRx
Processor
Cost
BWdensity
Energy
ReachChip EscapeDataRate
NOW NEXT LIMITS
8x8(VICTORIES) 32x32
$1/Gbps $0.1/Gbps
30Tb/s/cm2 (PETRA)
10pJ/b
1000km 100m 1cm
40Gbps 400Gbps
CommerciallyViableOpticalSolutionsDeployed
WDMCoherent
Signal Conditioning FFT
1pJ/b 100fJ/b
Difficult Challenges: Monolithic Integration
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• Light Source• Process Tools (193nm litho, 65nm CMOS)• Universal E-P CAD for photonic integration• Electronic-Photonic process integration• Power distribution• Athermalization• Wafer-level inspection and test• Scalable (single mode, E-P) packaging solution• Interconnection: fiber, optical, electronic• Throughput, Yield and Reliability
Difficult Challenge: Light Source
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• Do we want one laser or many lasers?• Do we want one wavelength or multiple
wavelengths?• Can we integrate lasers without epitaxy?• The gain medium for the light source is the
crucial material.• What are the materials system compatibility
issues?• Can we use wafer to wafer bonding and not
lose the scalability?
Difficult Challenge: EDA Tools
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• Goal: tape out functionality as with digital circuits today.– difficult for analog electronic circuits– essential to meet energy targets– essential for SDN-like control functions– essential for ramp of ‘good enough photonics’
• Fully integrated, seamless compatibility with digital/analog CAD tools.– lumped element device/circuit models– process integration– optical impedance matching
Integrated Silicon Photonics Packaging
Bill Bottoms
What Has To Be Packaged?
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• The components that will be assembled into the resulting complex 3D-SiPs may include:
– Monolithic photonic ICs (PICs)(includes photonics, electronics and plasmonics)
– Discrete optical components not integrated in the SiPh-ICs.– Si based logic and memory ICs– MEMS devices– Sensors (including a growing list of photonic sensors)– GaN power controller circuits– RF circuits– Passive components (including integrated passive devices)– Direct bandgap semiconductor lasers
• Packaging Functions– Optical interconnects to and from the outside world– Electrical interconnects to and from the outside world– Thermal paths to and from the outside world
What Has To Be Packaged?
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• The components that will be assembled into the resulting complex 3D-SiPs may include:
– Monolithic photonic ICs (PICs)(includes photonics, electronics and plasmonics)
– Discrete optical components not integrated in the SiPh-ICs.– Si based logic and memory ICs– MEMS devices– Sensors (including a growing list of photonic sensors)– GaN power controller circuits– RF circuits– Passive components (including integrated passive devices)– Direct bandgap semiconductor lasers
• Packaging Functions– Optical interconnects to and from the outside world– Electrical interconnects to and from the outside world– Thermal paths to and from the outside world
New devices and new materials will be added over the 15 year life of this Roadmap.
Packaging Technology Needs and Gaps
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• Co-design and simulation tools for heterogeneous integration
• Low cost electrical/photonic package substrates
• Power reduction at system level
• Increased parallelism in manufacturing processes
• Supply Chain supporting low cost package production
Interconnections:Connectors, Cable Assemblies & Printed Circuits
John MacWilliams
Packaging Challenges Impact Connections:
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• Cu – Optical Transition at IO Port: NOW
• Circuit Functions are Disaggregated: SOON
• CPU/ASIC Embeds Optical Interconnect: FUTURE
• Fiber Optic Connections: As Few as Possible
Solutions to Interconnect Challenges:
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• Connector/Cable Assembly Cost Reductions• Volume-Dependent: 105 or 106
• Standardization• Automation Tooling Investments• Transceiver Cost Reduction
• Optical Organic PCB Technology & Cost• Packaging: Cables or Waveguides?• Volume Commitments• Process Linkages:
• WG Materials – OPCB Makers – OPCB Connector Developments
• Chip/SiP/PoP Level Optical Interconnect• Technology Linkages Needed:
Device – Package – Substrate – Connector Manufacturers
SiPh Users Group!
OEM EMS
Materials Substrates Connectors
Device
Top Priority Interconnect Gap List:
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• Parallel optical solutions, especially transceivers, require lower cost options for on-chip/off- chip and on board applications
• Single mode fiber from backplane through the data center. • Organic Substrate Technology: Rigid….Flex…..Fly-
Over….Embedded Wave Guide• Matching Connector Technology for Vertical u-Via Connections
to Embedded WG• A physical architecture able to operate at 100Gb/s within Rack
and 1Tb/s Rack-to-Rack.• On-to and off-of chip data transmission methods for composite
rates >5Tb/s that are hard to accommodate electrically due to approximately 25 Gb/s CMOS rate limit per I/O channel
Assembly and Test
Richard Otte
Assembly & Test, Key Attributes
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SmallCommercialDemandforTechnicallyViableOpticalSolutions
NoTechnically ViableOpticalSolutionsExist
NOW NEXT LIMITS
CommerciallyViableOpticalSolutionsDeployed
Tolerances 0.05micron
10’s
<$200K
#ofParts
Assy Time
Assy SetUp
Assy EquipCost
SMFiberAttach
TestTime
0.5micron
$50Kto$1000K
<5
manyminutes minutes seconds
hours minutes
minutes/unit seconds/unit
minutes manyseconds fewseconds
CostofParts $$s cents
Implementation Vision:dedicatedmaterials,parts,toolsuppliers; focusonyield, throughputandutilization.
Why Assembly is Needed
• Since We Do Not Yet Know How to Provide All Needed Functionality with Integration, Heterogeneous Integration Is Needed.
That Means Assembly,and that Means $$$ !!
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Optical vs Electronic Needs
Optical products Differ from Electronic products• Single Mode assemblies require sub micron assembly
accuracy and mechanical stability.• Assemblies often use the Z axis as well as X & Y.• Cleanliness to minimize light loss and scattering by
particles and surface contaminants is needed.• A broader variety of parts and processes are used.• Production volumes are lower.
Notice that• If electrical conductors maintain continuity, they can flex
with temperature and mechanical stress.• Historically, electronic devices have been designed to flex
under these stresses !!So
• The TWG addresses the sub micron accuracy and stability required in many optical products.
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Low Cost Starts with Design
• Minimize Part Count & Assembly Steps• Eliminate Pigtails !!!
• Use parallel fabrication and assembly methods
• Choose Parts with:• dimensional consistency• location reference points
• Choose Robust Assembly Processes• evaluate part specifications and
dimensional tolerances• maximize the tolerances required
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GrandChallenges, Assembly&Test
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• Developing the Right Mind Set:– Move from individual parts to integration– Eliminating Pigtails
• Achieving 0.05 micron Tolerances• Improving Design Capability
– Training Designers to Design For Manufacturing– Providing Material Properties
• Developing Optical Specific Assembly Equipment– Minimize Assembly & Setup Time
• Developing The Low Cost High Accuracy Part Supply Chain
• Developing Standards • Conceiving of New Applications
Strategic Recommendations from the PSMC Roadmap
Strategic Recommendation2015-2020
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• Focus Projects on Addressing the Grand Challenges– Reduction in Power per function– Reduction in Cost– Decrease Latency– Increased physical bandwidth density
• Address challenges that the supply chain will not achieve in time to address the quantified industrial needs in the PSMC Roadmap– Design Tools– Manufacturing Technology– Materials Development– Supply Chain Consolidation through “Industry Standards”
PSMC: What Next ?
The Future of PSMC
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• PSMC #1 ends April 30, 2016 with Submission of the Written Roadmap to NIST.
• PSMC #2 Continues the Roadmap effort as Part of AIM-IP.
• PSMC #2 will Expand and Synchronize with AIM-IP:– More PEGs– More TWGs
• Watch for Further Developments
Thank You for your Attention & Interest
