Embed Size (px)
Citation preview
PSG COLLEGE OF TECHNOLOGY: COIMBATORE – 641 004DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGG.
VLSI DESIGN CENTRE
Name of the Sponsor Amount
Ministry of Electronics and InformationTechnology (MeitY)
1.69 Crores
PSG Management 20,00,000 LakhsTEQIP 2,67,350 Lakhs
Coordinator – Dr.P.Kalpana
Co-Coordinator – Dr.K.Rajalakshmi
Faculty Members Project Associate Lab Engineer
Dr.J.Ramesh Mr.S.Udaya Shankar Mr.P.Madhan kumar
Dr.S.Hema Chitra
Dr.M.Santhanalakshmi
Dr.P.Saravanan
Mrs.A.Uma
Mr.K.R.Radha Krishnan
Ms.C.Satyashree Sowbarnica
Mrs.M.Swathi Priya
I. HARDWARE AND SOFTWARE DETAILS
SOFTWARE’S AVAILABLESynopsys EDA tools: Asia Pac Front End University Bundle - 5 licenses Asia Pac Back End University Bundle - 5 licenses Asia Pac 2D TCAD University Bundle - 10 licenses Asia Pac Full Custom University Bundle - 3 licenses
Cadence EDA Tools: Core System Development Suite (SDS) Bundle
for digital and analog (Front-end and back end) - 20 Licenses CADENCE Analog & Digital PG 99Y10L
(Tool for both front end and back end IC designs) -10 LicensesMentor EDA Tools Bundle/Tools set IC Nanometer Design Bundle - 1 Bundle (100 User Licenses)
( Eldo, Questa, ADMS, Pyxis, Calibre, IE3D) Design Verification and test bundle (Vista, -1 Bundle (100 User Licenses)
ReqTracer, Questa Simulation, Questa Codelink, Precision synthesis, Leonardospectrum, Tessent, System vision
Board/PCB Bundle -1 Bundle(100 User Licenses)XILINIX EDA TOOLS & FPGA BOARDS Bundle/Tools set
Vivada System Design set - 1 Bundle (25 User Licenses) SDSoC Development set - 1 Bundle (25 User Licenses) Bundle-1 of Boards and Accessories
Basys3 Board + PMOD keypad+ - 10 NosPMOD CLPAnalog Discovery Kit) - 3 Nos
Bundle-2 of Boards and AccessoriesZybo board - 5 NosNexsys4-DDR Board - 5 Nos
Xilinx System Edition – Vivado Design Suite 2012 ALTERA
FPGA Development Board – a ICB HSMC - 1NoFPGA Development Board - a DE2 115 - 1NoFPGA Development Board a Video and - 1 NoEmbedded Kit
Xilinx FPGA Development Board - 2 Nos
HARDWARENumber of PC’s supported from Management - 3 Servers + 20 SystemsNumber of PC’s supported from MeiTY (SMDP C2SD) - 5 HP Systems
II. COLLOBORATION WITH INSTITUTIONS
The centre has collaboration with
Indian Institute of Science Bangalore, Semiconductor research work Laboratory Department of Space, Government of India and
Digital India Corporation (Formerly Media Lab Asia), Govt of India.
III. ABOUT SPECIAL MANPOWER DEVELOPMENT PROGRAMME – CHIPSTO SYSTEM DESIGN
Ministry of Communications & IT, Government of India has promoted the “SpecialManpower Development Programme for VLSI Design and Related software” with anobjective of developing the VLSI activities through the establishment of VLSI Centers andgiving training to under graduate, post graduate (MS / M Tech) and Doctoral (PhD) levels inVLSI related fields. SMDP-I was initiated in the year 2000, involving nineteen institutionscategorized into 7 resource centers (RC’s) and 12 Participating Institutes (PI’s).Aftercompletion of this Project, the second phase of the Program (SMDP-II) was started in2005.The ministry provided support to set up VLSI Design Centre with Systems, Hard waresand advanced CAD software tools in all the 32 institutions
Ministry of Electronics and Information Technology, Govt of India has initiatedSpecial Manpower Development Programme for Chips to system Design in 2015. PSGCollege of Technology is one among the 60 institutions in India, sanctioned with the totalproject outlay of 1.69 cores through C2SD project .The Project has following broadObjectives
a) Bring in a culture of system on Chip/System designing by developing working prototypeswith societal applications using mostly in-house designed ASICs/ICs
b) Capacity building in the area of VLSI/Microelectronics and Chip to System developmenti.e. to train Special manpower in the area of VLSI Design and chips to Systems atBE/B.Tech,ME/M.Tech and PhD level
c) Broaden the base of ASIC/IC designing in the country
d) Broaden the R&D base of Microelectronics /Chip to system through “Network PhD”program
e) Promote “Knowledge Exchange Program”
f) Promote protection of “Intellectual Property” generated under the program
ECE Department has also received grant of support under Visvesvaraya PHDscheme for Electronics & IT Digital India Corporation (Formerly Media Lab Asia), Govtof India through SMDP – C2SD Project.
IV SPONSORED RESEARCH PROJECTS1. Development of Application Specific Integrated Circuits(ASIC) for Light CombatAircraft
The main objective of this project is to develop an Application SpecificIntegrated Circuit (ASIC) to be used in Light Combat Aircraft for sensors interfacing.Atmospheric variations like temperature and pressure are observed by sensors and the sensorsare interfaced to controller for processing the data.
This Cluster project is being implemented by IISc, Bangalore with PSG College ofTechnology, Coimbatore, NIT - Warangal, IIT - Hyderabad, NITK - Surathkal and NIT-Rourkela.
At PSG College of Technology Processor module, boot loader and test environment arebeing developed.2.Biometric Identification System
Biometric ID cards apply to a number of different solutions, especially for thosecompanies and individuals that might require greater security. Those companies that work inhighly competitive fields might want biometric ID Cards as added security against illegalduplication and theft. Even biometric cards for children are starting to be implemented andare an excellent way to identify them quickly and easily, especially if they are young enoughto forget important information like their home address and number.
The project aims to improve the security of these cards by improving the side channelresistance of the same. The side channel attacks in particular power analysis attacks takeadvantage of the inherent leakage of the cryptographic implementation of the device. Hencethe proposed architecture includes a suitable countermeasure that resists such kind of attacks,thereby making the biometric ID cards more secure.
CHIP FABRICATED FROM SMDP – PHASE II
In the year 2008, under India chip programme an integrated circuit is fabricated jointly withIndian Institute of science, Bangalore.
V.LAB UTILIZATION AND OUTCOMES
ME VLSI Design Accredited by NBA for Five years (2016 – 2021) VLSI EDA Tools Xilinx, Synopsys, Cadence and Mentor Graphics are used by the
ME VLSI Design students for their laboratory and project works.
Apart from ME VLSI Design , other Master branches like Wireless communication,Communication Systems and Applied Electronics are using the tools for theirlaboratory and Project works.
Under graduate Course in ECE uses the Mentor Graphics tools and Xilinx tools fortheir laboratory works.
Under graduate and post graduate students uses FPGA Kits for their laboratory andproject Works.
Doctoral Research scholars are utilising the hardware and software tools for theirresearch work.
Many Core placement Companies like Intel, QUALCOMM, IBM. HCL, Xilinx,AMD, Western Digital, etc offer internships and placements to students based on theskills and knowledge acquired by students using EDAtools.
One Year Certification course on VLSI design is proposed. The hardware andsoftware facilities from the design centre will be utilized to conduct the program.
Number of PhDs completed in the VLSI Design Centre is 23. PSG – INTEL Centre of Excellence in VLSI System Design is to be established with
Advanced hardware and software from Intel with the contribution of Rs.2 Crores fromIntel and 25 Lakhs from PSG College of Technology .
VI. EVENTS ORGANISED1. International Symposium Orgnaized
No Name of TheCoordinators
Name of theConference
Date Number ofParticipants
AmountEarned
(Rs.)1. Dr.S.Subha Rani 18th International 16 – 18 July 135 12,00,000
Dr.P.Kalpana Symposium on 2014Dr.S.Hema Chitra VLSI Design andDr.M.Santhanalakshmi Test (VDAT –Dr.K.Rajalakshmi 2014)Dr.P.SaravananMrs.A.UmaMr.K.R.RadhaKrishnanDr.U.Saravana KumarMr.K.Rajasekar
2. Conferences Organized
No Name of TheCoordinators
Name of theConference
Date Number ofParticipants
AmountEarned
(Rs.)1 Dr.S.Subha Rani National Conference 6th & 7th ,May, 50 21,000
Dr.P.Kalpana on VLSI, 2013Dr.M.Santhanalakshmi Communication,
WirelessTechnologies
2 Dr.P.T.VanathiDr.J.Ramesh
TEQIP - II SponsoredNational Conference
30th January,2014
60 75,000
Dr.G.Umamaheswari on CommunicationDr.L.Thulasimani Systems and VLSIMr.S.Mohandass DesignMr.K.Rajasekar
3 Dr.S.Subha RaniDr.P.Kalpana
AICTE SponsoredNational Conference
14th & 15thMarch, 2014
60 2,00,000
on ResearchChallenges inWirelessCommunicationSystems and VLSIDesign
4 Dr.S.Subha Rani National Conference 29th & 30th 60 25000Dr.P.Kalpana on Electronic Chip to April, 2015Dr.M.Santhanalakshmi System Design andMrs.A.Uma Next Generation
CommunicationTechnologies
5 Dr.S.Subha RaniDr.P.KalpanaMrs.A.UmaDr.M.Santhanalakshmi
National Conferenceon Advance in Microand Nano Electronics(NCAMNE-2016)
23rd April2016
50 31,383
6 Dr.S.Subha RaniDr.P.KalpanaDr.M.SanthanalakshmiMrs.A.Uma
National Conferenceon Advance in Microand Nano Electronics(NCAMNE-2017)
27th - 28th
Apr 201750 24,250
7 Dr.S.Subha RaniDr.P.KalpanaMrs.A.UmaDr.P.Saravanan
National Conferenceon VLSI DesignCommunication andNanotechnologies
23rd –24th
March2018
50 25,000
8 Dr.S.Subha RaniDr.P.KalpanaDr.M.SanthanalakshmiDr.P.Saravanan
Two day NationalConference on MicroNano Electronics &CommunicationSystems
12th – 13th
,April2019
100 30000
3.Workshops Organized
NoName of TheCoordinators Programme Title Date
Number ofParticipants
1 Dr.S.Subha RaniDr.P.KalpanaDr.M.Santhanalakshmi
Hands onWorkshop onFPGA BasedEmbeddedSystem Design
11th&12th
October2019
40
2 Dr.S.Subha RaniDr.M.SanthanalakshmiMrs.A.Uma
TEQIP III SponsoredSponsored Three DaysWorkshop on Linux andPython Scripting
26.07.201928.07.2019
40
3 Dr.P.Saravanan One Credit course onEmbedded Processingwith FPGAs
06.10.2018 –07.10.2018
45
4 Dr.S.Subha RaniDr.P.KalpanaDr.S.Allin ChristeDr.M.SanthanalakshmiDr.K.Rajalakshmi
Signal and ImageProcessing on Zynq-7000 Soc Using XilinxVivado Tools
27.09.2018 –28.09.2018
25
5 Dr.S.Subha RaniDr.P.KalpanaDr.M.SanthanalakshmiMrs.A.Uma
TEQIP III SponsoredSponsored Three DaysWorkshop on ScriptingUsing Python
12.07.2018 –14.07.2018
60
6 Dr.P.SaravananMrs.M.Swathipriya
TEQIP III Sponsored TwoDay workshop onUniversal VerificationMethodology (UVM)
19.05.2018 –20.05.2018
20
7 Dr.S.Subha RaniDr.P.SaravananMr.M.Alagappan
Expert Lecture on AnalogCMOS Integrated CircuitDesign (Architecture toSilicon)
10.03.2018 60
8 Dr.P.SaravananMrs.M.SwathiPriya
TEQIP III Sponsored OneCredit course on SystemLevel VerificationTechniques andMethodologies
03.03.2018 –04.03.2018
50
9 Dr.S.Subha Rani System Design 27.10.17 - 25Dr.P.Kalpana Using Vivado 28.10.17Dr.K.Rajalakshmi Design Suite andDr.M.Santhanalakshmi Zynq-7000-SoC
10 Dr.S.Subha Rani Two Day 07.07.17 - 60Dr.P.Kalpana Workshop on 08.07.17Mrs.A.Uma Scripting UsingMs.C.Satyashreesowbarnica Python
11 Dr.S.Subha Rani Two Day 02.07.16 - 45Dr.P.Kalpana Workshop on 03.07.16Dr.P.Saravanan Command LineMrs.M.Swathi Priya Interface and
scripting usingPython
4.Faculty Development Program Organized
No
Name of TheCoordinators Programme Title Date
Number ofParticipants
AmountEarned
(Rs.)
1 Dr.S.Subha RaniDr.P.SaravananMr.M.AlagappanMr.K.R.Radha Krishnan
MeitY Electronics & ICTAcademy IIT GuwahatiSponsored One WeekFaculty DevelopmentProgramme on "VLSIDesign at Deep SubmicronNode"in association withSemiconductor Laboratory,Chandigarh.
04.02.2019 –08.02.2019
35 1,40,000
2 Dr.S.Subha RaniDr.P.KalpanaDr.P.SaravananMr.M.Alagappan
TEQ IP -IISponsored seven dayFaculty DevelopmentProgramme on Multiscale Modeling andsimulation of Nanelectronic Devices –A ResearchPerspective
25.07.201631.07.2016
25 75,000
3 Dr.S.Subha Rani AICTE sponsored 06.11.2013 40 4,00,000Dr.P.Kalpana Faculty development 19.11.2013Dr.P.Saravanan Programme on
Verification andTesting of VLSICircuits
4 Dr.S.Subha RaniDr.P.KalpanaMrs.M.SanthanalakshmiMrs.K.RajalakshmiMrs.A.UmaDr.P.SaravananMr.K.Rajasekar
TEQIP II SponsoredFaculty DevelopmentProgramme on VLSIarchitectures forsignal processing
18.11.2013 –23.11.2013
29 75,000
5.Training Programes Organized
No Name of theCoordinator(s)
Title ofCourse
Organizedby
Date Number ofParticipants
AmountEarned (Rs.)
1 Dr.S.Subha RaniDr.P.SaravananDr.S.Hema Chitra
AICTESponsored Oneweek Shortterm TrainingProgram onFrom Idea toImplementation: Exploring thePotentials ofFPGA in SmartEnivornment
ECEDept,PSG
CT
17.06.19 –22.06.19
42 1,50,000
2 Dr.S.Subha Rani Five Days ECE Dept, 19.06.2017 15 69,000Dr.P.Kalpana Training PSG CT ToMrs.M.Swathi Programme on 23.06.2017priya Mixed SignalMr.S.Udaya SoC : Design toShankar Sign-Off
3 Dr.S.Subha Rani SMDP - C2SD ECE Dept, 23.01.2017 17 2,75,000Dr.P.Kalpana MeitY PSG CT toMrs.M.Swathi Sponsored 25.01.2017priya Cadence tool
training
4 Dr.S.Subha Rani SMDP -C2SD ECE Dept, 16.01.2017 12 1,50,000Dr.P.Kalpana MeitY PSG CT toDr.K.Rajalakshmi Sponsored 19.01.2017
MentorGraphics tooltraining
6.ISTE STTP Conducted
No
Name of theCoordinator(s)
Title of Course Organized Date Particip
ants
AmountEarned
(Rs.)1 Dr.S.Subha Rani
Dr.S.Hema ChitraAICTE Sponsored Oneweek Short TermTraining Programme onComputer Aided DesignFor VLSI
ECE Dept and ITDept,PSG CTCoimbatore
11.11.2019-16.11.2019
40 1,50,000
2 Dr.K.RajalakshmiMrs.A.Uma
Two-Week ISTESTTP On Cmos,Mixed Signal AndRadio Frequency VlsiDesign
IIT Karagpur,and ECEDept,PSGCT
30.01.2017to04.02.2017
35 1,47,000
3.Dr.M.Santhanalak shmi Two-Week ISTESTTP On Analogelectronics
IIT Karagpurand IITBombay, ECEDept,PSG CT
04.06.13 to
14.06.13
31 1,10,000
7.Seminar Conducted
No
Name of theCoordinator(s)
Title ofCourse
Organized Date Participants
1 Dr.P.Saravanan Indian Council ofMedical Research(ICMR) SponsoredNational level seminaron ResearchPerspectives in FPGA-Based MedicalElectronic Devices forHealthcareApplications
IndianCouncil ofMedicalResearch(ICMR)& ECEDept, PSGCT
23 – 24March 2018
60
2. Dr.P.KalpanaMr.K.R.Radhakrishnan
Awareness Program onIEEE blender learningprogram in VLSI
ECE Dept,PSG CT
22nd
,August2015
70
3. Dr.P.KalpanaMr.K.R.Radhakrishnan
Technical seminar onSignal IntegrityEMI/EMC & Reliability
ECE Dept,PSG CT
06,August2015
30
4. Dr.S.Subha RaniDr.P.Kalpana
Didactic Seminar onOrCAD PSPICE &OrCAD PCB
EntupleTechnologies& ECE DeptPSG CT
24th
,August2015
100
8.Consultancy WorksThree Faculty Members from Sri Krishna College of Arts and Science, Coimbatore
has used the Synopsys TCAD, Cadence Tools from the VLSI Design Centre for theirresearch.
S.No Name College Name1. Sudheesh.S
Rajesh.A.P.Sithara.A
Sri Krishna College of Arts and Science,Coimbatore
9.Seminars/Workshops Organized
Sl.No
Name of theCoordinators
Title of theSeminar
Organized Date Number ofParticipa
nts
1 Dr.S.Subha RaniDr.P.KalpanaDr.M.Santhanalakshmi
Hands Workshopon FPGA BasedEmbeddedSystem Design
ECE Dept,PSG CT
11.10.201912.10.2019
40
2 Dr.S.Subha RaniDr.M.SanthanalakshmiMrs.A.Uma
TEQIP – IIISponsored ThreeDays workshopon ScriptingUsing Python
TEQIP – IIIECE Dept,PSG CT
26.07.2019–28.07.2019
40
3 Dr.S.Subha RaniDr.P.SaravananMr.M.Alagappan
TEQIP – III Sponsoredone day Expert Lectureon “Architecture toSilicon” {CMOSImplementation flow)
TEQIP – IIIECE Dept,PSG CT
10.03.2018 53
4 Dr.P.Kalpana Mr.K.R.RadhaKrishnan
Awareness Program onIEEE blended learningprogram in VLSI
ECE Dept,PSG CT
22-08-2015 70
5 Dr.P.Kalpana Mr.K.R.RadhaKrishnan
Technical seminar onSignal IntegrityEMI/EMC&Reliability
ECE Dept,PSG CT
6-08-2015 30
6 Dr.S.Subha RaniDr.P.Kalpana
Didactic Seminar onOrCAD PSPICE &OrCAD PCB
EntupleTechnologies
24-06-2015 100
7 Dr.S.Subha RaniDr.P.KalpanaMr.K.R.Radha Krishnan
CoreEl - DigilentWorkshop 2015
ECE Dept,PSG CT
21.09.2015 20
8 Dr.S.Subha RaniDr.P.KalpanaDr.M.SanthanalkshmiDr.K.Rajalakshmi
Two days workshop -on "Analog IC DesignFlow"
ECE Dept,PSG CT
11.08.15 &12.08.15
20
9 Dr.S.Subha Rani Dr.P.KalpanaDr.U.Saravanakumar,Mr.K.R.Radha Krishnan
Two Day Workshop onReconfigurableArchitectures forBiomedical Signal andImage Processing
ECE Dept,PSG CT
21.02.15-22.02.15
36
10 Dr.S.Subha RaniDr.P.KalpanaMr.P.Sarvanan
One day workshop onUniversal VerificationMethodology (UVM)
ECE Dept,PSG CT
12.10.14 24
11 Dr.S.Hemachitra TEQIP II Sponsored Analog 26.07.14 &Mr.K.R.Radhakrishnan One credit course on Devices, 27.07.14
Scripting Languages Bangalore 74ECE Dept,PSG CT
12 Dr.P.T.Vanathi Two days workshop on ECE Dept, 01.04.14 82Dr.J.Ramesh Digital Design with PSG CT 02.04.14
Verilog
13 Dr.P.Kalpana Three days training ECE Dept, 22.08.13 36Mr.K.R.Radhakrishnan programme on Mentor PSG CT 24.08.13
Graphics EDA tools forASIC design flow
14 Dr.P.Kalpana Two days workshop on ECE Dept, 28.01.13 25Cadence Design Tools PSG CT 29.01.13
15 Dr.S.Subha Rani FPGA based system ECE Dept, 20.04.13 35Dr.P.Kalpana design PSG CT 21.04.13Mr.U.SaravanakumarMr.K.Rajasekar
16 Dr.S.Hemachitra Scripting Languages Analog 09.02.13 23Mr.K.R.Radhakrishnan (One credit course) Devices, 10.02.13
Bangalore
VII 1. PhD REGISTERED (ON GOING)
S.No
Scholar Name Supervisor Name Year ofRegistration
1 A.Uma Dr.P.Kalpana 2014
2 S.Kamalakannan Dr.P.Kalpana 2014
3 K.R.Radha Krishnana Dr.S.Subha Rani 2014
4 V.Tamizhsevi Dr.K.Gunavathi 2014
5 M.Elangovan Dr.K.Gunavathi 2014
6 V. Umamaheswari Dr.J.Ramesh 2015
7 P. Vivek Karthick Dr.J.Ramesh 2016
8 A.Deepa Dr.M.Santhanalakshmi 2016
9 S.Hemalatha Dr.K.Rajalakshmi 2016
10 S. Shanthi Rekha Dr.P.Saravanan 2016
11 S.Udaya Shankar Dr.P.Kalpana 2017
12 Navaneethakrishnan Dr.M. Santhanalakshmi 2017
13 Sridevi Dr.M. Santhanalakshmi 2018
14. M.Priyadharshini Dr.P.Saravanan 2019
15. Sudheer Chirivella Dr.M.Santhanalakshmi 2019
16. Lavanya Takur Dr.K.Rajalkashmi 2019
2.PhD CompletedS.No
Scholar Name Supervisor Name Date ofCompletion
B.Vinodhkumar Dr.J.Ramesh 13/12/2018
1 K.Thiruvenkadam Dr.J.Ramesh 28/03/2018
2 V.Govindaraj Dr.J.Ramesh 20/06/2018
3 Aby Thomas Dr.P.T.Vanathi 25/01/2016
4 P.Saravanan Dr.P.Kalpana 21/08/2015
5 M.Santhanalakshmi Dr.P.T.Vanathi 07/02/2014
6 J.P.Anitha Dr.P.T.Vanathi 18/12/2013
7 K.Rajalakshmi Dr.A.Kandaswamy 27/11/2013
VIII PlacementSl.No Roll Number Name Name of the Company
1 17MV01 J. Anbarasan JGD Tech Pvt. Ltd2 17MV03 BoyinaSai Lakshmi
ChaitanyaWestern Digital
3 17MV04 V. Chowthri J JGD Tech Pvt. Ltd4 17MV07 D. Pavithra Western Digital5 17MV08 J. Praveenraj Western Digital6 17MV10V. M. Shivasubramaniyarajan Western Digital7 17MV11D. Vi Vidhya K KalycitoInfotech Pvt. Ltd
8 16MV01Aadhithya N HCL
9 16MV02Ashna A Intel Technologies India Pvt Ltd,
Bangalore10 16MV03
Burjula Sharath Kumar QUALCOMM
11 16MV04Deepa R Intel Technologies India Pvt Ltd,
Bangalore12 16MV05
Keerthana D Western Digital
13 16MV06Mahalakshmi A Western Digital
14 16MV07Priyaadharshini N Qualcomm
15 16MV09Sivashankari T Intel Technologies India Pvt Ltd,
Bangalore
1616MV10
Akshay Sreeraj Intel Technology India pvt.Ltd.
17 15MV02 C.Deepak Intel Technology India pvt.Ltd.
18. 15MV03 S.Ezhil SanDisk
19 15MV04 Arunachalam ReddyMadireddy Qualcomm India pvt.Ltd
20 15MV05 Mahendra Kumar G Cognizant Technolgy SolutionsIndia pvt.Ltd
21 15MV06 Mohanraj.B HCL
22 15MV07 Nivethitha P Collabera
23 15MV08 Ram Prasad Kamaraj Yantra Vision Software pvt.Ltd24 15MV31 Praveen Kumar Jaykar Qualcomm India pvt.Ltd25 15MV34 Suba Chandran Nabiraj Intel Technology India pvt.Ltd.
26 15MV35 Sugitha Elangovan Soilton Technologies Pvt.ltd27 15MV37 Yogajanani TCS28 14MV02 Damala Janaki Samsung R & d Institute29 14MV03 R.Dinesh Qualcomm India Pvt Ltd30 14MV04 D.Lalitha Kathambari Tata Elxsi
31 14MV05 Maramreddy SivaReddy Samsung R & d Institute
32 14MV06 K.Priyanka Cognizant Technology SolutionsIndia Pvt Ltd
33 14MV08 Srinivasan Manojkumar Intel Technology India Pvt Ltd34 14MV09 G.Varun AMD India Private Ltd35 14MV10 R.Yogeshwaran IBM India Pvt Ltd36 14MV35 N.Prasath Wipro Technologies37 13MV03 Loga Subramani Qualcomm India Pvt. Ltd38 13MV04 Purushotham Reddy Qualcomm India Pvt. Ltd39 13MV06 Naveenkumar Synopsys40 13MV07 Nivedita Cognizant Technology Solutions41 13MV08 Sathya IBM42 13MV09 Venkata Vishnu Broadcom43 13MV10 Yasoda Qualcomm44 13MV31 Anjali Wipro Technologies45 13MV32 Aravinda Gouthum Xilinx46 13MV33 Deepa PSG iTech47 13MV34 Devi Priyal IBM48 13MV35 Nithya AMD.49 13MV37 Vandana Cognizant Technology Solutions50 13MV38 Varun Kalycito
51 13MV36 Vaishaly.K Blue Bell Engineering Solutions
IX . PUBLICATIONS
International Journals
Hema Chitra .S,Sarvesh K,Madhu Preeetha B R,” Comparison of Different Configurations ofMicroBlaze Soft IP Core”, International Journal of Applied Engineering Research,Volume14,Number 8,,ISSN 0973-9769,April 2019
Shanthi Rekha, S., Saravanan, P.,” Survey on power analysis attacks and its impact on intelligentsensor networks”, IET Wireless Sensor SystemsVolume 8, Issue 6, Pages 295-304, December2018.
Shanthi Rekha, S., Saravanan, P.” Low-Cost AES-128 Implementation for Edge Devices in IoTApplications”, Journal of Circuits, Systems and Computers2018.
P.Saravanan, P.Kalpana “Novel Reversible Design of Advanced Encryption StandardCryptographic Algorithm for Wireless Sensor Networks”, Wireless PersonalCommunications,Volume 100, Issue 4, pp 1427–1458, June 2018,
Umapathi K, MeenakshiSundaram N & Kalpana P The impact of the modified Poisson–Boltzmann model on protein bound to a lipid coated silicon nanowire field effect transistorbiosensor in an electrolyte environment” International Journal of Physics and Chemistry ofLiquids, Pages 1-11, April 2018.
Umapathi K, MeenakshiSundaram N & Kalpana P,” Investigation of the effect of finite-sized ionson the nanowire field-effect transistor in electrolyte concentration using a modified Poisson–Boltzmann model”, Physics and Chemistry of Liquids,Volume 56, Issue 2, 4 Pages 231-240,March 2018,
M.Santhanalakshmi, A.Ashna “An Improved Folded Cascode Amplifier With Low Power CurrentMirror Circuits “International Journal of Pure and Applied Mathematics” Volume 118 No. 10 Jan2018, pp.45-50
Navaneethakrishnan R, Santhanalakshmi M,Ramalatha Marimuthu,Kumaresan A,Alagumeenaakshi M “ADAS Headlamp for improved visibility” International Journal of Pureand Applied Mathematics” Volume 119 No. 12 2018, pp. 12541-12548.
A. Uma, P. Kalpana, T. Naveen Kumar, “Design of DA-Based FIR Filter Architectures UsingLUT Reduction Techniques”, Proceedings of the International Conference on Microelectronics,Computing & Communication Systems 2015 , Lecture Notes in Electrical Engineering, Springer,volume 453, 2018.
Mahalakshmi A, ‘Design of Testable Reversible Toggle Flip Flop’, International Journal ofElectronics, Electrical and Computational System, June 2017.
Sivashankari T and Priyadharshini N, ‘Comparison of Low Power Scan Chain Architectures’,International Journal of Electrical and Electronics Engineers, Vol. 9 Issue 1, Jan 2017.
P.Saravanan, P.Kalpana,” A novel approach to attack smartcards using machine learning method”,Journal of Scientific and Industrial Research,Volume 76, Issue 2, Pages 95-99, February 2017S. Hema Chitra, R. Yogeshwaran, “ VLSI Implementation of RSA Cryptography using FractionalChebyshev Polynomials”, Asian Journal of Research in Social Sciences and Humanities Vol. 7,No. 3, pp. 43-60, March 2017,
M. Jotheeshkumar and S. HemaChitra ‘Verilog Implementation of Optimized Elliptic CurveCrypto Processor for FPGA platform and its Performance analysis’, International Journal ForTrends in Engineering & Technology, Volume 15 Issue 1, July 2016.
Venkateswari, R, Subha Rani, S. and Rajalakshmi, K. ‘An ultra low power MICS band receiverfor implantable wireless body area networks’, International Journal of Information andCommunication Technology, Inderscience, Vol. 8, Nos. 2/3, pp.184–197, 2016.
P. Saravanan; P. Kalpana A novel approach to design A5/1 stream cipher using power analysisattack resistant reversible logic gates by International Journal of Enterprise Network Management(IJENM), Vol. 7, No. 1, 2016
K.Divya And M. Santhanalakshmi “A 14-GS/S, 3-Bit, At-Speed Testable ADC and DAC PairIn 0.18μm CMOS” International Journal of Advanced Research In Management, Architecture,Technology & Engineering, Vol.2 pp.33-39, March 2016.
M.Santhanalakshmi, “ A CMOS lock in amplifier for low power biomedical applications”,International Journal of biomedical Engineering and Technology”,Volume No.1,2016
A.Uma,” Design of Low power 2-4 compressor based 4-bit DADDA multiplier using two phaseclocking adiabatic logic”, International Journal for trends in Engineering and Technology(IJTET), Vol.14,issue 01,June,2016
M.Jotheesh kumar,S.Hema chitra,”verilog implementation of optimized Elliptic curve cryptoprocessor for FPGA Platform and its performance analysis”, International Journal for ntrends inEngineering & Technology,Volume 1,issue 1,PP 36 – 42,2016.
S.Hema Chitra and S.Naveenkumar, “A Synthesis flow of Behavioural level Designs in SystemCfor FPGA implementation”, International Journal of Applied Engineering Research ResearchIndia Publications, ISSN 0973-4562 Vol. 10 No.29, 2015
S.Hema Chitra and S.Nikilla, “ A Survey On Routing Intelligence In Network-On-ChipArchitecture For Real-Time Communication Services” International Journal of AppliedEngineering Research Research India Publications, ISSN 0973-4562 Vol. 10 No.29, 2015
SanthanaLakshmi, M. “A CMOS lock-in amplifier for low-power biomedical applications”International Journal of Biomedical Engineering and Technology, Vol. 20, No. 1, 2016.
P. Kalpana and P.Saravanan, “A Novel Implementation of SRAM PUF for Secure Applications”,International Journal of Applied Engineering Research Research India Publications, vol. 10, no.55, pp. 658-662, 0973-4562, June 2015
S.Allin Christe and M.Balaji, “FPGA Implementation of 2D Wavelet Transform of Image UsingXilinx System Generator”, International Journal of Applied Engineering Research Research IndiaPublications, Volume:10, ISSN: 09734562, Pg.No-22463-22466, May 2015
S.Allin Christe and R.Ayswarya, “Hardware-Sofware Co-design Approach of AES Algorithmusing Altium Nano Board”, International Journal of Applied Engineering Research Research IndiaPublications, ISSN: 09734562, Volume:10, Issue No.29, Pg.No-22425-22430, May 2015
M.Santhanalakshmi and K.Yasoda, “Verilog-A Implementation of Energy-Efficient SAR ADCsfor Biomedical Application”, International Journal of Applied Engineering Research ResearchIndia Publications, Volume : 10, No.29, Pg.No- 22359 – 22363, ISSN No. 09734562, May 2015
K.Rajalakshmi and A.Kandaswamy, “Reconfigurable FIR architecture for the filter bank ofspeech processor in Cochlear Implant”, International Journal of Applied Engineering ResearchResearch India Publications, Vo. 10.29 (2015), ISSN 0973-4562, 2015
P. Kalpana and P.Saravanan,” An energy efficient XOR gate implementation resistant to poweranalysis attacks”, Journal of Engineering Science and Technology,Volume 10, Issue 10, Pages1275-1292, October 2015
P. Kalpana and P.Saravanan, “Performance Analysis of Reversible Finite Field ArithmeticArchitectures Over GF(p) and GF(2m) in Elliptic Curve Cryptography”, Journal of Circuits,Systems and Computers World Scientific, vol. 24, no. 8. pp. 1550122-1550150, 0218-1266, June2015
P. Saravanan and P. Kalpana, "Energy Efficient Reversible Building Blocks Resistant ToPower Analysis Attacks," Journal of Circuits, Systems and Computers, vol. 23, no. 9,July 2014, pp. 1450127-1 - 1450127-40. ISSN : 0218-1266.
K.Rajalakshmi and A.Kandaswamy, “ Folded Architecture for Digital Gammat one filterused in speech processor of Cochlear Implant”, International Journal ETRI Journal, Vol.35,No.4, ISSN 1225 -6463, August 2013
U. Saravanakumar and R. Rangarajan, “Energy and throughput analysis of routing algorithms for2D mesh Network on chip”, Procedia Engineering, vol. 30, pp. 144-151, 2012, ISSN: 1877-7058.
U. Saravanakumar and R. Rangarajan, “Performance Explorations of Multicore Network on ChipRouter”, International Journal of Simulation: Systems, Science and Technology, vol. 13, no. 1,2012, pp. 36 – 42, ISSN: 1473-804X.
U. Saravanakumar and R. Rangarajan, “Design and performance evaluation of on chip networkrouters”, Journal of Theoretical and Applied Information Technology, vol. 52, no. 2, pp.211-218, 2013, ISSN: 1992-8645.
U. Saravanakumar and R. Rangarajan, “Simulation and analysis of multicast routingalgorithm for 2-D mesh network on chip”, Asian Journal of Scientific Research, vol. 6, no. 4,pp.754-762, 2013, ISSN: 1992-1454.
U. Saravanakumar, K. Rajasekar and R. Rangarajan, “Implementation of SchedulingAlgorithms for On Chip Communications”, International Journal of Computer Applications, vol.62, no. 14, pp. 35-38, 2013, ISSN: 0975-8887U. Saravanakumar, R. Rangarajan, R. Haripriya,R. Nithya and K. Rajasekar, “Cluster based hierarchical routing algorithm for network onchip”, Circuits and Systems, vol. 4, pp. 401-406, 2013, ISSN: 2153-1285.
S. P. Vimal, M. Kasiselvanathan and U. Saravanakumar, “A new SLM and PTS schemes forPAPR reduction in OFDM systems”, International Journal of Advanced Research ComputerCommunication Engineering, vol. 2, pp. 4236-4240,2013, ISSN: 2319-5940.
Mrs.M.Santhanalakshmi, P.T.Vanathi, “Implantable Neural Signal Amplifier forEpileptic Seizure Prediction”. Elsevier Ltd., 383426 – 3433, in 2012.
Mrs.M.Santhanalakshmi, P.T.Vanathi “A fully Integrated Neural signal acquisition amplifierfor Epileptic seizure prediction” in the International Journal of Electrical and ElectronicsEngineering (IJEEE), Vol-1 Issn. 2231 – 5284, Iss-4 in 2012.
Mrs.K.Rajalakshmi, A.Kandaswamy “A fractional delay FIR filter based on LagrangeInterpolation of farrow structure” in the International Journal of Electrical and ElectronicsEngineering (IJEEE) ISSN :2231 – 5284, Vol-1 Iss-4, in
2012.
K.Rajalakshmi, A.Kandaswamy , ‘VLSI Architecture of Digital Auditory Filter for SpeechProcessor of Cochlear Implant” International Journal on Computer Applications, 39(7):19-22,February 2012. Published by Foundation of Computer Science, New York, USA,BibTeX.
S.Allin Christe, M.Vignesh, Dr.A.Kandaswamy, ‘An efficient FPGA implementation of MRIimage Filtering and tumor characterization using Xilinx system generator” International Journalof VLSI design and Communication Systems ,Vol.2,No.4,Dec 2011.
M.SanthanaLakshmi, P.T Vanathi ‘An improved OTA for a 2nd order Gm-C LowPass Filter” European journal of Scientific research, Vol. 66, No.1, pp. 75-84, Nov.2011.
P.Saravanan,N.Renukadevi,G.Swathi.P.Kalpana, “A highthroughput ASIC implementation ofconfigurable AES processor’ International journal of Computer applications, 2011.
N.M. Sivamangai,K. Gunavathi. , ‘A Low Power SRAM Cell with High Read Stability’, ECTITransactions on Electrical Eng., Electronics, and Communications, Vol. 9, No. 1, pp. 16-22,2011.
N.M. Sivamangai,K. Gunavathi , ‘Design For Test Technique for Leakage Power Reduction inNanoscale Static Random Access Memory’, Journal of Computer Science, Vol. 7, No. 8, pp.1252-1260,2011.
N.M. Sivamangai,K. Gunavathi. , ‘Fault Detection in SRAM Cell Using Wavelet TransformBased Transient Current Testing Method’, International Journal of Latest Trends in SoftwareEngineering (IJLTSE), Vol. 1, No. 1, pp. 20-27,2011.
P.Kalpana ,K.Deepalakshmi , “Fault based testing of Low Noise Amplifiers”, CiiT,Internationaljournal of wireless communication, May 2010
M.Santhanalakshmi P.T.Vanathi, “An improved low voltage, low power class AB operationaltransconductance amplifier for mobile applications”, International journal of computer andnetwork security, Vol 2 No 5, may 2010
M.Santhanalakshmi “Second Order Gm-C Low Pass Filter for mobile Applications”International Journal of Electronics & telecommunication and instrumentation Engineering, Vol.3, No 1 2010, PP 09-14.
N.M. Sivamangai, K. Gunavathi,P. Balakrishnan , ‘A BICS Design to Detect Soft Error in CMOSSRAM’, International Journal on Computer Science and Engineering (IJCSE), Vol. 2, No. 3, pp.734-740, 2010.
M.Santhanalakshmi P.T.Vanathi, “A low power Gm-C low pass filter for mobile applications,Journal of scientific & industrial research, vol69,october 2010, pp750-755
M.Santhanalakshmi “Design of Biomedical Op amp” Journal of computer science,Vol. 5, No. 1Nov-Dec-2010, PP 63—69.
Ramesh J., Gunavathi K. , ‘A Novel Linear Ramp Generator for Analog and Mixed Signal Built-In Self-Test Applications’, International Journal of Electrical Engineering and EmbeddedSystems, Issue 1, pp. 21-32,2010.
Gunavathi K,Sampath. P , ‘A 900 MHz Image Reject Receiver with SS-LMS Calibration’,International Journal of Recent Trends in Engineering, Vol.2, No.6, pp.53-57, 2009.
Gunavathi K. Sampath. P, C.M.Preethi , ‘An Improved 70MHz CMOS Gm-C 2nd Order BandPass Filter for Wireless Systems’, International Journal on Electronic and Electrical Engineering(IJEEE), Vol.6, No.9, pp. 6-11, 2009.
P.Kalpana,K.Gunavathi, “ Test generation based fault detection in Analog VLSI circuits usingNeural Networks”, ETRI Journal, Apr 2009,pp 209-214.
P.Ramanathan, P.T.Vanathi , ‘Power Delay optimized adder for Multiply and Accumulate Units’,International Journal of Digital Signal Processing, Vol. 9, Issue 1, pp.11-17, 2009
P.Ramanathan, P.T.Vanathi , ‘High Speed Multiplier Design using Decomposition Logic’,Serbian Journal of Electrical Engineering, Vol.6, No.1, pp.33-42, 2009.
P.Ramanathan, P.T.Vanathi , ‘A Novel Power Delay Optimized 32-bit Parallel Prefix Adder forHigh Speed Computing’, International Journal of Recent Trends in Engineering, 2009.
P.Ramanathan,P.T.Vanathi , ‘Hybrid Prefix Adder Architecture for Minimizing the Power DelayProduct’, International Journal of Electronics, Circuits and Systems, Vol.3, No.1, pp.66-70, 2009.
P.Ramanathan, P.T.Vanathi, T.S.Keirthana,N. Sindhu Maheswari , ‘Comparative Analysis ofPower Delay Product Between Different Families with Achievement of Reduction usingDecomposition Algorithm’, International Journal of Power, Control, Signal and Computation,Vol.1, No.1, pp.41-46.,2010.
N.M. Sivamangai ,K. Gunavathi , ‘High Reliable Self Repairable Architecture for SRAM’,International Journal on Programmable Devices, Circuits and Systems (ICGST-PDCS), Vol. 9,Issue 1, pp.1-8, 2009.
Ramesh J., Vanathi P.T ,Gunavathi K. , ‘Fault Classification in Phase Locked Loops usingBack Propagation Neural Networks’, International Journal of Soft Computing Applications(IJSCA), No. 3, pp. 77-95.,2008
Ramesh J., Vanathi P.T ,Gunavathi K. , ‘Fault Classification in Phase Locked Loops usingBack Propagation Neural Networks’, Electronics and Telecommunication Research Institute
(ETRI) Journal, Vol. 30, No. 4, pp. 546-554. 2008
P.Kalpana, K.Gunavathi, “ Wavelet based fault detection in analog VLSI circuits using neuralnetworks”, Journal of Applied soft computing, Elsevier science, Sep2008, pp 1592-1598.
P.T.Vanathi, J.Ramesh, K.Gunavathi “Fault Classification in Phase Locked Loops using BackPropagation Neural Networks” in the International Journal of Soft Computing Applications, Issue3, June 2008, Page 77-95.
Ramesh J,Gunavathi K. , ‘A Novel Built-In Self-Test Architecture for Charge- Pump PhaseLocked Loops’, International Journal on Programmable Devices, Circuits and Systems (ICGST-PDCS), Vol. 7, Issue 1, pp.1-6.,2007
P.Kalpana,K.Gunavathi, “A novel implicit parametric fault detection method for analog/mixedsignal circuits using wavelets”, International journal on Programmable devices and circuits , vol7,May 2007.
P.Kalpana, K.Gunavathi, “A novel wavelet based testing method for analog VLSI circuits usingpseudorandom patterns”, AMSE Journal, France, vol 79, 2006.
M.Santhanalakshmi ,“Optimizing CMOS Circuit for Performance Improvements using AdiabaticLogic” published in Information Technology, Vol 6 No 3, 2007
P.Kalpana,K.Gunavathi , “Enhancing fault detection sensitivity of oscillation based test methodusing wavelets” Journal of system science and engineering, Vol 12& pp 62-70,Nov2005.(System society of India).
P.Kalpana,Dr.K.Gunavathi , “Behavioral Modeling And Fault Simulation Of System OnChips” acad journal& Vol 13,2004.
P.Kalpana,Dr.K.Gunavathi , “Fault oriented Test Pattern Generator for Digital to Analogconverters” acad journal& vol 13,2004.
International Conferences
S.Udaya Shankar and P.Kalpana, “Reliability and Circuit Timing Analysis with HCI and NBTI”,2nd International Conference on VLSI, Communication and Signal Processing (VCAS 2019),Motilal Nehru National Institute of Technology (MNNIT), Allahabad, October 21st -23rd, 2019.
A.Uma,C.Selvagangai,P.Kalpana “ Design of Chopper Stabilized Preamplifier for ECGmonitoring System”,IEEE 4th International Conference on Devices, Circuits and Systems(ICDCS),pp.126-129,March 2018
. E. Sugitha, M. Santhanalakshmi and Manoj Kumar Srinivasan “Modeling and Simulation ofphase-locked loop using verilog-A” International Conference on Advancements in Automation,Robotics and Sensing, PSG College of Technology,23 -24 June 2016.
K.Divya and M. Santhanalakshmi “A 14-GS/s, 3-bit, At-speed Testable ADC and DAC Pair in0.18μm CMOS” Second International Conference on Emerging Enhancement in Engineering andTechnology, Indra Ganesan College Of Engineering, Tiruchirappalli, 18-19 March 2016.
M. Santhanalakshmi and K. Yasoda, “Verilog-A implementation of energy-efficient SAR ADCsfor biomedical application” 19th International Symposium on VLSI Design and Test (VDAT),2015, Ahmedabad, 2015, pp. 1-6 is indexed in IEEEXplore.
K. Rajalakshmi, R. Nivedita, “VLSI Implementation of Smith–Waterman Algorithm forBiological Sequence Scanning”, Proceedings of the International Conference on Microelectronics,Computing & Communication Systems 2015 , Lecture Notes in Electrical Engineering, Springer,volume 453, 2018
K.R.RadhaKrishnan , S.Subha rani, ”Clock skew optimizied VLSI architecture for zero frequencyfilter”,2nd IEEE International Conference on VLSI Systems, Architecture, Technology andapplications (VLSI SATA 2016) Amrita Vishwa Vidyapeetham University,Bengaluru,10th – 12thJanuary 2016,
Hema Chitra S., “A High Speed Blowfish Cryptographic Algorithm For Hardware SecurityModule In Mobile Devices”, International Conference on Advancements in Automation, Roboticsand Sensing, Department of RAE, PSG College of Technology, Coimbatore, June 22-24, 2016.
V. Srihari ; P. Kalpana ; R. Anitha Spam over IP telephony prevention using Dendritic CellAlgorithm,” 3rd International Conference on Signal Processing, Communication and Networking,ICSCN 2015; Chennai; India; 26 March 2015 through 28 March 2015
A.uma, “Design of DA Based filter architectures using LUT reduction Techniques, 1stInternational conference on Micro-electronics, Computing & Communication systems (MCCS –2015),ISVE at Advanced Regional Telecom Training Centre, HazaribagRoad,Ranchi,Jharkhand,14 – 15th November,2015.
K.Rajalakshmi, “VLSI Implementation of Smith-Waterman algorithm for Bilogical sequencesscanning”, 1st International conference on Micro-electronics, Computing & Communication
systems (MCCS – 2015),ISVE at Advanced Regional Telecom Training Centre, HazaribagRoad,Ranchi,Jharkhand,14 – 15th November,2015.
J.Alexander, M.SanthanaLakshmi, M.Renuga “Low Power ENG Signal Acquisition Amplifier forEpileptic Seizure Prediction, presented at IEEE Students’ Conference on Electrical, electronics andComputer Science, March 1-22012. (SCEECS’12) Organized By Madhya Pradesh IEEE section &MoulanaAzad National Institute of Technology, Bhopal. It is indexed in IEEE Xplore.
P. Saravanan ; Nithya Rajadurai ; P. Kalpana , Power analysis attack on 8051 microcontrollers,5th IEEE International Conference on Computational Intelligence and Computing Research, IEEEICCIC 2014; Park College of Engineering and TekhnologyCoimbatore, Tamilnadu; India; 18December 2014 through 20 December 2014;
International Symposium
Shanthi Rekha, S. and Saravanan, P., “Threshold Implementation of a Low-Cost CLEFIA-128Cipher for Power Analysis Attack Resistance ”, Presented at International Symposium on VLSIDesign and Test (VDAT-2019) at IIT Indore 4th July – 6th July, 2019, Proceedings to be includedin Springer .
Saravanan, P,Mehtre BM,” A Novel Approach to Detect Hardware Malware Using HammingWeight Model and One Class Support Vector Machine” Presented at International Symposium onVLSI Design and Test (VDAT-2018) at TCE Madurai 28th June – 30th June 2018. Proceedings tobe included in Springer
Shanthi Rekha, S. and Saravanan, P., “Low Cost Circuit Level Implementation of Present-80 S-Box”, Presented at International Symposium on VLSI Design and Test (VDAT-2017) at IITRoorkee, 29th June – 2nd July, 2017, Proceedings to be included in Springer LNCS.
P. Saravanan ,P.Kalpana, V.Prcethisri.,Sneha, V. Power analysis attack using neural networkswith wavelet transform as pre-processor, 18th International Symposium on VLSI Design and Test,VDAT 2014; Coimbatore; India; 16 July 2014 through 18 July 2014.
National Journals
Lalitha Kathambari D, Kalpana P and Uma A, ‘Design of Low power successive approximationADC using segmented architecture’, National Journal of Technology, ISSN: 0973-1334, March
2017.
Dinesh R and P Saravanan, ‘A countermeasure for leakage power analysis attacks oncryptographic processor’, National Journal of Technology, ISSN: 0973-1334, June 2017.
Subha Rani S, Radhakrishnan K R, Varun Power Aware Simulation And Verification of 16-BitALU Using Unified Power Format Standards’, National Journal of Technology, ISSN: 0973-1334, June 2017
S.Hema Chitra (Second Author) and N.Vinay Reddy,” A Pipelined Fused Processing Unit forDSP Applications”, National Journal of Technology, ISSN-0973-1334, Volume:11 IssueNo.1, Category : H, PSG College of Technology, Mar 2015K.Divya And M. Santhanalakshmi “A 4-bit At-Speed Testable Two step Flash ADC and DACPair In 0.18μm CMOS”, National Journal of Technology, Vol. 13, Iss. 3 Sep 2017
S.Allin Christe and M.Balaji, “ HW/SW Co-design of various Image Processing AlgorithmsUsing Xilinx System Generator”, National Journal of Technology, ISSN: 0973-1334, Volume:11Issue No.1, Pg.No-1-9, Category : H, PSG College of Technology, Mar 2015
K.Rajalakshmi, Swathi Gandi and A.Kandaswamy,” Design of variable fractional delay basedFIR filter’, National journal of Technology, ISSN-0973-1334 Vol.9,No.1 March 2013
U. Saravanakumar, R. Rangarajan and K. Rajasekar, “Hardware Implementation of PipelineBased Router Design for On-Chip Network”, ICTACT Journal on Communication Technology,vol. 3, no. 4, pp. 646-650, 2012, ISSN: 0976-0091.
P.Ramanathan and P.T.Vanathi, ‘Novel Decomposition Algorithm for Power DelayOptimization in Wallace and Carry Save Multipliers’, National Journal of Technology. 2009.
J.Saranya, P.Kalpana,” Testing of Digital VLSI circuits for resistive bridging faults”, Nationaljournal of Technology, vol 3 ,June 2007
M.Santhanalakshmi , “Improved Adiabatic Logic for Efficient Charge Recovery”National Journal of Technology of PSG College of Technology, Coimbatore-4,Vol2& No 2 June 2006.
P.Vijayakumar,K.Gunavathi , “Performance Improvement of CMOS Circuits with concurrentApplication of Resonant Charging and Retiming Algorithm” National Journal of Technology&2005.
