10: Circuit Families 1

Pseudo-nMOS Logic

( Ratioed Logic)

10: Circuit Families 2

Introduction

• What makes a circuit fast? – I = C dV/dt -> tpd (C/I) DV – low capacitance – high current – small swing

• Logical effort is proportional to C/I • pMOS are the enemy!

– High capacitance for a given current

• Can we take the pMOS capacitance off the input? • Various circuit families try to do this…

B

A

11

4

4

Y

3

Ratioed Logic

VDD

VSS

PDNIn1In2In3

F

RLLoad

VDD

VSS

In1In2In3

F

VDD

VSS

PDNIn1In2In3

F

VSS

PDN

Resistive DepletionLoad

PMOSLoad

(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS

VT < 0

Goal: to reduce the number of devices over complementary CMOS

4

Ratioed Logic VDD

VSS

PDN

In1

In2

In3

F

RLLoad

ResistiveN transistors + Load

• VOH = VDD

• VOL = RPN

RPN + RL

• Assymetrical response

• Static power consumption

•

• tpL= 0.69 RLCL

5

Active Loads VDD

VSS

In1

In2

In3

F

VDD

VSS

PDN

In1

In2

In3

F

VSS

PDN

Depletion

Load

PMOS

Load

depletion load NMOS pseudo-NMOS

VT < 0

10: Circuit Families 6

Pseudo-nMOS

• In the old days, nMOS processes had no pMOS

– Instead, use pull-up transistor that is always ON

• In CMOS, use a pMOS that is always ON

– Ratio issue

– Make pMOS about ¼ effective strength of pulldown network

Vout

Vin

16/2

P/2

Ids

load

0 0.3 0.6 0.9 1.2 1.5 1.8

0

0.3

0.6

0.9

1.2

1.5

1.8

P = 24

P = 4

P = 14

Vin

Vout

Pseudo-nMOS

10: Circuit Families 7

Pseudo-NMOS VTC

10: Circuit Families 8

Pseudo-nMOS Design

Size of PMOS VOL

Static Power

Dissipation tpLH

4 0.693 V 564 mW 14 ps

2 0.273 V 298 mW 56 ps

1 0.133 V 160 mW 123 ps

0.5 0.064 V 80 mW 268 ps

0.25 0.031 V 41 mW 569 ps

10: Circuit Families 9

10: Circuit Families 10

Pseudo-nMOS Gates

• Design for unit current on output

to compare with unit inverter.

• pMOS fights nMOS

• Iout = 4I/3 – I/3

Inverter NAND2 NOR2

AY

B

AY

A B

gu =

gd =

gavg

=

pu =

pd =

pavg

=

Y

gu =

gd =

gavg

=

pu =

pd =

pavg

=

gu =

gd =

gavg

=

pu =

pd =

pavg

=

f

inputs

Y

10: Circuit Families 11

Pseudo-nMOS Gates

• Design for unit current on output

to compare with unit inverter.

• pMOS fights nMOS

Inverter NAND2 NOR2

4/3

2/3

AY

8/3

8/3

2/3

B

AY

A B 4/34/3

2/3

gu = 4/3

gd = 4/9

gavg

= 8/9

pu = 6/3

pd = 6/9

pavg

= 12/9

Y

gu = 8/3

gd = 8/9

gavg

= 16/9

pu = 10/3

pd = 10/9

pavg

= 20/9

gu = 4/3

gd = 4/9

gavg

= 8/9

pu = 10/3

pd = 10/9

pavg

= 20/9

f

inputs

Y

10: Circuit Families 12

Pseudo-nMOS Design

• Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H

• G = 1 * 8/9 = 8/9

• F = GBH = 8H/9

• P = 1 + (4+8k)/9 = (8k+13)/9

• N = 2

• D = NF1/N + P =

In1

Ink

Y

Pseudo-nMOS

1

1H

4 2 8 13

3 9

H k

10: Circuit Families 13

Pseudo-nMOS Power

• Pseudo-nMOS draws power whenever Y = 0

– Called static power P = IDDVDD

– A few mA / gate * 1M gates would be a problem

– Explains why nMOS went extinct

• Use pseudo-nMOS sparingly for wide NORs

• Turn off pMOS when not in use

A B

Y

C

en

10: Circuit Families 14

Ratio Example

• The chip contains a 32 word x 48 bit ROM

– Uses pseudo-nMOS decoder and bitline pullups

– On average, one wordline and 24 bitlines are high

• Find static power drawn by the ROM

– Ion-p = 36 mA, VDD = 1.0 V

• Solution:

pull-up pull-up

static pull-up

36 μW

(31 24) 1.98 mW

DDP V I

P P

Pseudo-NMOS Design

• Pseudo-nMOS gates will not operate correctly if VOL>VIL of the driven gate.

• This is most likely in the SF corner.

• Conservative design requires extra weak pMOS.

• Another choice is to use replica biasing.

• Idea comes from analog design.

• Replica biasing allows 1/3 the current ratio rather than the conservative ¼ ratio of earlier.

10: Circuit Families 15

Replica Biasing

10: Circuit Families 16

Ganged CMOS

10: Circuit Families 17

Ganged CMOS

A B N1 P1 N2 P2 Y

0 0 OFF ON OFF ON 1

0 1 OFF ON ON OFF ~0

1 0 ON OFF OFF ON ~0

1 1 ON OFF ON OFF 0

10: Circuit Families 18

19

Improved Loads

A B C D

F

CL

M1M2 M1 >> M2Enable

VDD

Adaptive Load

Improved Loads

10: Circuit Families 20

21

Improved Loads (2)

Differential Cascode Voltage Switch Logic (DCVSL)

22

DCVSL Example

B

A A

B B B

Out

Out

XOR-NXOR gate

23

DCVSL Example

DCVSL Transient Response

10: Circuit Families 24

25

Pass-Transistor Logic In

pu

ts

Switch

Network

OutOut

A

B

B

B

• N transistors

• No static consumption

Example: AND Gate

10: Circuit Families 26

NMOS-Only Logic

10: Circuit Families 27

28

NMOS-Only Switch

29

NMOS Only Logic: Level Restoring Transistor

• Advantage: Full Swing

• Restorer adds capacitance, takes away pull down current at X

• Ratio problem

Restorer Sizing

10: Circuit Families 30

10: Circuit Families 31

LEAP

• LEAn integration with Pass transistors

• Get rid of pMOS transistors

– Use weak pMOS feedback to pull fully high

– Ratio constraint

B

S

S

AYL