library IEEE;use IEEE.STD_LOGIC_1164.ALL;-- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned values--use IEEE.NUMERIC_STD.ALL;-- Uncomment the following library declaration if instantiating-- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;ENTITY ps2_keyboard IS GENERIC ( deb_cycles: INTEGER := 200; --4us for debouncer (@50 MHz) idle_cycles: INTEGER := 3000); --60us (>1/2 period ps2_clk) PORT ( clk: IN BIT; --system clock (50 MHz) ps2clk: IN BIT; --clk from keyboard (1017 kHz) ps2data: IN BIT; --data from keyboard ssd: OUT BIT_VECTOR(6 DOWNTO 0));--data out to SSD END ps2_keyboard; ---------------------------------------------------------------------- ARCHITECTURE ps2_keyboard OF ps2_keyboard IS SIGNAL deb_ps2clk: BIT; --debounced ps2_clk SIGNAL deb_ps2data: BIT; --debounced ps2_data SIGNAL data, dout: BIT_VECTOR(10 DOWNTO 0); SIGNAL idle: BIT; --'1' means data line is idle SIGNAL error: BIT; --'1' when start, stop, or parity wrong BEGIN ---------Debouncer for ps2clk:--------------- PROCESS (clk) VARIABLE count: INTEGER RANGE 0 TO deb_cycles; BEGIN IF (clk'EVENT AND clk='1') THEN IF (deb_ps2clk=ps2clk) THEN count := 0; ELSE count := count + 1; IF (count=deb_cycles) THEN--VHDL Design of Serial Communications Circuits 385 deb_ps2clk