Project Report on Software modem

7/29/2019 Project Report on Software modem

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EL-518

Real Time Embedded Systems

Project Report

On

SOFTWARE MODEM

Prepared by: Guided by:

1. Pankaj Dhalvaniya - 201111008 Prof. Rahul Dubey.2. Darshal Patel - 2011110113. Mayur Vansadiya - 2011110164. Anand Kapadiya - 2011110195. Pratik Shah - 201111020


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ACKNOWLEDGEMENT

We wish to express our sincere gratitude to Prof. Rahul Dudey, for providing us an

opportunity to do our project work on SOFTWARE MODEM. We also wish to express our

gratitude to the Lab assistant- Mr. Bhargav and Mrs. Firoza who rendered their help duringthe period of our project work. Last but not least we wish to avail ourselves of this

opportunity, to express a sense of gratitude and love to our friends for their manual

support, strength, help and for everything .

Place:- DA-IICT

Gandhinagar

Date: 20-Apr-2012


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INDEXPg.No.

ABSTRACT4

Chapter1: Theoretical background

1.1 Theory of Operation and Requirements.5

1.2 Requirements6

1.3 Block Diagram..6

1.4 Transmission Scheme.7

1.5 Receiver Scheme7

Chapter2: Our approach to the project

2.1 Transmitter Design ........................................................................................8

2.1.1 MATLAB implementation .......................................................................... 8

2.1.2 MATLAB Plots of transmitter ..................................................................... 9

2.1.3 Implementation on controller ................................................................ 10

2.1.4 Controller Code for transmitter............................................................... 11

2.1.5 Testing of controller code ....................................................................... 13

2.2 Receiver Design ...........................................................................................14

2.2.1 MATLAB Implementation ....................................................................... 14

2.2.2 Difference Equation of Low pass Filter ................................................... 14

2.2.3 MATLAB Code ......................................................................................... 17

2.2.4 Output ..................................................................................................... 19

2.2.5 Results .................................................................................................... 19


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Appendix ..20

References ..25

Websites ...25


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ABSTRACT

A Softmodem, or software modem, is a modem with minimal hardware capacities,

designed to use a host computer's resources (mostly CPU power and RAM but sometimes

even audio hardware) to perform most of the tasks performed by dedicated hardware in a

traditional modem.

Main task in the software modem project is to implement a modem (which is

conventionally being implemented using hardware) in a micro controller. As modem uses

FSK modulation, we have to do FSK modulation in controller, transmit it after DAC

conversion and decode it on receiver.


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Chapter1: Theoretical Background

1.1 Theory of Operation and Requirements:

The modem will use frequency-shift keying (FSK), a technique used in 1200-baud

modems. The FSK scheme transmits sinusoidal tones, with 0 and 1 assigned to different

frequencies. Sinusoidal tones are much better suited to transmission over analog phonelines than are the traditional high and low voltages of digital circuits.

The 01 bit patterns create the chirping sound characteristic of modems. The analog

input is sampled and the resulting stream is sent to two digital filters (such as an FIR filter).

One filter passes frequencies in the range that represents a 0 and rejects the 1-bandfrequencies, and the other filter does the converse. The outputs of the filters are sent to

detectors, which compute the average value of the signal over the past n samples. When

the energy goes above a threshold value, the appropriate bit is detected. We will send data

in units of 8-bit bytes. The transmitting and receiving modems agree in advance on the

length of time during which a bit will be transmitted (otherwise known as the baud rate).

But the transmitter and receiver are physically separated and therefore are not

synchronized in any way.


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1.2 Requirements:

Inputs:- Input to modulator (transmitter) is a stored data file. Input to demodulator(receiver) is a FSK modulated signal.

Outputs:- Output of modulator is FSK modulated signal and output of demodulator isa bit stream of 1 and 0.

Functions:-Transmitter: Sends data from memory in 8-bit bytes plus start bit.

Receiver: Automatically detects bytes and reads bits.

1.3 Block Diagram:

I

Transmitter Block: It takes data from the Store Digital Data, generate samples of FSKsignal using timer and look-up table. DAC converts samples to analog FSK signal.

Receiver Block: It takes FSK signal as input. Its first block is an ADC. ADC gives samples to

the digital filter. Filter detects 0 and 1 and combines it according to proper frame.


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1.4 Transmission Scheme:

The best way to generate waveforms that retain the proper shape over long intervals

is table lookup. Software oscillators also can be used to generate periodic signals. Figure

shows an analog waveform with sample points and the C code for these samples. Tablelookup can be combined with interpolation to generate high-resolution waveforms without

excessive memory costs, which is more accurate than oscillators because no feedback is

involved. The required number of samples for the modem can be found by experimentation

with the analog/digital converter and the sampling code. These discrete samples pass from

D/A to generate analog signal to be transmitted on transmission line.

1.5 Receiver Scheme:

The receiver will detect the start of a byte by looking for a start bit, which is always 0.

By measuring the length of the start bit, the receiver knows where to look for the start of

the first bit. However, since the receiver may have slightly misjudged the start of the bit, it

does not immediately try to detect the bit.


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Chapter2: Our Approach to the project

2.1 Transmitter Design

Transmitter as explained consists of FSK modulation and DAC conversion. FSK

consists of transmitting to different frequencies for 1 and 0 bit. Actual frequencies usedfor modem has very less difference (around 200hz) between two frequency. Considering we

have to implement it on controller ATMEGA32 which operates on 1MHz and an SPI based

DAC, we have taken large difference and lower frequencies. We have taken frequency of

200Hz for 0 and 600Hz for 1.

Another consideration is time taken to send one bit. We have taken 200Hz frequency

for 0. For proper detection at receiver we want that we send as many cycles of sin wave as

possible. So to make sure that we get 10 cycles of it for transmitting 0, we have taken bit

= (1

200) 1 0 = 5 0.

2.1.1 MATLAB Implementation

We have used MATLAB to check the functionality of our design before it is

implemented to the controller. This has really helped us because MATLAB provides batter

testing and debugging of written code.

Given below is a MATLAB code for FSK generation:

t = 0.0001:0.0001:.5;

t1 = 2.5+2.5*sin(2*pi*200*t); % 200hz sin wave with peak to peak

amplitude of 5v and DC shifted by 2.5v to remove negative voltages

t2 = 2.5+2.5*sin(2*pi*600*t); % same as abobe but frequency is

600hz.

z=zeros(1,200); % to take bit '1'

o=ones(1,200); % to take bit '0'

l=[o z z o z o o z z z o o o o o o z z o o o z z z o]; %data bytes

010110001 and 10001110 added with start bit and idle bits

grid on;

plot(t,l); %plot input data stream

k = (1-l).*t1 + (l).*t2; %FSK modulation

figure;

plot(t,k); %plot fsk modulated wave


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2.1.2 Matlab Plots of transmiiter:

Fig 2.1 Input bit pattern

Fig 2.2 FSK modulated wave

As you will see there is no actual relation between MATLAB code for transmitter and

its processor implementation but this code will be used to check the receiver functionality.


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2.1.3 Implementation on controller

We have used ATMEAG32 controller and MAX5500 DAC to implement transmitter.

To generate sin wave I have taken 20 samples. These samples have been decided for 12 bit

ADC and 5v reference voltage. These samples are: 2680, 3251, 3704, 3995, 4095, 3995,

3704, 3251, 2680, 2048, 1415, 844, 391, 100, 0, 100, 391, 844, 1415, 2048.Time period at which these samples are applied to DAC, decides the frequency of sin

wave. To generate sin waves of two different frequencies we have to change the time

period between two samples.

To generate frequency of 200Hz for transmitting 0, time period between two

samples can be decided as:

=

1200

20

= 250

And to generate 600Hz sin wave, time period between two samples can be decided as:

=

160020

= 83.33

So, if we want to transmit 0 time between two samples should be 250us and if we

want to transmit 1 then samples are same but they should be sent at 83.33us interval.

We have done this using timer0. Timer0 is used with no clock prescaling and with

timer overflow mode. As crystal frequency used is 1Mhz, to get 250us delay timer0 must be

loaded with 256-250=6. And to get 83.33us delay it must be loaded with 256-83=173.

As explained previously we have selected time period of 50ms to send a single bit. So

after every 50ms we have to change the frequency of transmission according to the

decision on bit. To get this 50ms interval we have used a timer1 in overflow mode with

clock prescaling of 64. So one increment will take64

106= 64. So, it must be loaded with

= 65536

50103

64106 = 65536 781 = 64755

Max5500 is SPI compatible DAC. So we have used controller as SPI master to transmit

samples. SPI clock is selected as fosc/2. That is 500KHz.


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2.1.4 Controller Code for transmitter:

#include

#include

#include

int sample[20] =

{2680,3251,3704,3995,4095,3995,3704,3251,2680,2048,1415,844,391,100,0,100,391,844,1415,204

8}; // 20 samples for 1 complete cycle assuming 5v Vdd & 12 bit DAC

unsigned char data[8]={1,0,0,1,1,1,0,1}; // 1 frame to be sent. We have sent same data again and

again for simplicity

int tcount;

int i=0;

int j=0;

void SPI_MasterTransmit(int iData) // function to transmit data on SPI assuming controller as

master

{

/* Start transmission of higher 8 bits*/

SPDR = iData>>8;

/* Wait for transmission complete */

while(!(SPSR & (1


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}

}

else

{

tcount=173; //generate frequency of 600hz for

i=-1;

}i=i+1;

TCNT1=64755; // for 50ms interval as we have decided 50ms time to transmit one bit

TCNT0=tcount;

TIMSK=0X05; // enable timer0 on exit

}

SIGNAL(SIG_OVERFLOW0) //ISR of timer 0 for transmiting a sample

{

TCNT0=tcount;SPI_MasterTransmit(sample[j]|0x3000); //send sample for transmission of SPI.

0x3000 is ored with sample values of 12 bits to add 4 control(0011) bits in MSB.

j=j+1;

if(j==20)

j=0;

}

void SPI_MasterInit(void) // to initialize controller as SPI master

{

/* Set MOSI and SCK output, all others input */

DDR_SPI = (1


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2.1.5 Testing of controller code

We have written above code in AVR Studio. We have successfully builded and

debugged it in AVR Studio.

To check the SPI is working perfectly working or not we have used CDLogic a logic

analyzer from SLS. It is a device which can display signals on 36 channels at a time. It can be

connected to PC via USB. So it displays waveform on our PC screen. So it basically converts

our PC into a CRO. Its advantage is that we can see signal for long period of time which is

not possible in CRO. So it is very useful to test serial communication lines.

We have connected MOSI and SCK pins of microcontroller to two of its channel.

These are the master SPI pins which get connected to slave DAC. The MOSI pin is

connected to PodA:2 and SCK is connected to PODA:3.

The waveforms we have got is shown below:

Fig 2.3 MOSI and SCK data on CDLogic

As seen the 16 bits of samples are send at every SCK clock. And two samples are

separated by around 85us. So these samples are of frequency 600Hz. This indicates correct

functionality of our code. We have verified that SCK is 2us, so its frequency is 500KHz.

Clearly these type of waveforms cant be seen on CRO. So CDLogic is quite useful to

see address or data information on serial lines.


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2.2 Receiver Design

2.2.1 MATLAB Implementation:We have written MATLAB code for receiver block. We havent used any special

MATLAB command. So this code can be easily implemented in controller with proper ADC

sampling time configuration.Receiver contains FSK demodulator. So it must be able to first detect the start bit and

then correctly sample next 8 bits. In our implementation we have done the same thing.

First of all we need to differentiate between the two frequencies. For that we are

using a low pass filters difference equation implementation.

2.2.2 Difference Equation of Low pass Filter:

Consider the first order analogue low-pass filter below with input and output voltages x(t)

and y(t) respectively:-

R

C

x(t) y(t)

Since the current in R is equal to the current in C it follows that:

dt

tdyc

R

txty

Therefore the differential equation for this circuit is:

txdt

tRCdyty

The system function is:

RCs

sHa

1

1

To convert this equation in to difference equation, By bi-linear transformation Put,

=2

(

11

11)

Here T is sampling frequency. We have taken it as 100us.

Fig. 6.1


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So we get,

=

=

1+1

1+1+2

(

11

11)

By simplifying this equation and taking Inverse Z-transform, we get

1

10

nybnxany

Where

T

RCa

1

1

0 and RCTRC

b

1

By putting T=100 us and =1

2=318 us, we get a0=0.1116 and b1=0.8884.

So our differential equation will be,

18884.01116.0 nynxny

Here y[n] is present output, y[n-1] is previous output and x[n] is a present input. We

have used this difference equation because it can be easily implemented in the controller.

As its cutoff frequency is 200Hz. 200Hz signal will be get less attenuation than 600Hz signal.

So, from the amplitude levels we can differentiate the two frequencies.

So in our MATLAB code we have first given the FSK signal to it and according to its

output we have taken decision of 1 or 0 bit. Input output waveforms to the LPF is given on

next page.


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Figure 2.4 Input to the LPF (FSK modulate wave)

Figure 2.5 Output of the LPF (high frequency attenuated)


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Detection of a start bit: We know when a line is idle a 1 is transmitted and to indicate a

start of frame a 0 is transmitted. So as seen in Fig3.2 as soon as start bit come we will get

high amplitude. To reduce the wrong prediction of start bit due to noise we have kept a

logic that will make sure noises are neglected.

Sampling of data bits: We have taken sampling time of 100us and our one bit is 50ms long.So we will get 50ms/1000us=500 samples for a single bit. Now to reduce the error due to

some shift on the edges we have ignored first 100 samples and last 100 samples. Thus we

have taken middle 300 samples to decide whether the bit is 1 or 0.

2.2.3 MATLAB Code:The code combines transmitter and receiver part.

clc;

close all;

clear all;

flag=0;

count=0;

ideal=1;

j=1;

t = 0.0001 :0.0001:1.25; %Sampling time is 100u sec.

t1 = 2.5+2.5*sin(2*pi*200*t); %200hz sin wave with peak to

peak amplitude

of 5v and DC shifted by 2.5v

to remove

negative voltages

t2 = 2.5+2.5*sin(2*pi*600*t); %same as above but frequency is

600hz.

z=zeros(1,500); %to take bit '1'

o=ones(1,500); %to take bit '0'

%data bytes 010110001 and 10001110 added with start bit and idle bits

l=[o z z o z o o z z z o o o o o o z z o o o z z z o];

grid on;

plot(t,l); %To plot input data stream

k = (1-l).*t1 + (l).*t2; %FSK modulation

figure;

plot(t,k); %To plot the FSK modulated wave

start=0; %flag for detection of start

bit

idle=1;

ns=0; %To count samples of bit

y1(1)=0;

z=1; %counter for data bytes

complete=0;

for i=2:12500

%Difference equation of low pass filter with 200Hz cutoff frequency

y1(i)=.1116*k(i)+(0.8884)*y1(i-1);


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if(y1(i)>=3.5 && idle==1) %To Identify the start bit

ns=ns+1; %Start counting count the

sample

if(ns==2) %start bit detected

idle=0;

start=1; %Flag for excluding the start

bit from Data byte

end

end

if(idle==0) %To demodulate the FSK signal

ns=ns+1;

if(ns>100 || ns3.5) %Detection of 0's samples

count=count+1; %Count samples that goes above

3.5 level

end

if(ns==400)

if(count>20)

ans(z,j)=0; %Zero detected

else

ans(z,j)=1; %One detected

end

j=j+1; %For the next bit in Data byte

if(j==9) %After one Frame of Data is

Received

complete=1; %Flag for making line idle

z=z+1; %For next Data byte

j=1; %For 1st byte of next data byte

start=0; %Flag for detecting start bit

count=0;

end

end

end

end

if(ns==500) %To check whether samples of

All 1's or 0's has been

received or not

ns=0; %Initialize Count for the next

bit

if(start==1)

start=0; %Flag for Excluding start bit

end

if(complete==1) %After receiving whole data

byte, make line idle

idle=1;

complete=0;

end

count=0;


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end

end

end

figure;

plot(t,y1) %To plot the output of low pass

filter

ans %To show all received data

byte in command window

2.2.4 OUTPUT:

Figure 2.6 detected bytes on the command window

2.2.5 Results:

The input bit stream was given as l variable. Input bit stream was1 0 0 1 0 1 1 0 0 0 1 1 1 1 1 1 0 0 1 1 1 0 0 0 1

As seen from the output the data bytes have been detected correctly, which shows proper functionality of

our code.

Start bit Ideal Line Data b tes


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Appendix

ATMEGA32 Datasheet

Pin Diagram:

ATMEGA32 Special Features:

High-performance, Low-power AtmelAVR 8-bit Microcontroller

Advanced RISC Architecture

131 Powerful Instructions Most Single-clock Cycle Execution 32 8 General Purpose Working Registers Fully Static Operation Up to 16 MIPS Throughput at 16MHz On-chip 2-cycle Multiplier

High Endurance Non-volatile Memory segments

32Kbytes of In-System Self-programmable Flash program memory 1024Bytes EEPROM


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2Kbytes Internal SRAM Write/Erase Cycles: 10,000 Flash/100,000 EEPROM Data retention: 20 years at 85C/100 years at 25C(1) Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program

True Read-While-Write Operation

Programming Lock for Software Security JTAG (IEEE std. 1149.1 Compliant) Interface

Boundary-scan Capabilities According to the JTAG Standard Extensive On-chip Debug Support Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

Peripheral Features

Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode Real Time Counter with Separate Oscillator Four PWM Channels 8-channel, 10-bit ADC 8 Single-ended Channels 7 Differential Channels in TQFP Package Only 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x Byte-oriented Two-wire Serial Interface Programmable Serial USART Master/Slave SPI Serial Interface Programmable Watchdog Timer with Separate On-chip Oscillator On-chip Analog Comparator

Special Microcontroller Features

Power-on Reset and Programmable Brown-out Detection Internal Calibrated RC Oscillator External and Internal Interrupt Sources Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby


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I/O and Packages

32 Programmable I/O Lines 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF

Operating Voltages

- 2.7V - 5.5V for ATmega32L- 4.5V - 5.5V for ATmega32

Speed Grades

- 0 - 8MHz for ATmega32L- 0 - 16MHz for ATmega32

Power Consumption at 1MHz, 3V, 25C

- Active: 1.1mA- Idle Mode: 0.35mA- Power-down Mode: < 1A- 8-bit Microcontroller with 32Kbytes In-System Programmable Flash ATmega32


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MAX5500 datasheet:

Features:

Four 12-Bit DACs with Configurable Output Amplifiers +5V or +3V Single-Supply Operation Low Supply Current: 0.85mA Normal Operation 10A Shutdown Mode (MAX5500) Force-Sense Outputs Power-On Reset Clears All Registers and DACs to Zero Capable of Recalling Last State Prior to Shutdown SPI/QSPI/MICROWIRE Compatible Simultaneous or Independent Control of DACs through 3-Wire Serial Interface User-Programmable Digital Output Guaranteed Over Extended Temperature Range (-40C to +105C)

PIN Diagram:


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Functional Diagram:

16 bit data format:

Timing Diagram:


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References:

1. Computers as components by wyne wolf (section 5.11)2. ATMEGA32 datasheet3. MAX5500 datasheet

Websites:

1. Low pass filer on Wikipedia for difference equation of low pass filter.Link:http://en.wikipedia.org/wiki/Low-pass_filter

2. For CDLogic logic analyzerhttp://www.slscorp.com/products/test-a-measurement/logic-analyzer.html
http://en.wikipedia.org/wiki/Low-pass_filterhttp://en.wikipedia.org/wiki/Low-pass_filterhttp://en.wikipedia.org/wiki/Low-pass_filterhttp://www.slscorp.com/products/test-a-measurement/logic-analyzer.htmlhttp://www.slscorp.com/products/test-a-measurement/logic-analyzer.htmlhttp://www.slscorp.com/products/test-a-measurement/logic-analyzer.htmlhttp://en.wikipedia.org/wiki/Low-pass_filter

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Project Report on Software modem