Project Overview - Eindhoven University of Technology · Project Overview. 8-Dec-04 H. Corporaal -PreMaDoNA kickoff 2 Agenda 15.00 Opening and Overview Henk Corporaal Bart Mesman

PreMaDoNAkickoff 15 oct 2004

Henk Corporaal

Project Overview

8-Dec-04 H. Corporaal - PreMaDoNA kickoff 2

Agenda� 15.00 Opening and Overview Henk Corporaal

Bart Mesman� 15.30 Implementation and Demonstrator Patrick Groeneveld� 15.40 Project Management Bart Mesman� 15.55 Application track Peter de With

Gerard de Haan� 16.05 Simulation track Sander Stuijk

Orlando Moreira� 16.15 5 minutes coffee/thea break� 16.20 Network Architecture Layer Jef van Meerbergen

Kees GoossensMarco Bekooij

� 16.30 Design Flow Bart TheelenBart Mesman

� 16.40 Resource Management and QoS Jef van MeerbergenMilan PastrnakPeter Poplavko

� 16.50 Discussion� 17.00 Reception� 17.30 Close


PreMaDoNAPredictable Matching of Demands onNetworked Architectures

� Partners:� Philips Research� Philips Semiconductors� LogicaCMG� TU/e


Overview� Problem statement� NOC� Predictable design

� QoS management� Design flow� Architectural support for predictable design

� Work packages� Links with other projects (intern; extern)


Problem statement

� Observations

� Problem

� Solution


Observation 1:The 3 Cs

� Convergence of 3 Cs

computers, communications and consumer

electronics

� The computer enters the 3rd fase

computing power - networking - intelligent processing

� The world is 1 network

wherever, whenever, all information and communication available

��


Observation 2: Current HW design practise

Logic

System

AlgorithmR/T

circuit

Behaviour Structure

Physical

Y-Chart (Gajski-Kuhn)

� Design Flow is path in Y chart

� Till RT-level largely manual flow

Start

Done !


Integration

TaskTask

Task

Systempeople

C

ASM

Softwarepeople

vhdl

verilogHardware

people

Paper spec

Observation 3: Informal system specification


Observation 4: Design productivity

• Yes, we can fabricate the ICs, but …• Can we design them ?• Can we program them ?

103

102

101

4 8 12 16 year

complexity

HW gap

SW gap

Process technology + 58%

HW design productivity +21 %

SW productivity + 8 %


Video

3D

Rel. CPU-load for 15 fps

0%200%400%600%800%

1000%1200%

Order ofMagnitude

0 %

25 %

50 %

75 %

100 %

0 50 100 150 200 250 300

Frame (IPPP ...)

Load (Sequence: weather, VO1, binary shape, 10Hz, 112 kbit/s, QCIF)

Factor 2

P. Kuhn, G. Diebel, “ Complexity Analysis of the MPEG-4 VM 8.0,”ISO/IEC JTC1/SC29/WG11/MPEG97/m2862, Fribourg, October 1997*

*

Obervation 5:More dynamism


Observation 6: Memory gap“ data where are you?”

µProc:55%/year

CPU

DRAM:7%/yearDRAM

1

10

100

1000

1980 1985 1990 1995 2000

Processor-MemoryPerformance Gap:(grows 50% / year)

Performance

Time

“Moore’s Law”

[Patterson]


What’s the design problem?

Given an incredible complex system, finish the design

� Yesterday� with Zero power� with Zero cost� with QoS guarantees

� At sufficient performance !


Solution ?1. Platforms

� HW and SW IP reuse� Standardization (interfaces)� Scalability and Flexibility

2. Advanced Design Flow for Platforms� Raise abstraction level� Tool support� Modeling of Power, Cost, Performance

3. Predictability� QoS (quality of service) hooks� Reason about design properties at all levels


Platform characteristics� Programmable

� One or more processor cores� Reconfigurable� Scalable and flexible� Memory hierarchy

� Exploit locality� Separate local and global wiring� HW and SW IP reuse

� Standardization (on SW and HW-interfaces)� Raising design abstraction level

� Reliable� Cheaper


Platform and platform design

Realization

Applications

System design

Platform design

RaiseabstractionlevelPlatform

Design once, reuse many times


Example Platforms: Bus-based: Philips Nexperia

Philips Nexperia


Reconfigurable logic based:Xilinx Virtex II-Pro

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� ��

Up to 16 serial transceivers

� ��

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PowerPC

Reconfigurable logicblocks

Memory blocks

GHz IO: Up to 16 serial transceivers


IP NetworkInterface

R

R

R

R

R

R

R

R

R

NetworkInterface

IP

NetworkInterface

IP

RouterNetwork

Built-in network guarantees

NoC based: Philips AETHEREAL


Future platformsit's not only about HW !

Example: Smart Networked Devices

radio programmablehardware

reconfig.hardware

OS&

RMlibrary

Virtual MachineProtocols

Multimedia (MPEG 21)

Networkacceleratorhardware


On-chipNetwork

Networkinterface

NoC realization

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�$�%&'��' �"�( !"#��

�)#*�� "�+ !"#��

��,$

�-�,$

�.�&,/��0

Future platforms:realization


synthesis

idea

user requirements

non-executable specification

executable specification

HW-SW partitioning

compilation

platform

hardware software

transformation and refinement steps

algorithm design

architecture design

requirement capturing

(System specification)

(System implementation)

(System behavior)

(System architecture)

(System realization)

(System idea)

System Design trajectory

(reference code)


Sequential C/C++ description

control parts streaming parts

KPN

BDF / SDF

System design trajectory: specifics

modeling

Informal description

NoC Platform

POOSL / RPN


System level: events and streaming

• hardware + software • RT guarantees (throughput), DSP• parallelism in space• added value, differentiating factor• build on DSP/application knowledge

• Processing of events• Controlling host-CPU (GP Risc e.g. ARM)• standard OS• ‘classical’ SW complexity• general purpose approach

status

Event_in Event_out

stream_in stream_out

mode


Predictability: What is needed ?

Deal with dynamism� Changing application set� Changing application behavior:

� Scenario switches

� Less dramatic load changes� e.g. changing number of objects / scene


PredictabilityArchitecture level aspects� Deterministic control of all shared resources

should be possible� caches

� software control

� shared memories� network

� guaranteed throughput


PredictabilityDesign flow aspects� Design time

� Determine of upper bounds on time and resources�pareto curves

� Scenario discovery: � separate your application in parts for which upper

bounds not too far from worst case

Freq

Load

Sc1

Sc2

Sc3


Predictability: Compositionality

High leveldesign

Low leveldesign

x

y

z

ab

x

y

z

ab

P(x,y) if [P(a,b),...] !

P(x,y) if [P(a,b),...] ?


Mapping multiple jobs T1 T2T0

Multiple jobs can be active simultaneously.

When can a second job start ?

Are the requested resources available ?If not, can the quality level be lowered ?

If not, can other jobs go for a lower quality ?

If yes, independent from other jobs ?

resources

time

100%

reconfiguration

How to give guarantees?


Predictability: ComposabilityCan we add Pareto points?

Q

Cost (resources)

Q

Cost (resources)

+

application 1 application 2

(q1,c1) (q2,c2)

(q1+q2,c1+c2) ?


Local manager

Application n

Predictability� Run time aspects

� Scalable applications � QoS management

Local manager

Global manager

Application n / Scenario m

Platform

QoS protocol


4 levels� Level 3: System

� Multiple applications running simultaneously

� Level 2: Application� started/stopped by user� e.g. DVD player

� Level 1: Job� e.g. SDF graph for the sound-part of a DVD player

� Level 0: Task � e.g. SDF actor


PreMaDoNA proposes a solution based on the removal and/or software control of unpredictable elements in the architectures in

combination with a predictable mapping methodology that supportsreasoning about throughput.

An FPGA demonstrator will prove that1. That our predictable design methodology saves a lot of design

iterations.2. That NoCs can be used as an adequate target for real-time video

applications.3. That dynamically application demands can be matched with the

available NoC resources. Video quality should gracefully reduce when resources are limited.


Relations between WPs

QOS management: WP3

NoC architecture: WP1

NoC implementation: WP2

Application: WP6

Resource management: WP3

NoC realisation: WP2

Mapping: WP5Simulation: WP4

Application(Platformindependent)

Platform(Applicationindependent)

Compute jobs

Resourcebudgets


Application characteristics� Task level: well-known compute intensive

kernels� Job level: data dependent dynamic

applications (jobs)� Application level: multiple jobs

� System level: mutiple applications� Streaming dominates the cost

VideoIn1

NR HSRC VSRC

mem


Application package� Case studies

� Video Scaler (Bart Barenbrug; Philips Research)� FM radio (Caracas architecture; Philips

Semiconductor)� Arbitrary Shape (Object) Texture decoder


Links to related projects� Internal:

� Epicurus: Demons, FAME, Promes, Betsy, ….

� External:� Philips Research: Aethereal and Hydra� Philips Semiconductor� Progress projects: SCALP, Artemisia, SmartCam,

IMEC MPSoC, M4, Matador, SLI� and many others….


PreMaDoNAPredictable Matching of Demands

on Networked Architectures

Being able to design NoC-based real-time systems in a predictable way, such that we

can guarantee non-functional requirements,

while being able to dynamically match quality versus available resources.

Solution based on the removal and/or software control of unpredictable elements in the architectures in combination with a

predictable mapping methodology that supports reasoning about non-functional properties


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Project Overview - Eindhoven University of Technology · Project Overview. 8-Dec-04 H. Corporaal -PreMaDoNA kickoff 2 Agenda 15.00 Opening and Overview Henk Corporaal Bart Mesman