1

CHAPTER -1

INTRODUCTION:

1.1. Overview

The algorithm of Flexible Bus System is devised in a way that this system replaces

the scheduled bus lines systems and buses and dynamically changes their routes according to

passenger‟s demands. Passengers are informed about the real time location of the buses

which makes it easy for the passengers to decide whether to ride a particular bus or not

making this system passenger friendly.

The main objective of this project is to do a research on the use of short range

wireless technology called “Zigbee” in Demand Responsive Transit (DRT), making it much

more efficient, reliable and less expensive. This research is not the only way to develop this

kind of a system and by no means suggested the best solution but it can definitely be one of

the better alternatives we have till date and can be used in the areas where there are no 3G,

WiMax or other long range wireless technologies available. This research will also help us

understand the potential of Zigbee. Till now Zigbee is being used as in-house or in-vehicle

technology but this research brings an idea of using Zigbee as communication tool for Inter-

Vehicle and Vehicle to Infrastructure. Using Zigbee to communicate between Bus and the

Bus Stop will also reduce the total cost of the system as Zigbee devices are far cheaper than

WiFi, 3G and WiMax devices. Due to the fact that Zigbee is low power as compared to other

short range wireless technologies like WiFi, this system can be deployed in mountainous

areas where power is a major concern.

1.2 Existing Algorithm:

The algorithm of Flexible Bus System is devised in a way that this system replaces

the scheduled bus lines systems and buses can dynamically change their routes according to

passenger‟s demands. Passengers are informed about the real time location of the buses

which makes it easy for the passengers to decide whether to ride a particular bus or not

making this system passenger friendly.

Everything in the System is connected to the Control Centre and all the information

is shared with the Control Centre. Communication between Bus and Control Centre is

through 3G; similarly communication between Control Centre and Bus Stop is through 3G.

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Installing the 3G modules on Bus Stop and Bus which are more than 1 in most of the cases

will greatly increase the total installation cost of the system.

Fig 1.1 Existing FBS System

Following are some drawbacks to this approach.

1. Installation cost is very high.

2. Maintenance cost is very high.

3. High power consumption.

4. Cannot be applied in areas where there are no long range wireless signals available

(Rural or mountainous areas).

To overcome these problems we propose a model which is less costly than the system

discussed above. We call our proposed system “The Flexible Bus System”. This paper will

only include the wireless communication part of this system.

1.3 Proposed Algorithm:

The algorithm for this system is devised in such a way that passengers have to wait less on

the bus stops and buses drive to the bus stops where passengers are waiting instead of

driving to the Bus Stops where there are no passengers. Fig. 3 shows the algorithm flow for

The Flexible Bus Systems. Passenger after reaching the Bus Stop punches the RFID Card and

all the information (Passenger ID, Destination etc) is transferred to Control Centre which then

sends the info on which Bus to ride. Similarly info for all the Buses are transferred to

Control Centre through Bus Stops and then Route info for the Buses are transferred to Buses

through the Bus Stops. Navigation is installed in the bus which guides the Buses about the

routes. For example if BusA is on Bus Stop2 and a passenger is waiting on Bus Stop9, then

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instead of going to the Bus Stop9 by driving to all the Bus Stops from 2~9, the Bus will

directly drive to Bus Stop9 to pick up the passenger. This way the wait time of the passenger

waiting on Bus Stop9 will be less as compared to the case in which Bus has to drive from

2~9. The Flexible Bus System will not only decrease the wait time of the passengers but it

will also decrease the drive time of the Buses which will greatly reduce the total cost of the

System.

1.4 Block Diagram:

Fig 1.2 Block Diagram of Proposed Algorithm

1.5 System Architecture:

The Flexible Bus System consists of One Central station, Bus and Bus stops.

1.5.1 Central Station:

The Central station is equipped with one ARM7TDMI based LPC2148

microcontroller, and is interfaced with Zigbee wireless module. In this system all the Bus,

Central

Station

(LPC2418)

Bus Stop

(LPC2418)

Bus

(LPC2418) GPS

RFID Reader

Zigbee

Zigbee

Zigbee

RFID

Reader

RFID TAG

(Passenger before riding the bus)

RFID TAG

(Riding getting off)

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Bus stops and central station uses Zigbee as a communication medium. The complete

information of all the passengers account details, Buses and Bus stops is stored in the

External memory (EEPROM) interfaced to the station using I2C protocol. For example if a

passenger wants to reserve a ticket from any bus/bus stop he will provided an RFID tag with

some balance, the passenger has to punch his tag near to the RFID reader placed at Bus/Bus

stop ,and he has to give his complete details about is travel . Then the controller placed in that

bus stop sends the details of the passenger to the central station using Zigbe. The central

station receives the data through Zigbee and stores in one memory for processing. It will

compare the data received from bus or bus stop and the passenger Id, it will check the

complete details of the travel like source, destination and number of persons travelling. The

central station after comparing all the details according to the Bus root ,source and

destination the equivalent amount for the travel are debited from his account. And after

successful reservation of tickets the details of the reservation are sent to corresponding station

by Zigbee. If there are any errors like tag detection, not enough balance then the central

station will send the appropriate command data to corresponding station.

In this central station we are providing choice to admin ,they can modify the data and update

the balance of users whenever they needed.

1.6 Bus Stop / Bus

In this FBS system the bus stop and bus are interfaced with RFID, Zigbee and Hex

keypad. Each passenger who wants to utilize this FBS system, has to take one RFID tag from

central station or any Bus stations with some pre deposited amount.

When any passenger wants to reserve tickets he has to keep his RFID tag near to

RFID reader placed at either Bus or Bus Stop. if tag ID is matched then he will ask for

selecting the Bus root he would like to travel using Hex keypad. If the selected root is not

available then it will ask for select valid root again. The next it will ask for selecting the

source and then destination, number of persons. Each time the reservation is valid only for 6

members if the bus is remaining with less than 6 seats then it will allow persons equal to bus

capacity.

After all the reservation process it will send the complete data to central station

through Zigbee. The central station completes the process and sends the appropriate data to

bus and bus stop. If bus receives data from central station about ticket reservation at bus stop

then it will check if that information is about successful reservation of tickets, it will check

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the remaining seats after reservation and how many tickets reserved to this and displays them

on LCD and sends the request signal to send GPS coordinates. In the bus a PIC18F452

microcontroller which is interfaced with GPS system is placed. And this PIC controller is

inter connected to the LPC2148 . Whenever the Bus system wants to send the bus location to

other stations then it will send the request signal to PIC there the required location

information is sent through Zigbee to all the necessary stations.

If Bus stop receives the data from central station about ticket confirmation at the bus

stop then it will check whether that data belongs to that bus stop or not. It ignores if the data

doesn‟t belongs to it otherwise first it will check for is there any error in the confirmation

process if so it will check for what type of error and finds it then displays the error message

on LCD.

In the received data if there is no error information then it will check for remaining

balance of the passenger in their account and remaining seats in that bus to which the

passenger has reserved.

In this same process the information between bus , bus stop and central station is

processing through Zigbee. If any passenger reserves tickets for a bus that particular bus will

send the location of it to that bus stop and we can also send the time to reach that stop if

needed. Suppose if one bus is going , and there is no one passenger in next stop for this bus

the stop will send that information to that bus and bus will not stop at that stop.

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CHAPTER -2

EMBEDDED SYSTEM HARDWARE

2.1 Introduction to Microcontroller:

A microprocessor system consists of a microprocessor with memory, input ports and

output ports connected to it externally. A microcontroller is a single chip containing a

microprocessor, memory, input ports and output ports. Since all four blocks reside on the one

chip, a microcontroller is much faster than a microprocessor system.

We have several other basic microcontroller families such as PIC, M68HCXX, and AVR etc.

All these basic microcontrollers are useful for implementing basic interfacing and control

mechanisms for simple applications. There are several applications which require lot of

computation and high speed data processing. In such applications advanced microcontrollers

and microprocessors are used. One such advanced architecture is ARM.

2.2 History of ARM:

ARM stands for Advanced RISC machine. The first processor in ARM family was

developed at Acorn Computers Ltd between October 1983 and April 1985. Acorn Computers

was a British computer company established in Cambridge, England, in 1978. The company

worked for Reduced Instruction Set Computer (RISC) processor design. The company

produced a variety of computers which were very popular in the United Kingdom. These

included the Acorn Electron, the BBC Micro and the Acorn Archimedes. Particularly BBC

Micro computer dominated the UK educational computer market during the 1980s and early

1990s.

2.3 ARM Architecture:

The ARM core uses RISC architecture. Its design philosophy is aimed at delivering

simple but powerful instructions that execute within a single cycle at a high clock speed. The

RISC philosophy concentrates on reducing the complexity of instructions performed by the

hardware because it is easier to provide greater flexibility and intelligence in software rather

than hardware. As, a result RISC design plays greater demands on the compiler. In contrast,

the traditional complex instruction set computer (CISC) relies more on the hardware for

instruction functionality, AND consequently the CISC instructions are more complicated.

Certain design features have been characteristic of most RISC processors:

One cycle execution time: RISC processors have a CPI (clock per instruction) of one cycle.

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This is due to the optimization of each instruction on the CPU. Each instruction is of a fixed

length to allow the pipeline to fetch future instructions before decoding the current

instruction.

Pipelining: The processing of instructions is broken down into smaller units that can be

executed in parallel by pipelines. Ideally the pipeline advances by one step on each cycle for

maximum throughput. Instructions can be decoded in one pipeline stage.

Large number of registers: The RISC design philosophy generally incorporates a larger

number of registers to prevent large amount of interactions with memory. Any register can

contain either data or an address. Registers act as the fast local memory store for all data

processing operation.

Load-store architecture: The processor operates on data held in registers. Separate load and

store instructions transfer data between the register bank and external memory.

These design rules allow a RISC processor to be simpler, and thus the core can operate at

higher clock frequencies.

Table 2.3.1: Difference between RISC and CISC architectures:

2.4 ARM Processor Core:

Similar to most RISC machines ARM works on load-store architecture, so only load

and store instructions perform memory operations and all other arithmetic and logical

operations are only performed on processor registers. The figure shows the ARM core data

1. Complex instructions taking multiple cycles Simple instructions taking one cycle

2. Any instruction may refer to memory Only LOAD/STORE refer to memory

3. Not pipelined or less pipelined Highly pipelined

4. Instructions interpreted by the micro-program Instructions executed by the hardware

5. Variable format Fixed format instructions

6. Many instructions and modes Few instructions and modes

7. Complexity in the micro-program Complexity in the compiler

8. Single register set Multiple register sets

CISC RISC

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flow model. In which the ARM core as functional units connected by data buses,. And the

arrows represent the flow of data, the lines represent the buses, and boxes represent either an

operation unit or a storage area. The figure shows not only the flow of data but also the

abstract components that make up an ARM core.

Figure 2.4.1: ARM core dataflow model

In the above figure the Data enters the processor core through the Data bus. The data may be

an instruction to execute or a data item. This ARM core represents the Von Neumann

implementation of the ARM data items and instructions share the same bus. In contrast,

Harvard implementations of the ARM use two different buses.

The instruction decoder translates instructions before they are executed. Each instruction

executed belongs to a particular instruction set.

The ARM processors, like all RISC processors, use load-store architecture. This means it has

two instruction types for transferring data in and out of the processor: load instructions copy

data from memory to registers in the core, and conversely the store instructions copy data

from registers to memory. There are no data processing instructions that directly manipulate

data in memory. Thus, data processing is carried out solely in registers.

Data items are placed in the register file – a storage bank made up of 32-bit registers. Since

the ARM core is a 32- bit processor, most instructions treat the registers as holding signed or

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unsigned 32-bit values. The sign extend hardware converts signed 8-bit and 16-bit numbers

to 32-bit values as they are read from memory and placed in a register.

The ALU (arithmetic logic unit) or MAC (multiply – accumulate unit) takes the register

values Rn and Rm from the A and B buses and computes a result. Data processing

instructions write the result in Rd directly to the register file. Load and store instructions use

the ALU to generate an address to be held in the address register and broadcast on the

Address bus.

One important feature of the ARM is that register Rm alternatively can be preprocessed in the

barrel shifter before it enters the ALU. Together the barrel shifter and ALU can calculate a

wide range of expressions and addresses.

After passing through the functional units, the result in Rd is written back to the register file

using the Result bus. For load and store instructions the incrementer updates the address

register before the core reads or writes the next register value from or to the next sequential

memory location. The processor continues executing instructions until an exception or

interrupt changes the normal execution flow.

2.4.1 ARM Bus Technology:

Embedded systems use different bus technologies. The Peripheral Component

Interconnect (PCI) bus connects devices such as video card and disk controllers to the X 86

processor buses. This is called External or off chip bus technology.

Embedded devices use an on-chip bus that is internal to the chip and allows different

peripheral devices to be inter-connected with an ARM core.

There are two different types of devices connected to the bus

1. Bus Master

2. Bus Slave

Bus Master: A logical device capable of initiating a data transfer with another device across

the same bus (ARM processor core is a bus Master).

Bus Slave: A logical device capable only of responding to a transfer request from a bus

master device (Peripherals are bus slaves)

Generally a Bus has two architecture levels

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Physical lever: Which covers electrical characteristics a bus width (16, 32, 64 bus).

Protocol level: which deals with protocol?

NOTE: - ARM is primarily a design company. It seldom implements the electrical

characteristics of the bus, but it routinely specifies the bus protocol

2.4.2 AMBA (Advanced Microcontroller Bus Architecture) Bus protocol:

AMBA Bus was introduced in 1996 and has been widely adopted as the On Chip bus

architecture used for ARM processors.

The first AMBA buses were

1. ARM System Bus ( ASB )

2. ARM Peripheral Bus ( APB )

Later ARM introduced another bus design called the ARM High performance Bus (AHB).

Using AMBA

i. Peripheral designers can reuse the same design on multiple projects

ii. A Peripheral can simply be bolted on the On Chip bus without having to redesign an

interface for different processor architecture.

This plug-and-play interface for hardware developers improves availability and time to

market.

AHB provides higher data throughput than ASB because it is based on centralized

multiplexed bus scheme rather than the ASB bidirectional bus design. This change allows the

AHB bus to run at widths of 64 bits and 128 bits

ARM introduced two variations on the AHB bus

1. Multi-layer AHB

2. AHB-Lite

In contrast to the original AHB , which allows a single bus master to be active on the bus at

any time , the Multi-layer AHB bus allows multiple active bus masters.

AHB-Lite is a subset of the AHB bus and it is limited to a single bus master. This bus was

developed for designs that do not require the full features of the standard AHB bus.

AHB and Multiple-layer AHB support the same protocol for master and slave but have

different interconnects. The new interconnects in Multi-layer AHB are good for systems with

11

multiple processors. They permit operations to occur in parallel and allow for higher

throughput rates.

2.4.3 ARCHITECTURE Revisions:

Every ARM processor implementation executes a specific instruction set architecture

(ISA), although an ISA revision may have more than one processor implementation .The ISA

has evolved to keep up with the demands of the embedded market. This evolution has been

carefully managed by ARM, so that code written to execute on an earlier architecture revision

will also execute on a later revision of the architecture. The nomenclature identifies

individual processors and provides basic information about the feature set.

2.4.4 NOMENCLATURE:

ARM uses the nomenclature shown below is to describe the processor

implementations. The letters and numbers after the word “ARM” indicate the features a

processor may have.

ARM { x }{ y }{ z }{ T }{ D }{ M }{ I }{ E }{J }{ F }{ -S }

x → family

y → memory management / protection unit

z → cache

T → Thumb 16 bit decoder

D → JTAG debug

M → fast multiplier

I → Embedded ICE macro cell

E → enhanced instruction (assumes TDMI)

J → Jazelle

F → vector floating-point unit

S → synthesizable version

All ARM cores after the ARM7TDMI include the TDMI features even though they may

not include those letters after the “ ARM ” label

The processor family is a group of processor implementations that share the same

hardware characteristics. For example, the ARM7TDMI, ARM740T, and ARM720T all

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share the same family characteristics and belong to the ARM7 family

JTAG is described by IEEE 1149.1 standard Test Access Port and boundary scan

architecture. It is a serial protocol used by ARM to send and receive debug information

between the processor core and test equipment

Embedded ICE macro cell is the debug hardware built into the processor that allows

breakpoints and watch points to be set

Synthesizable means that the processor core is supplied as source code that can be

compiled into a form easily used by EDA tools.

2.4.5 Introduction to ARM7TDMI core:

The ARM7TDMI core is a 32-bit embedded RISC processor delivered as a hard

macro cell optimized to provide the best combination of performance, power and area

characteristics.

2.4.6 ARM7TDMI Features:

32/16-bit RISC architecture (ARM v4T)

32-bit ARM instruction set for maximum performance and flexibility

16-bit Thumb instruction set for increased code density

Unified bus interface, 32-bit data bus carries both instructions and data

Three-stage pipeline

32-bit ALU

Very small die size and low power consumption

Fully static operation

Coprocessor interface

Extensive debug facilities (Embedded ICE debug unit accessible via JTAG interface unit)

2.4.7 Benefits:

Generic layout can be ported to specific process technologies

Unified memory bus simplifies SoC integration process

ARM and Thumb instructions sets can be mixed with minimal overhead to support

application requirements for speed and code density

Code written for ARM7TDMI-S is binary-compatible with other members of the ARM7

Family and forwards compatible with ARM9, ARM9E and ARM10 families, thus it's

13

quite easy to port your design to higher level microcontroller or microprocessor

Static design and lower power consumption are essential for battery -powered devices

Instruction set can be extended for specific requirements using coprocessors

Embedded ICE-RT and optional ETM units enable extensive, real-time debug facilities

2.5 ARM Register file & modes of operation:

The ARM architecture has register file with 37 registers. In addition to these registers

there will be several other registers inside the processor which will not be visible to the

programmer but used by the processor internally to execute instructions. The current program

status register (CPSR) has condition flags and several other control bits. When the ARM

enters in privileged modes it has access to some special registers as explained below.

However these are arranged into several banks, with the accessible bank being governed by

the processor mode. Each mode can access a particular set of r0-r12 registers, a particular r13

(the stack pointer) and r14 (link register)‏, r15 (the program counter)‏, cpsr (the current

program status register)‏and privileged modes can also access a particular spsr (saved program

status register)‏.In user mode 16 data registers and 2 status registers are visible. Depending

upon context, register r13 and r14 can also be used as General Purpose Registers. In ARM

state the registers r0 to r13 are Orthogonal that means - any instruction which use r0 can as

well be used with any other General Purpose Register (r1-r13)‏‏.

The ARM processor has three registers assigned to a particular task or special function: r13,

r14 and r15. They are frequently given different labels to differentiate them from the other

registers.

Register r13 is traditionally used as the stack pointer (sp) and stores the head of the stack

in the current processor mode

Register r14 is called the link register (lr) and is where the core puts the return address

whenever it calls a subroutine.

Register r15 is the program counter ( pc ) and contains the address of the next instruction

to be fetched by the processor

2.5.1 ARM Modes of Operation:

ARM has total seven modes of operation. They are user , abort, fast interrupt, request,

interrupt request, supervisor, system and undefined. Out of all these modes the user mode is

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non-privileged mode which does not have write permissions to CPSR. The other six modes

are privileged modes.

Privileged: - Full read-write access to the CPSR. Under this we are having Abort, Fast

interrupt request, Interrupt request, Supervisor, System and Undefined.

Abort (10111): When there is a failed attempt to access memory

Fast interrupt Request (FIQ (10001)) & interrupt request (10010) : Correspond to interrupt

levels available on ARM

Supervisor mode (10011): State after reset and generally the mode in which OS kernel

executes

System mode (11111): Special version of user mode that allows full read-write access of

CPSR.

Undefined (11011): When processor encounters an undefined instruction

Non-privileged:- Only read access to the control filed of CPSR but read-write access to the

condition flags.

User (10000): User mode is user for programs and applications. And this is the normal mode

The above figure shows all 37 registers of register file. Out of these 37 registers, 20 registers

are hidden from a program in different modes. These are called banked registers.

2.6 ARM Instruction Set:

Different ARM architectures revisions support different instructions. However

new revisions usually add instructions and remain backwardly compatible. The following

15

shows the type of instructions that ARM support.

Data Processing Instructions

Branch Instructions

Load-store Instructions

Software Interrupt Instruction

Program Status Register Instructions

16

CHAPTER – 3

LPC2148 MICROCONTROLLER

3.1ARM7controller

Fig 3.1 Block Diagram of LPC2148 Microcontroller

The LPC2148 microcontrollers are based on a 32 bit ARM7TDMI-S CPU with real-

time emulation and embedded trace support, that combines the microcontroller with

embedded high speed flash memory of 512 kB. A 128-bit wide memory interface and a

17

unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For

critical code size applications, the alternative 16-bit Thumb mode reduces the code by more

than 30 % with minimal performance penalty.

Due to their tiny size and low power consumption, LPC2148 microcontrollers

are ideal for the applications where miniaturization is a key requirement, such as access

control and point-of-sale. A blend of serial communications interfaces ranging from a USB

2.0 Full Speed device, multiple UARTS, SPI, SSP to I2Cs and on-chip SRAM of 8 kB up to

40 kB, make these devices very well suited for communication gateways and protocol

converters, soft modems, voice recognition and low end imaging, providing both large buffer

size and high processing power. Various 32-bit timers, single or dual 10-bit ADC(s), 10-bit

DAC, PWM channels and 45 fast GPIO lines with up to nine edge or level sensitive external

interrupt pins make these microcontrollers particularly suitable for industrial control and

medical systems.

3.2 Features of LPC2148 Microcontroller:-

16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.

8 to 40 kB of on-chip static RAM and 32 to 512 kB of on-chip flash program

memory.

128 bit wide interface/accelerator enables high speed 60 MHz operation.

In-System/In-Application Programming (ISP/IAP) via on-chip boot-loader software.

Single flash sector or full chip erase in 400 ms and programming of 256 bytes in 1 ms.

EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with the

on-chip RealMonitor software and high speed tracing of instruction execution.

USB 2.0 Full Speed compliant Device Controller with 2 kB of endpoint RAM.

In addition, the LPC2146/8 provides 8 kB of on-chip RAM accessible to USB by

DMA.

One or two (LPC2141/2 vs. LPC2144/6/8) 10-bit A/D converters provide a total of

6/14 analog inputs, with conversion times as low as 2.44 μs per channel.

Single 10-bit D/A converter provide variable analog output.

Two 32-bit timers/external event counters (with four capture and four compare

Channels each), PWM unit (six outputs) and watchdog.

Low power real-time clock with independent power and dedicated 32 kHz clock

input.

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Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus

(400 kbit/s), SPI and SSP with buffering and variable data length capabilities.

Vectored interrupt controller with configurable priorities and vector addresses.

Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package.

Up to nine edge or level sensitive external interrupt pins available.

60 MHz maximum CPU clock available from programmable on-chip PLL with

settling time of 100 μs.

On-chip integrated oscillator operates with an external crystal in range from 1 MHz to

30 MHz and with an external oscillator up to 50 MHz.

Power saving modes include Idle and Power-down.

Individual enable/disable of peripheral functions as well as peripheral clock scaling

for additional power optimization.

Processor wake-up from Power-down mode via external interrupt, USB, Brown-Out

Detect (BOD) or Real-Time Clock (RTC).

– Single power supply chip with Power-On Reset (POR) and BOD circuits: CPU

operating voltage range of 3.0 V to 3.6 V (3.3 V ± 10 %) with 5 V tolerant I/O pads.

3.3 Description about the Block Diagram:-

3.3.1 On chip Flash Program Memory : -

LPC 2148 is having 512 kB Flash memory. This memory may be used for

both code and data storage. Programming of the flash memory may be accomplished in

several ways(ISP/IAP).

3.3.2 On chip Static RAM:-

On-chip static RAM may be used for code and/or data storage. The SRAM may be

accessed as 8-bit, 16-bit, and 32-bit. An 8 kB SRAM block intended to be utilized mainly by

the USB

3.3.3 Interrupt Controller:-

The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and

categorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and non-

vectored IRQ as defined by programmable settings.

3.3.4 Analog to Digital Converter :-

LPC2148 contains two analog to digital converters(ADC0 & ADC1 ). Total number of

available ADC inputs is 14. These two ADC‟s are 10 bit successive approximation analog to

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digital converters. Measurement range of 0 V to VREF. Global Start command for both

converters.

3.3.5 Digital to Analog Converter :-

The DAC enables to generate a variable analog output. The maximum DAC output

voltage is the VREF voltage. 10-bit DAC. Buffered output. Power-down mode available.

3.3.6 USB 2.0 Device Controller :-

The USB is a 4-wire serial bus that supports communication between a host and a

number (127 max) of peripherals. Enables 12 Mbit/s data exchange with a USB host

controller. A DMA controller (available only in LPC2146/48) can transfer data between an

endpoint buffer and the USB RAM.

3.3.7 UART :-

LPC2148 contains two UARTs( UART0 & UART1). In addition to standard transmit

and receive data lines, the LPC2148 UART1 also provides a full modem control handshake

interface. 16 byte Receive and Transmit FIFOs. It contains Built-in fractional baud rate

generator covering wide range of baud rates without a need for external crystals of particular

values.

3.3.8 I2C-bus serial I/O controller :-

I2C is a bidirectional. It is a multi-master bus, it can be controlled by more than one

bus master connected to it. It supports bit rates up to 400 kbit/s. Bidirectional data transfer

between masters and slaves. Serial clock synchronization allows devices with different bit

rates to communicate via one serial bus. Serial clock synchronization can be used as a

handshake mechanism to suspend and resume serial transfer.

3.3.9 SPI serial I/O control :-

It is s a full duplex serial interface, designed to handle multiple masters and slaves

connected to a given bus. Synchronous, Serial, Full Duplex Communication.

3.3.10 SSP serial I/O control :-

Supports full duplex transfers. Data frames of 4 bits to 16 bits of data flowing from

the master to the slave and from the slave to the master. Synchronous serial communication.

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Master or slave operation. 8-frame FIFOs for both transmit and receive. Four bits to 16 bits

per frame .

3.3.11 Timers :-

LPC 2148 has two 32-bit timer/counters with a programmable 32-bit prescaler. It also

having external External event counter. Four 32-bit capture channels per timer/counter that

can take a snapshot of the timer value when an input signal transitions. A capture event may

also optionally generate an interrupt.

It is also having Four 32-bit match registers that allow:

Continuous operation with optional interrupt generation on match.

Stop timer on match with optional interrupt generation.

Reset timer on match with optional interrupt generation.

Four external outputs per timer/counter corresponding to match registers, with the

following capabilities:

Set LOW on match.

Set HIGH on match.

Toggle on match.

Do nothing on match.

3.3.12 Watchdog Timer :-

The purpose of the watchdog is to reset the microcontroller within a reasonable

amount of time if it enters an erroneous state. When enabled, the watchdog will generate a

system reset if the user program fails to „feed‟ (or reload) the watchdog within a

predetermined amount of time.

3.3.13 Real Time Clock :-

The RTC is designed to provide a set of counters to measure time when normal or idle

operating mode is selected. The RTC has been designed to use little power, making it suitable

for battery powered systems where the CPU is not running continuously (Idle mode).

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3.3.14 Crystal Oscillator :-

On-chip integrated oscillator operates with external crystal in range of 1 MHz to 25

MHz. The oscillator output frequency is called fosc and the ARM processor clock frequency

is referred to as CCLK for purposes of rate equations, etc. fosc and CCLK are the same value

unless the PLL is running and connected.

3.3.15 PLL :-

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The

input frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current

Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice,

the multiplier value cannot be higher than 6 on this family of microcontrollers due to the

upper frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz,

so there is an additional divider in the loop to keep the CCO within its frequency range while

the PLL is providing the desired output frequency. The output divider may be set to divide by

2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is

insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed

following a chip reset and may be enabled by software. The program must configure and

activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The

PLL settling time is 100 μs

22

3.4 PIN Diagram of LPC2148

Fig 3.2 LPC2148 Pin Diagram

23

CHAPTER-4

PIC MICROCONTROLLER 18F452

4.1 Introduction

Microchip manufacture a series of microcontrollers called PIC (Peripheral interface

controller). There are many different flavours available, some basic low memory types, going

right up through to ones that have Analogue - To- Digital converters and even PWM built in.

There are several ways of programming the PIC - using BASIC, C, or Assembly Language.

A PIC microcontroller is a processor with built in memory and RAM and you can use it to

control your projects (or build projects around it). So it saves you building a circuit that has

separate external RAM, ROM and peripheral chips. Microchip is providing the 8-bit, 16-bit

and the 32 bit microcontrollers based on the desired application requirement the design

engineer can choose from those. Microchip is also providing the software for the

microcontrollers where the application programs are written MPLAB IDE, it is also

providing the in circuit debugger called MPLAB ICD3. The compilers for the 8bit, 16-bit and

the 32 bit are different.

4.2 PIN DIAGRAM

The main features of the pic 18f452 microcontroller are given below:

24

High-Performance Modified RISC CPU:

C compiler optimized instruction set architecture

Up to 10 MIPs operation:

DC - 40 MHz osc./clock input

4 MHz - 10 MHz osc./clock input with PLL active

16-bit wide instructions, 8-bit wide data path

Priority levels for interrupts

Peripheral Features:

High current sink/source 25 mA/25 mA

Three external interrupt pins

Timer0 module: 8-bit/16-bit timer/counter with

8-bit programmable prescaler

Timer1 module: 16-bit timer/counter

Timer2 module: 8-bit timer/counter with 8-bit period register (time-base for PWM)

Timer3 module: 16-bit timer/counter

Secondary oscillator clock option - Timer1/Timer3

Master Synchronous Serial Port (MSSP) module, Two modes of operation

I2C™ Master and Slave mode

Addressable USART module Supports RS-485 and RS-232.

Parallel Slave Port (PSP) module.

25

Fig 4.2.1 Block diagram of the pic 18f452

26

CHAPTER – 5

EXTERNAL HARDWARE

5.1 Liquid Crystal Display

These components are “specialized” for being used with the microcontrollers, which

means that they cannot be activated by standard IC circuits. They are used for writing

different messages on a miniature LCD. Amodel described here is for its low price and great

possibilities most frequently used in practice. It is based on the HD44780 microcontroller

(Hitachi) and can display messages in two lines with 16 characters each . It displays all letters

of alphabet, greek letters, punctuation marks, mathematical symbols etc. In addition, it is

possible to display symbols that user makes up on its own. Automatic shifting message on

display (shift left and right), appearance of the pointer, backlight etc. Are considered as

useful characteristics.

LCD screen

LCD screen consists of two lines with 16 characters each. Each character consists of

5x8 or 5x11 dot matrix. This book covers 5x8 character display because it is commonly

used.Contrast on display depends on the power supply voltage and whether messages are

displayed in one or two lines. For that reason, variable voltage 0-Vdd is applied on pin

marked as Vee. Trimmer potentiometer is usually used for that purpose. Some versions of

displays have built in backlight (blue or green diodes). When used during operating, a resistor

for current limitation should be used (like with any LE diode).

27

If there are no characters on display or all of them are dimmed upon the display is on,

the first thing that should be done is to check the potentiometer for contrast regulation. Is it

properly adjusted? Same applies in case the operation mode is changed (writing in one or two

lines).

LCD Basic Commands

All data transferred to LCD through outputs D0-D7 will be interpreted as commands or as

data, which depends on logic state on pin RS:

RS = 1 - Bits D0 - D7 are addresses of characters that should be displayed. Built in processor

addresses built in “map of characters” and displays corresponding symbols. Displaying

position is determined by DDRAM address. This address is either previously defined or the

address of previously transferred character is automatically incremented.

RS = 0 - Bits D0 - D7 are commands which determine display mode. List of commands

which LCD “recognizes”are given in the table below:

What is Busy flag ?

Comparing to the microcontroller, LCD is an extremly slow component. Because of

that It was necessary to provide a signal which will indicate that display is ready to receive a

new data or a command following the previous one has been executed. That signal is called

28

busy flag and can be read from line D7. When the bit BF is cleared (BF=0), display is ready

to receive.

LCD Connection

Depending on how many lines are used for connection to the microcontroller, there

are 8-bit and 4-bit LCD modes. The appropriate mode is determined at the beginning of the

process in a phase called “initialization”. In the first case, the data are transferred through

outputs D0-D7 as it has been already explained. In case of 4-bit LED mode, for the sake of

saving valuable I/O pins of the microcontroller, there are only 4 higher bits (D4-D7) used for

communication, while other may be left unconnected. Consequently, each data is sent to LCD

in two steps: four higher bits are sent first (that normally would be sent through lines D4-D7),

four lowerbits are sent afterwards. With the help of initialization, LCD will correctly connect

and interprete each data received. Besides, with regards to the fact that data are rarely read

from LCD (data mainly are transferred from microcontroller to LCD) one more I/O pin may

be saved by simpleconnecting R/W pin to the Ground. Such saving has its price. Even though

message displaying will be normally performed, it will not be possible to read from busy flag

since it is not possible to read from display.

Luckily, solution is simple. It is sufficient to give LCD enough time to perform its task upon

sending every character or command. Since execution of the slowest command is

approximately 1.64mS, it will be quite enough to wait for approximately 2mS.

29

5.2 Zigbee Communication

ZigBee is an open technology developed by the ZigBee Alliance to overcome the

limitations of BLUETOOTH and Wi-Fi. ZigBee is an IEEE 802.15.4 standard for data

communications with business and consumer devices. It is designed around low-power

consumption allowing batteries to essentially last forever. BLUETOOTH as we know was

developed to replace wires and Wi-Fi to achieve higher data transfer rate, as such till now

nothing has been developed for sensor networking and control machines which require longer

battery life and continuous working without human intervention. ZigBee devices allow

batteries to last up to years using primary cells (low cost) without any chargers (low cost and

easy installation).

The ZigBee standard provides network, security, and application support services operating

on top of the IEEE 802.15.4 Medium Access Control (MAC) and Physical Layer (PHY)

wireless standard. It employs a suite of technologies to enable scalable, self-organizing, self-

healing networks that can manage various data traffic patterns. The network layer supports

various topologies such star, clustered tree topology and self healing mesh topology which is

essential in Smartdust Apart from easy installation and easy implementation.

ZigBee has a wide application area such as home networking, industrial networking,

Smartdust, many more, having different profiles specified for each field. The upcoming of

ZigBee will revolutionize the home networking and rest of the wireless world.

The ZigBee Alliance is not pushing a technology; rather it is providing a standardized base

set of solutions for sensor and control systems.

The physical layer was designed to accommodate the need for a low cost yet allowing for

high levels of integration. The use of direct sequence allows the analog circuitry to be very

simple and very tolerant towards inexpensive implementations.

The media access control (MAC) layer was designed to allow multiple topologies without

complexity. The power management operation doesn't require multiple modes of operation.

30

The MAC allows a reduced functionality device (RFD) that needn't have flash nor large

amounts of ROM or RAM. The MAC was designed to handle large numbers of devices

without requiring them to be "parked".

The network layer has been designed to allow the network to spatially grow without requiring

high power transmitters. The network layer also can handle large amounts of nodes with

relatively low latencies.

Low power consumption, simply implemented ,Users expect batteries to last many months to

years! Consider that a typical single family house has about 6 smoke/CO detectors. If the

batteries for each one only lasted six months, the home owner would be replacing batteries

every month!

In contrast to Bluetooth, which has many different modes and states depending upon your

latency and power requirements, ZigBee/IEEE 802.15.4 has two major states: active

(transmit/receive) or sleep. The application software needs to focus on the application, not on

which power mode is optimum for each aspect of operation.

Even mains powered equipment needs to be conscious of energy. ZigBee devices will be

more ecological than their predecessors saving megawatts at it full deployment. Consider a

future home that has 100 wireless control/sensor devices,

Low cost to the users means low device cost, low installation cost and low maintenance.

ZigBee devices allow batteries to last up to years using primary cells (low cost) without any

chargers (low cost and easy installation). ZigBee's simplicity allows for inherent

configuration and redundancy of network devices provides low maintenance.

High density of nodes per network , ZigBee's use of the IEEE 802.15.4 PHY and MAC

allows networks to handle any number of devices. This attribute is critical for massive

sensor arrays and control networks.

Simple protocol, global implementation, ZigBee's protocol code stack is estimated to be

about 1/4th of Bluetooth's or 802.11's. Simplicity is essential to cost, interoperability, and

maintenance. The IEEE 802.15.4 PHY adopted by ZigBee has been designed for the 868

MHz band in Europe, the 915 MHz band in N America, Australia, etc; and the 2.4 GHz band

is now recognized to be a global band accepted in almost all countries.

5.2.1 ZigBee/IEEE 802.15.4 - General Characteristics

Dual PHY (2.4GHz and 868/915 MHz)

31

Data rates of 250 kbps (@2.4 GHz), 40 kbps (@ 915 MHz), and 20 kbps (@868

MHz)

Optimized for low duty-cycle applications (<0.1%)

CSMA-CA channel access

Yields high throughput and low latency for low duty cycle devices like sensors and

controls

Low power (battery life multi-month to years)

Multiple topologies: star, peer-to-peer, mesh

Addressing space of up to:

18,450,000,000,000,000,000 devices (64 bit IEEE address)

65,535 networks

Optional guaranteed time slot for applications requiring low latency

Fully hand-shaked protocol for transfer reliability

Range: 50m typical (5-500m based on environment)

5.2.2 ZIGBEE ARCHITECTURE

The IEEE 802.15.4 standard and Zigbee wireless network technology are ideal for the

implementation of a wide range of low cost, low power and reliable control and monitoring

applications within the private home and industrial environment. The working model of the

IEEE 802.15.4 and Zigbee is illustrated in Figure 6.9.

Fig: 5.2.2 Zigbee Architecture

32

In the Zigbee architecture, the PHY layer and MAC layer are based on the IEEE

802.15.4 WPAN standard. Zigbee defines the NWK and APS layers. The software and

hardware vendor will provide the software stack with appropriate tools to allow an OEM to

create applications, which are added to the APL. The Physical (PHY) layer and Medium

Access Control (MAC) layer are based on the IEEE802.15.4 PAN standard. This includes the

actual radio hardware. Above the MAC and PHY are the Network (NWK) and application

layers defined by Zigbee.

The first two layers, the physical (PHY) and Medium Access Control (MAC) are

defined in the IEEE standard. The other layers that build on the PHY and MAC layers are

defined by the Zigbee alliance.

The PHY layer contains the RF transceiver and access to the other hardware and

control mechanisms. The function of the PHY is to activate and deactivate the radio

transceiver and other hardware specific services such as access to the channels.

The MAC layer is as described by the name a controlling device for radio

medium. It controls access to the physical radio channel and other services defined by the

PHY service. It is also responsible for a reliable transmission system through its services. The

services are about channel access and transmission techniques and validation of data packets.

The network (NWK) layer is responsible for the network controlling functions. It

controls the mechanism for joining and leaving a network and for creating a network for

those devices which have the capability to do so. The NWK layer applies also security to

what is going to be data packets. The NWK layer is responsible for discovery and storing

information about the neighbors in the network. Responsibility for routing between devices

and routing of packets to their destination goes to this layer.

The application layer (APL) consists of three different blocks which have different

functionalities and responsibilitiesThe APS layer provides an interface between the NWK

layer and the APL with its set of services.

The Zigbee device object (ZDO) is responsible for managing Zigbee devices in the

network. This could be discovering new device in the network and define its role in the

network it also determines the services the new device provides. Possible device types are

those defined in Zigbee standard and they are coordinators, routers and end devices. The

33

Application Frame (AF) contains application objects which can be manufacturer defined

application objects. An example of an application object is a power switch.

The security service provider (SSP) provides enhanced security options as encryption

with 128-bit key transport.

5.2.3TRANSCEIVER

Pin Diagram

Fig: 5.2.3 Pin diagram of X-Bee Transceiver

Zigbee modules feature a UART interface, which allows any microcontroller or

microprocessor to immediately use the services of the Zigbee protocol. All a Zigbee hardware

designer has to do in this ase is ensure that the host‟s serial port logic levels are compatible

with the XBee‟s 2.8- to 3.4-V logic levels. The logic level conversion can be performed using

either a standard RS-232 IC or logic level translators such as the 74LVTH125 when the host

is directly connected to the XBee UART. The below table gives the pin description of

transceiver.

Pin Name Directio

n

Description

1 Vcc - Power Supply

2 DOUT Output UART Data Out

3 DIN/CONFIG Input UART Data In

4 DO8 Output Digital Output 8

34

5 RESET Input Module Reset

6 PWM0/RSSI Output PWM Output 0/RX Signal Strength Indicator

7 PWM1 Output PWM Output 1

8 [reserved] - Do not connect

9 DDR/SLEEP_RQ/DI

8

Input Pin Sleep Control Line or Digital Input 8

10 GND - Ground

11 AD4/DIO4 Either Analog Input 4 or Digital I/O 4

12 CTS/DIO7 Either Clear-to-Send Flow Control or Digital I/O 7

13 ON/SLEEP Output Module Status Indicator

14 VREF Input Voltage Reference for A/D Inputs

15 Associate/AD5/DIO5 Either Associated Indicator, Analog Input 5 or

Digital I/O 5

16 RTS/AD6/DIO6 Either Request-to-Send Flow Control, Analog Input 6

or Digital I/O 6

17 AD3/DIO3 Either Analog Input 3 or Digital I/O 3

18 AD2/DIO2 Either Analog Input 2 or Digital I/O 2

19 AD1/DIO1 Either Analog Input 1 or Digital I/O 1

20 AD0/DIO0 Either Analog Input 0 or Digital I/O 0

Table: 5.1 Pin Description of X-Bee Transceiver

FEATURES:

Table: 5.2 Performance characteristics

Parameters Value

Indoor/Urban Range 30m

Outdoor RF (LOS) 100m

Transmit Power Output 1mW (0dBm)

RF Data Rate 250,000bps

Serial Interface Data Rate 1200-115200bps

Receiver Sensitivity -92dBm

Table: 5.3 Power Requirement characteristics

35

Parameters Value

Supply Voltage 2.8 - 3.4V

Transmit Current 45mA

Receive Current 50mA

Table: 5.4 General characteristics

Parameters Value

Operating Frequency ISM 2.4GHz

Dimensions 2.468 x 2.761

Operating Temperature -40o to 85

o C

Antenna Options Integrated Chip Antenna

Table: 5.5 Networking and Security characteristics

Parameters Value

Supported Network Topologies Point-to-point, Point-to-multipoint,

Peer-to-peer

Number of Channels 16 Direct Sequence Channels

Addressing Options PAN ID, Channel and Addresses

5.2.4 System Data Flow Diagram

Fig: 5.2.4 Data Flow Diagram

36

The X-Bee RF Modules interface to a host device through a logic-level asynchronous

Serial port. Through its serial port, the module can communicate with any logic and voltage

Compatible UART; or through a level translator to any serial device.

Data is presented to the X-Bee module through its DIN pin, and it must be in the

asynchronous serial format, which consists of a start bit, 8 data bits, and a stop bit. Because

the input data goes directly into the input of a UART within the X-Bee module, no bit

inversions are necessary within the asynchronous serial data stream. All of the required

timing and parity checking is automatically taken care of by the X-Bee‟s UART.

Just in case you are producing data faster than the X-Bee can process and transmit it,

both X-Bee modules incorporate a clear-to-send (CTS) function to throttle the data being

presented to the X-Bee module‟s DIN pin. You can eliminate the need for the CTS signal by

sending small data packets at slower data rates.

If the microcontroller wants to send data to transceiver, it will send RTS (Request to

Send) signal. If the transceiver is idle it sends CTS (Clear to Send) signal. The RTS and CTS

signals are active low. When microcontroller receives CTS command it will send data to the

transceiver through DIN pin. The transceiver will send the data to microcontroller through

DOUT pin. The communication between transceiver and the microcontroller at the

transmitter and receiver is similar. The communication between transmitter and receiver is

through RF communication.

5.2.5 Serial Data

Fig: 5.2.5 Serial Data Sequence

For example:

37

UART data packet 0x1F (decimal number is 31) as transmitted through the RF

module.

Data enters the module UART through the DI pin (pin 3) as an asynchronous serial

signal. The signal should idle high when no data is being transmitted. Each data byte consists

of a start bit (low), 8 data bits (least significant bit first) and a stop bit (high). The following

figure illustrates the serial bit pattern of data passing through the module.

The module UART performs tasks, such as timing and parity checking, that are

needed for data communications. Serial communications depend on the two UARTs to be

configured with compatible settings (baud rate, parity, start bits, stop bits, data bits).

X-Bee RF Modules operate in Transparent Mode. When operating in this mode, the

modules act as a serial line replacement - all UART data received through the DI pin is

queued up for RF transmission. When RF data is received, the data is sent out the DO pin.

5.3 EEPROM

EEPROM (also written E2PROM and pronounced "e-e-prom," "double-e prom," "e-

squared," or simply "e-prom") stands for Electrically Erasable Programmable Read-Only

Memory and is a type of non-volatile memory used in computers and other electronic devices

to store small amounts of data that must be saved when power is removed, e.g., calibration

tables or device configuration.

When larger amounts of static data are to be stored (such as in USB flash drives) a

specific type of EEPROM such as flash memory is more economical than traditional

EEPROM devices. EEPROMs are realized as arrays of floating-gate transistors. EEPROM is

user-modifiable read-only memory (ROM) that can be erased and reprogrammed (written to)

repeatedly through the application of higher than normal electrical voltage generated

externally or internally in the case of modern EEPROMs. EPROM usually must be removed

from the device for erasing and programming, whereas EEPROMs can be programmed and

38

erased in circuit. Originally, EEPROMs were limited to single byte operations which made

them slower, but modern EEPROMs allow multi-byte page operations. It also has a limited

life - that is, the number of times it could be reprogrammed was limited to tens or hundreds of

thousands of times. That limitation has been extended to a million write operations in modern

EEPROMs. In an EEPROM that is frequently reprogrammed while the computer is in use,

the life of the EEPROM can be an important design consideration. It is for this reason that

EEPROMs were used for configuration information, rather than random access memory.

5.4 Global Positioning System

The Global Positioning System (GPS) offers the capability to accurately determine

location anywhere on earth in addition to speed, altitude, heading, and a host of other critical

positioning data. GPS is widely used in military, consumer, and service markets with

applications ranging from container shipping to weapons systems and handheld devices.

The GPS system consists of 24 satellites orbiting in six planes around the earth. The

satellites transmit a microwave signal, which is read by the GPS receiver on earth. The GPS

receiver requires a successful lock onto at least four GPS satellites to gather an accurate

signal for calculating position and velocity. The module triangulates its position with relation

to three satellites, using a fourth satellite as a clock source.

The GPS system is designed such that at any point, a GPS module on earth has a clear

view of at least four satellites, barring any obstruction such as buildings, interiors of a

canyon, dense foliage, or mountains. This application note details important data

considerations and implementation methods to integrate a GPS receiver with a CY8C29466

device and enable data logging through an SD card. Finally, the GPS data is parsed and

displayed onto an LCD screen. This application note guides a PSoC® developer in

integrating GPS applications and providing portable code that can be bolted into a user‟s

application

Handheld receivers calculate

- latitude

- Longitude

- velocity

Developed by Department of Defense

Orbiting navigational satellites

39

- Transmit position and time data

5.4.2 The GPS Constellation

Components of the System:

User segment

GPS antennas & receiver/processors

Position

Velocity

Precise timing

Used by

- Aircraft

- Ground vehicles

- Ships and individuals

5.4.3 HOW DOES GPS WORK?

40

Satellite ranging

- Satellite locations

- Satellite to user distance

- Need four satellites to determine position

Distance measurement

- Radio signal traveling at speed of light

- Measure time from satellite to user

Low-tech simulation

Distance to a satellite is determined by measuring how long a radio signal takes

to reach us from that satellite.

To make the measurement we assume that both the satellite and our receiver are

generating the same pseudo-random codes at exactly the same time.

By comparing how late the satellite's pseudo-random code appears compared to

our receiver's code, we determine how long it took to reach us.

Multiply that travel time by the speed of light and you've got distance.

Accurate timing is the key to measuring distance to satellites.

Satellites are accurate because they have four atomic clocks ($100,000 each) on

board.

Receiver clocks don't have to be too accurate because an extra satellite range

measurement can remove errors.

To use the satellites as references for range measurements we need to know

exactly where they are.

GPS satellites are so high up their orbits are very predictable.

All GPS receivers have an almanac programmed into their computers that tells them

where in the sky each satellite is, moment by moment.

Minor variations in their orbits are measured by the Department of Defense.

The error information is sent to the satellites, to be transmitted along with the timing

signals.

5.4.4 GPS Position Determination

41

Features

The GPS smart receiver provides a host of features that make it easy for integration and use.

Ultra low power design.

High performance receiver tracks up to 16 satellites.

Compact design ideal for applications with minimal space.

A rechargeable battery sustains internal clock and memory. It is recharged during

normal operation.

User initialization is not required.

One full duplex serial communication and user selectable baud rates allow maximum

interface capability andflexibility.

Water proof (1 meter) design for all weather.

Built-in low noise, high gain active antenna.

5.5 Hex Keypad Explanation

The hex keypad is a peripheral that connects to the DE2 through JP1 or JP2 via a 40-

pin ribbon cable. It has 16 buttons in a 4 by 4 grid, labelled with the hexadecimal digits 0 to F.

An example of this can been seen in Figure 1, below. Internally, the structure of the hex

42

keypad is very simple. Wires run in vertical columns (we call the m C0 to C3) and in

horizontal rows (called R0 to R3).

These 8 wires are available externally, and will be connected to the lower 8 bit s of t

he port. Each key on the keypad is essentially a switch that connects a row wire to a column

wire. When a key is pressed, it makes an electrical connection between the row and column

Reading Values from the Hex Keypad

It is tempting to view the hex keypad as a peripheral which just tells us which key was

pressed, and all we have to do is read the value via the GPIO port. This is the wrong view to

take. The hex keypad is just a way for a user to interact with the DE2 board. As described in

the previous section, all the keypad does is make electrical connections between rows

and columns – it is up to your program to determine from that which key was

pressed. The hex keypad is connected to the DE2 Media Computer via the GPIO parallel

ports. We need to remember a few things about the GPIO ports in order to read and interpret

hex keypad input properly. Recall that each pin on JP1 or JP2 can be configured individually

as input or output. Furthermore, the port direction can be reconfigured by your program, so

that the inputs and outputs can be changed while your program is running. Finally, remember

that each pin in the HEX keypad is connected to a pull-up resistor, so any input coming from

the hex keypad will read a 1 by default (i.e. when a key is not being pressed).These facts,

coupled with our knowledge of how the row and column wires of the hex keypad are wired

up to the DE2 board, will allow us to determine which key has been pressed. If we treat all

the hex keypad wires as inputs, we will always read in a 0xFF, since there is nothing driving

those wires – they are unconnected. Even when a key is pressed, the effect is of connecting

one input port to another, so the pull-up resistors will always output a 1.

43

5.6 RFID

Short for radio frequency identification, RFID is a dedicated short range communication

(DSRC) technology. The term RFID is used to describe various technologies that use radio

waves to automatically identify people or objects. RFID technology is similar to the bar code

identification systems we see in retail stores everyday; however one big difference between

RFID and bar code technology is that RFID does not rely on the line-of-sight reading that bar

code scanning requires to work.

A basic RFID system consists of three components:

An antenna or coil

A transceiver (with decoder)

A transponder (RF tag) electronically programmed with unique information

The antenna emits radio signals to activate the tag and to read and write data to it.

The reader emits radio waves in ranges of anywhere from one inch to 100 feet or

more, depending upon its power output and the radio frequency used. When an RFID

tag passes through the electromagnetic zone, it detects the reader's activation signal.

The reader decodes the data encoded in the tag's integrated circuit (silicon chip) and

the data is passed to the host computer for processing.

The purpose of an RFID system is to enable data to be transmitted by a portable device,

called a tag, which is read by an RFID reader and processed according to the needs of a

particular application. The data transmitted by the tag may provide identification or location

information, or specifics about the product tagged, such as price, color, date of purchase, etc.

RFID technology has been used by thousands of companies for a decade or more. . RFID

44

quickly gained attention because of its ability to track moving objects. As the technology is

refined, more pervasive - and invasive - uses for RFID tags are in the works.

5.6.1 Asset Tracking

It's no surprise that asset tracking is one of the most common uses of RFID.

Companies can put RFID tags on assets that are lost or stolen often, that are underutilized or

that are just hard to locate at the time they are needed. Just about every type of RFID system

is used for asset management. NYK Logistics, a third-party logistics provider based in

Secaucus, N.J., needed to track containers at its Long Beach, Calif., distribution center. It

chose a real-time locating system that uses active RFID beacons to locate container to within

10 feet.

5.6.2 Applications

RFID has been used in manufacturing plants for more than a decade. It's used to track

parts and work in process and to reduce defects, increase throughput and manage the

production of different versions of the same product.

SupplyChainManagement

RFID technology has been used in closed loop supply chains or to automate parts of

the supply chain within a company's control for years. As standards emerge, companies are

increasingly turning to RFID to track shipments among supply chain partners.

Retailing

Retailers such as Best Buy, Metro, Target, Tesco and Wal-Mart are in the forefront of

RFID adoption. These retailers are currently focused on improving supply chain efficiency

and making sure product is on the shelf when customers want to buy it.

Payment Systems

RFID is all the rage in the supply chain world, but the technology is also catching on

as a convenient payment mechanism. One of the most popular uses of RFID today is to pay

for road tolls without stopping. These active systems have caught on in many countries, and

quick service restaurants are experimenting with using the same active RFID tags to pay for

meals at drive-through windows.

Security and Access Control

RFID has long been used as an electronic key to control who has access to office

buildings or areas within office buildings. The first access control systems used low-

45

frequency RFID tags. Recently, vendors have introduced 13.56 MHz systems that offer

longer read range. The advantage of RFID is it is convenient (an employee can hold up a

badge to unlock a door, rather than looking for a key or swiping a magnetic stripe card) and

because there is no contact between the card and reader, there is less wear and tear, and

therefore less maintenance.

As RFID technology evolves and becomes less expensive and more robust, it's likely that

companies and RFID vendors will develop many new applications to solve common and

unique business problems.

5.7 Buzzer

A buzzer or beeper is an audio signaling device, which may be mechanical,

electromechanical, or piezoelectric. Typical uses of buzzers and beepers include alarm

devices, timers and confirmation of user input such as a mouse click or keystroke.

Applications:

Microwave ovens and House hold appliances

Annunciate panels

Electronic metronomes

46

CHAPTER – 6

SOFTWARE DEVELOPMENT USING UVISION KEIL IDE

Step 1: Give a double click on uvision 4 icon on the desktop, it will generate a window as

shown below.

Step 2: To create new project go to project select new micro vision project .

Step 3: select a drive where you would like to create your project.

Step 4: Create a new folder and name it with your project name.

Step 5: Open that project folder and give a name of your project executable file and save it.

Step 6: After saving it will show some window there you select your microcontroller

company i.e NXP from Phillips.

Step 7: Select your chip as LPC2148

Step 8: After selecting chip click on OK then it will display some window asking to add

STARTUP file. Select YES .

Step 9: A target is created and startup filoe is added to your project target and is shown

below.

Step 10: To write your project code select a new file from FILE menu bar.

Step 11: It will display some text editor ,to save that file select SAVE option from FILE

menu bar.

Step 12: By giving a file name lwith extension .C for c files and save it.

Step 13: Write the code of your project and save it.

Step 14: To add our c file to target give a right click on Source Group ,choose “ADD files to

Group” option.

Step 15: It will display some window there select the file you have to add and click on ADD

option.

Step 16: The file will be added to our target and it shows in the project window.

Step 17: Now give a right click on target in the project window and select “Options for

Target”.

Step 18: It will shoe some window, in that go to output option and choose Create Hex file

option by selecting that box.

Step 19: In the same window go to Linker option and choose Use Memory Layout from

Target Dialog by selecting the box,and click OK.

Step 20: Now to Compile your project go to Project select Build Target option or press F7.

47

Step 21: In the build OUT PUT window you can see the errors and warnings if there in your

code.And here your project Hex file will be created.

48

DUMPING THE HEX FILE TO MICROCONTROLLER USING FLASH

MAGIC

Step 1-Communications

Set COM Port :COM1

Baud Rate : 9600

Device : LPC2148

Interface :None(ISP)

Oscillator Freq(MHz) :12

Step 2-Erase

Select the box Erase all Flash + Code Rd Prot

Step 3-Hex File

Click on browse to load the serial.hex file from the folder serial_driver.

Step 4-Options

Select the box Verify after programming.

49

Power up the microcontroller board using USB cable, make serial cable connection

between PC and microcontroller‟s UART0 db9 connector.

To make the board enter programming mode

Hold down Boot switch (isp) and Reset, then release Reset first and finally Boot.

Step 5-Start

Click the Start button

Create a Project in MikroC for PIC18F452 development board

Step1: Click for MikroC Icon . Which appearing after Installing MikroC.

To start MikroC IDE click Start>Programs> Mikroelektronika>mikroC> mikroC. The initial

screen will appear followed by the main window.

If any project is opened close the project to create new project.

Click the Close Project icon or select Project > Close Project from the drop-down menu:

Click the New Project icon or select Project > New Project from the drop-down menu:

Set up your project

Project Wizard dialog will appear - fill the dialog with appropriate settings for your project:

Enter a name for your new project,

Choose project path,

Enter short text which describes your project (this is optional),

Choose the microcontroller from drop-down menu (P18F452),

Set the device clock by entering the value in edit box(10.000M.Hz),

Set configuration bits (Device Flags) by clicking Default, after you have set up your

project, click OK to continue.

Write the code:

50

Compiler will create the project file and an accompanying source file, named same as your

project. This source file will be automatically opened in the Code Editor, so we can write

the source code. This is the Code Editor:

Build:

Now it‟s time to build our project. First, save your file by clicking on the Save Icon, or click

Ctrl+S. Select Project > Build from the drop-down menu, or click the Build Icon. You can also

use the shortcut Ctrl+F9.

51

CHAPTER-7

RESULTS

Results at central stations:

Results at bus & bus stop:

When the passanger uses his RFID tag at any bus or bus stop, he has to enter details like source and

destination.

52

After details are entered it displays no of seats remaining & filled. To confirm the ticket one has to

press „C‟. This data is sent to central station.

53

CHAPTER 8

HARDWARE IMGAES

Fig 8.1 ARM 7 devolopment board with on board LPC2148 Micro-controller

Fig 8.2 Global Positioning system

54

Fig 8.3 ARM 7 devolopment board with on board LPC2148 Micro-controller interfaced with

RFID, hex key pad:

55

CONCLUSION

The Flexible Bus Systems is an efficient and a smart Demand Responsive Transit

(DRT). It is flexible in a sense that it can change dynamically according to the demand of the

passenger.

The system can fulfil the demands of the passengers in a way that they have to wait less on

the Bus Stops and even if they miss the Bus they can be entertained by the next bus without

Waiting for very long. The use of Zigbee for communication between the Buses and the Bus

Stops greatly reduce the total cost of the system. Everything is connected to the Control

Centre which is the brain of the system. Control Centre and Bus Stops are connected through

the internet and Buses and Control Centre are connected to each other through Bus Stops. All

the characters (Buses, Bus Stops and Passengers) are updated with latest information all the

times which makes The Flexible Bus Systems more information rich and reliable

56

REFERENCES

1 Shahin Farahani, Zigbee Wireless Networks and Transceivers

2 Lee, E., Ryu, K., Paik, I.: A Concept for Ubiquitous Transportation Systems and Related

development Methodology. In: International IEEE Conference on Intelligent

Transportation Systems, pp.37-42(2008)

3 Yuwei Li, Jessica Wang, Justin Chen, Michael Cassidy, Design of a Demand-

Responsive Transit System (California PATH Working Paper UCB-ITS-PWP-2007-4)

4 ZHANG Feizhou, CAO Xuejun, YANG Dongkai, Intelligent Scheduling of Public

Traffic Vehicles Based on a Hybrid Genetic Algorithm (TSINGHUA SCIENCE AND

TECHNOLOGY, ISSN 1007-0214 09/25 pp625-631, Volume 13, Number 5, October 2008)

5 Jin Xu, Zhe Huang, An Intelligent Model for Urban Demandresponsive Transport System

Control (Journal of Software, Vol. 4, No. September 2009)

6 R´emy Chevrier, Philippe Canalda, Pascal Chatonnay and Didier Josselin, Comparison

of three Algorithms for solving the Convergent Demand Responsive Transportation Problem

(Proceedings of the IEEE ITSC 2006)

7 Zigbee Standards Organization, Zigbee Specification, ZigBee Document 053474r17,

January 17, 2008.

8 Tomohiro Utsumi, Shin Konno, Yusuke Kanno, Ken-ichi Yukimatsu,Mahito

Kobayashi, Masashi Hashimoto, A Feasibility study on theBuffer-Less Routing Networks

using Deflection Routing Control(Proceedings of IEICE Vol. J92-B No. 11 pp. 1741-1749

2009).

57

APPENDIX

CODE FOR BUS STOP:

#include <LPC214X.H>

#include"header.h"

#include"string.h"

#define total_buses 4

#define bs1 0x31

#define BUZ_ON IO1CLR=(1<<31)

#define BUZ_OFF IO1SET=(1<<31)

volatile unsigned int no_persons=0,rem_seats=0;;

unsigned char busroot[4][250] = {

{"FROM : DSNR\tTO:JNTU \r\n sop no. stopname \r\n 1. DSNR \t2.Malakpet\r\n3.

chaderghat\t4.koti\r\n5. abids \t6.lakdikappol\r\n7. khairtabad\t8.panjagutta\r\n9. ameerpet \r\n"},

{"FROM : DSNR\tTO:JNTU \r\n sop no. stopname \r\n 1. DSNR \t2.Malakpet\r\n3.

chaderghat\t4.koti\r\n5. abids \t6.lakdikappol\r\n7. khairtabad\t8.panjagutta\r\n9. ameerpet \r\n"},

{"FROM : DSNR\tTO:JNTU \r\n sop no. stopname \r\n 1. DSNR \t2.Malakpet\r\n3.

chaderghat\t4.koti\r\n5. abids \t6.lakdikappol\r\n7. khairtabad\t8.panjagutta\r\n9. ameerpet \r\n"},

{"FROM : DSNR\tTO:JNTU \r\n sop no. stopname \r\n 1. DSNR \t2.Malakpet\r\n3.

chaderghat\t4.koti\r\n5. abids \t6.lakdikappol\r\n7. khairtabad\t8.panjagutta\r\n9. ameerpet

\r\n"}};

unsigned char rfid_data[11],central_data[20],rfid_flag=0;

const char tag[4][11] ={{"1D004526C2\0"},{"1D0043FE71\0"},

{"1C00FFF69F\0"},{"1E00C8CB74\0"}};

unsigned int

tag_id=0,tag_index=0,index=0,keypad_flag=0,k=0,central_flag=0,i=16,bus_number=0,len=0,src=0,ds

t=0,nop1=0;

unsigned char tx_data[11],*bus_no,*source,*destin,*nop,key[3],DEC[4],unit_data[7];

int main()

{

58

PINSEL0 = 0x00050005;

PINSEL1 = 0x00000000;

PINSEL2 = 0x00000000;

IO0DIR = (1<<22) | (1<<21) | (1<<20) | (1<<19) | (1<<18) | (1<<17) | (1<<16);

//keypad initialization

IODIR1 = 0xC00f0000; //P1.16-P1.19 (COLUMNS - outputs)

IOCLR1 = 0x000f0000; //making outputs(clms) low p1.16,17,18,19

IOCLR0 |= 0x0000f800; //making inputs(rows) low p0.12,13,11,15

IO1SET = (1<<31);

VPBDIV = 0x01;

uart1_init();

uart0_init();

LCD_Init();

Delay(20);

display_title1();

send_string0("\r\n Flexible BUS System ");

send_string0("\r\n BUS No.1");

tx_data[0] = 'S';

tx_data[1] = 'P';

tx_data[2] = '1';

flushtext();

unit_data[0] = 'U';

unit_data[1] = '1';

unit_data[2] = 'R';

while(1)

{

if(rfid_flag == 1)

{

rfid_flag = 0;

send_string0(rfid_data);

59

tag_id = findtag_index(rfid_data);

if(tag_id < 20)

{

send_string0("\r\n id is");

send_char0(tag_id+48);

tx_data[3] = (unsigned char)(tag_id+48);

send_string0("\r\n Enter Bus details like \r\n -->Root Number \r\n -->Source and Destination

\r\n -->Number of persons \r\n after entering press 'C' to exit");

k = 0;i=16;

keypad_flag = 0;

display_title2();

b: display1();

keypad_flag = 0;

k=0;i=16;

while(keypad_flag == 0)

bus_no = keypad_scan();

temp1 = data;

if(data == 0)

{

DEC[0]='0';

DEC[1]='\0';

}

while(data>0)

{

data = data/10;

i++;

}

i=i-1;

if(i==0)

60

{

DEC[1]=DEC[2]=DEC[3]='\0';;

}

if(i==2)

{

DEC[3]='\0';

}

if(i==1)

{

DEC[2]=DEC[3]='\0';

}

while(temp1>0)

{

temp = temp1%10;

temp1 = temp1/10;

DEC[i] = temp + 48;

i--;

}

}

void buzzer()

{

BUZ_ON;

Delay(30);

BUZ_OFF;

}

LCD_Command(0x01);

LCD_Command(0x80);

LCD_String("Keypad scanning");

LCD_Command(0xC0);

LCD_String("NOP :");

61

}

void display5()

{

LCD_Command(0x01);

LCD_Command(0x80);

LCD_String("Bus Root No. : 1");

LCD_Command(0xC0);

LCD_String("C:60 F:");

LCD_String(DEC);

}

void display6()

{

LCD_Command(0xCA);

LCD_String("A:");

LCD_Data(central_data[9]);

LCD_Data(central_data[10]);

}

void HexatoDeci(unsigned int data)

{

unsigned int temp,temp1,i;

i = 0;

62

CODE FOR CENTRAL STATION:

void enter_data_updation_admin(void)

{

unsigned char choice;

k: UART0_SendStr("\r\n ----- DATA BASE UPDATION_ADMIN ----- \r\n");

p: UART0_SendStr("\r\n choose 1: To update BALANCE \r\n choose 2: To update BUS

FARES \r\n choose 3: To diplay memory contents \r\n choose 4: To Clear memory \r\n choose 5: To

update seats \r\n choose 6: To Exit \r\n Enter choice (1/2/3/4/5/6): ");

UART0_GetByte();

choice=rdata-48;

UART0_SendByte(rdata);

clear_variables();

if(choice==0 || choice>=7)

{

UART0_SendStr("\r\n wrong choice ");

goto k;

63

}

else if(choice==6)

{

UART0_SendStr("\r\n EXITING DATA BASE UPDATION_ADMIN ");

return;

}

else if(choice==5)

{

UART0_SendStr("\r\n Seat updation ");

seat_updation();

goto p;

}

else if(choice==4)

{

UART0_SendStr("\r\n Enter Block to clear (0/1) ");

UART0_GetByte();

clear_memory(rdata-48);

UART0_SendStr("\r\n CLEARED THE DATA BASE BY ADMIN ");

}

else if(choice==3)

{

display_memory_contents(0);

display_memory_contents(1);

goto p;

}

else if(choice==1)

{

bn=0x00;

uen=0;

UART0_SendStr("\r\n RFID TAG ID(1Bytes): ");

64

for(j=0;j<1;j++)

{

UART0_GetByte();

rftc[j]=rdata;

UART0_SendByte(rftc[j]);

uen++;

}

UART0_SendStr("\r\n CHECKING DATA BASE for RFID TAG.... ");

for(i=1;i<=tdbp_blk0;i++)

{

i2c_read(BLK_0,((i*16)-1));

for(j=0;j<1;j++)

str[j]=I2C_RD_Buf[j];

f=strcmp(rftc,str);

if(f==0) //same as if(f)

{

UART0_SendStr("\r\n TAG ID FOUND ");

fat=i;

break;

}

}

if(fat==0)

{

UART0_SendStr("\r\n TAG ID NOT FOUND");

UART0_SendStr("\r\n Want to create a new entry (Y/N) :");

UART0_GetByte();

UART0_SendByte(rdata);

if(rdata=='Y' || rdata=='y')

{

fdbp_blk0=fdbp_blk0+1;

65

if(fdbp_blk0!=tdbp_blk0+1)

{

fdbp_blk1=fdbp_blk1+1;

if(fdbp_blk1!=tdbp_blk1+1)

{

UART0_SendStr("\r\n Creating new entry ...");

fat=fdbp_blk1;

}

else

{

UART0_SendStr("\r\n Memory full ...");

goto p;

}

}

else

goto p;

}

UART0_SendStr("\r\n ENTER FARE (3Bytes)(000-999): ");

for(j=0;j<3;j++)

{

UART0_GetByte();

fare[j]=rdata;

UART0_SendByte(fare[j]);

uen++;

if((rdata-48)<0 || (rdata-48)>9)

{

UART0_SendStr("\r\n Wrong entry ..ENTER

DIGITS ");

uen--;

j--;

66

}

}

UART0_SendStr("\r\n writing/reading to memory ------- ");

for(j=0;j<1;j++)

I2C_WR_Buf[j]=rn[j];

for(j=1;j<2;j++)

I2C_WR_Buf[j]=sc[j-1];

for(j=2;j<5;j++)

I2C_WR_Buf[j]=fare[j-2];

for(j=5;j<6;j++)

I2C_WR_Buf[j]='6';

for(j=6;j<7;j++)

I2C_WR_Buf[j]='0';

for(j=7;j<16;j++)

I2C_WR_Buf[j]='\0';

i2c_write(BLK_1,((fat*16)-1));

i2c_read(BLK_1,((fat*16)-1));

UART0_SendStr(&I2C_RD_Buf[0]);

}

goto p;

67

CODE FOR BUS:

#include <LPC214X.H>

#include"header.h"

#include"string.h"

#define total_buses 4

#define bs1 0x31

#define BUZ_ON IO1CLR=(1<<31)

#define BUZ_OFF IO1SET=(1<<31)

unsigned char busroot[4][250] = {

{"FROM : DSNR\tTO:JNTU \r\n sop no. stopname \r\n 1. DSNR \t2.Malakpet\r\n3.

chaderghat\t4.koti\r\n5. abids \t6.lakdikappol\r\n7. khairtabad\t8.panjagutta\r\n9. ameerpet \r\n"},

{"FROM : DSNR\tTO:JNTU \r\n sop no. stopname \r\n 1. DSNR \t2.Malakpet\r\n3.

chaderghat\t4.koti\r\n5. abids \t6.lakdikappol\r\n7. khairtabad\t8.panjagutta\r\n9. ameerpet \r\n"},

{"FROM : DSNR\tTO:JNTU \r\n sop no. stopname \r\n 1. DSNR \t2.Malakpet\r\n3.

chaderghat\t4.koti\r\n5. abids \t6.lakdikappol\r\n7. khairtabad\t8.panjagutta\r\n9. ameerpet \r\n"},

{"FROM : DSNR\tTO:JNTU \r\n sop no. stopname \r\n 1. DSNR \t2.Malakpet\r\n3.

chaderghat\t4.koti\r\n5. abids \t6.lakdikappol\r\n7. khairtabad\t8.panjagutta\r\n9. ameerpet

\r\n"}};

unsigned char rfid_data[11],central_data[20],rfid_flag=0;

const char tag[4][11] ={{"1D004526C2\0"},{"1D0043FE71\0"},

{"1C00FFF69F\0"},{"1E00C8CB74\0"}};

unsigned int

tag_id=0,tag_index=0,index=0,keypad_flag=0,k=0,central_flag=0,i=16,bus_number=0,len=0,src=0,ds

t=0,nop1=0;

unsigned char tx_data[11],*bus_no,*source,*destin,*nop,key[3];

int main()

{

PINSEL0 = 0x00050005;

PINSEL1 = 0x00000000;

68

PINSEL2 = 0x00000000;

IO0DIR = (1<<22) | (1<<21) | (1<<20) | (1<<19) | (1<<18) | (1<<17) | (1<<16);

//keypad initialization

IODIR1 = 0x800f0000; //P1.16-P1.19 (COLUMNS - outputs)

IOCLR1 = 0x000f0000; //making outputs(clms) low p1.16,17,18,19

IOCLR0 |= 0x0000f800; //making inputs(rows) low p0.12,13,11,15

IO1SET = (1<<31);

VPBDIV = 0x01;

uart1_init();

uart0_init();

LCD_Init();

Delay(20);

display_title1();

send_string0("\r\n Flexible BUS System ");

send_string0("\r\n BUS STOP No.1");

tx_data[0] = 'S';

tx_data[1] = 'B';

tx_data[2] = '1';

flushtext();

while(1)

{

if(rfid_flag == 1)

{

rfid_flag = 0;

send_string0(rfid_data);

tag_id = findtag_index(rfid_data);

if(tag_id < 20)

{

send_string0("\r\n id is");

69

send_char0(tag_id+48);

tx_data[3] = (unsigned char)(tag_id+48);

send_string0("\r\n Enter Bus details like \r\n -->Root Number \r\n -->Source and Destination

\r\n -->Number of persons \r\n after entering press 'C' to exit");

k = 0;i=16;

keypad_flag = 0;

display_title2();

b: display1();

keypad_flag = 0;

k=0;i=16;

while(keypad_flag == 0)

bus_no = keypad_scan();

keypad_flag = 0;

send_string0("\r\n bn:");

send_string0(bus_no);

len = strlen(bus_no);

if(len == 1) bus_number = (bus_no[0]-0x30);

else if(len == 2) bus_number = (bus_no[0]-0x30)*10 + (bus_no[1]-0x30);

if(bus_number>total_buses)

{

send_string0("\r\n Invalid bus number try again");

key[j]='\0';

}

void display_title1()

{

LCD_Command(0x01);

LCD_Command(0x80);

LCD_String("Flexible Bus sys");

LCD_Command(0xC0);

70

LCD_String("BUS STOP No.1");

}

void display_title2()

{

LCD_Command(0x01);

LCD_Command(0x80);

LCD_String("Keypad scanning");

send_string0("key pad scanning\n");

}

void display1()

{

LCD_Command(0x01);

LCD_Command(0x80);

LCD_String("Keypad scanning");

LCD_Command(0xC0);

LCD_String("Bus No :");

}

void display2()

{

LCD_Command(0x01);

LCD_Command(0x80);

LCD_String("Keypad scanning");

LCD_Command(0xC0);

LCD_String("Source :");

}

void display3()

{

LCD_Command(0x01);

71

LCD_Command(0x80);

LCD_String("Keypad scanning");

LCD_Command(0xC0);

LCD_String("Destin :");

}

void display4()

{

LCD_Command(0x01);

LCD_Command(0x80);

LCD_String("Keypad scanning");

LCD_Command(0xC0);

LCD_String("NOP :");

}

void buzzer()

{

BUZ_ON;

Delay(30);

BUZ_OFF;

}