Progress on Gigatracker Pixels

2/5/06 G. Stefanini/P326 SPC Ref/GTK WG 1

Progress on Gigatracker Pixels

• Sensors• Bump bonding• Pixel ASIC and readout electronics• Detector configuration• Cooling• Simulations

• Based on GTK Working Group meeting of 3 April 06 and latest updates

2/5/06 P. Riedler 2

IRST-itc Sensor Wafer

T

B

C. Piemonte, A. Pozza, M. Boscardin

2/5/06 P. Riedler 3

Diodes - Pre-Irradiation Tests

• I-V and C-V measured in RD50 lab at CERN

• Total leakage current at 23.7°C

• C-V indicate Vfd~15V

• One diode (B1) with higher current (~4µA)

2/5/06 P. Riedler 4

Diodes Irradiation in Ljubljana• TRIGA reactor, 250kW, irradiation with fast neutrons• All diodes biased at 30V during irradiation• Guard and pad contact connected together• Fluence levels from 1.0x1012 to 2.0x1014 ( 1 MeV n eq/cm2) - including 2x safety factor• Immediately after irradiation stored in freezer (-20°C)

A1,B1

A2

B4

B3

B2

2/5/06 P. Riedler 5

Study of Radiation Damage in Diodes

• Annealing measurements (CERN + Ferrara)– According to ROSE standards with I-V and C-V– Measurements last week on 5 irradiated diodes at 80 degC– Bias voltage up to 400V in order to verify the current stability– One diode also measured after full annealing with bias up to

1,000V ===> no indication of breakdown– The current behaviour at low bias voltage needs further study

• Measurements just completed, analysis under way

• Further work– More irradiations at the T7 facility at CERN

3/4/06 P. Riedler 6

Sensor Wafers Processing

• Two sensor wafers sent to VTT for processing (end 2005)• Visual inspection showed excellent quality• Both wafers showed strong bow (~60-70µm)

– potential problem for bump bonding process (requires < 30µm)

• Both wafers broke up in the photo-resist track at VTT– probably due to the bow of the wafers combined with tight

dimensional tolerances in the automated centering stage

• The limit settings have been changed• More wafers reworked by IRST ==> smaller bow

3/4/06 P. Riedler 7A. Pozza

3/4/06 P. Riedler 8A. Pozza


Wafer Processing and Bump Bondingat VTT (II)

• In week 9: fire incident in one of the VTT clean rooms

• Electroplating benches (Ni and Pb-Sn deposition), reflow oven (bump bonding) and CMP machine (thinning) were affected

• Equipment cleaned, inspected and moved to second clean room

• First ladders delivered this week


• Readout wafers (200mm diameter) target thickness: 100µm or less, to reduce material budget– sensor wafers thickness is constrained by signal amplitude

• One blank wafer thinned successfully to 100µm

• Upcoming tests: thin (dummy) bumped wafer to 100µm

• Discussion with VTT end of March on thinning - several points of concern (e.g. stress effects) discussed and tests planned

Thinning at VTT (I)

2/5/06 11

1st GTK chip design meetingWhere, when, who

• Torino, 21.03.2006

• People attending the meeting:– Ferrara: A. Cotta Ramusino, R. Malaguti– Torino: A. Rivetti, G. Mazza, S. Martoiu, A. La Rosa– CERN: A. Kluge, S. Tiuraniemi, G. Anelli

G. Anelli

2/5/06 12

First important decision taken• We made the choice of using a 0.13 um CMOS technology. The main

reasons behind the choice are:– The 0.25 um technology might not be available to us at the time of

production of the chip;– The design kit of the 0.25 um technology is not maintained anymore;– The 0.13 um technology will be available to us for many years in the

future;– The 0.13 um technology offers a superior performance for digital

circuits;– Most of the problems of using this technology are solved or being

solved: more and more people in the community are using it, a design kit is going to be prepared soon, CERN will have a frame contract with a vendor and will organize frequent MPWs as it has been done for the 0.25 um technology in the past.

G. Anelli

2/5/06 13

Second important decision• We plan to submit a test chip containing several test structures and

basic blocks in August – October 2006. An exact date has not been fixed yet, this depends also on the outcome of CERN’s call for tender. One option could be to submit a 10 mm^2 chip on the 7th of August through Mosis (IBM 0.13 um LM technology).

• We decided to share the responsibilities as follows:– Preamplifier: Giovanni A., Angelo R., maybe Sakari T.;– Current mode CFD: Sorin M.;– One TDC per pixel: Angelo R., Sorin M.;– Time over threshold: Alex K., Giovanni A.;– CFD: Angelo C.R., Roberto M., Stefano C.;– General architecture, trigger: Alex K., Gianni M.;– T.D.C.: Gianni M., Sakari T.;– Substrate noise: Sakari T., Giovanni A.;– LVDS buffers: Sakari T.;– RC delay and jitter in lines: Angelo C.R., Roberto M., Stefano C.

G. Anelli

2/5/06 14

Issues still under discussion• Time-walk cancellation is a very critical issue to get the necessary

timing resolution. This is also why we will investigate in parallel several possibilities (2 CFD architectures and TOT);

• In the first test chip we might not be using enclosed transistors, if this gives problem with the extraction. Nevertheless, all the designs have to be made keeping in mind the limitations of using ELTs;

• LVDS drivers: what is the C of what we are going to drive with them? Question about DC or AC coupling;

• Having two power supplies implies more lines and more material budget;

• How will we test the blocks. We stress the importance of thinking about how to test what we design when we design it. Also, whenever it is possible, we should include testability features;

• How to cover the beam area is a hot topic. The solution with a 21 mm long chip biased on one side only seems not feasible. Power drops on the power distribution lines will be important. Also, we all agree that 3 mm are not enough to fit all the circuitry we need outside the matrix.

G. Anelli

2/5/06 A. Kluge 15

General: Chip Specifications

Chip Parameter

Specification Preliminary Design parameter

Time resolution

160/200 ps 160/200 ps (bin size?)

Beam size(a x b)

48 x 36 mm2 48 x 36 mm2

Pixel size(a x b)

300 x 300 µm2 300 x 300 µm2

Matrix size

(a x b)

32 x ?

Active area/per chip(a x b)

9.6 x ? mm2

# chip/module

(a x b)

5 x 2 / 5 x 3 / 4 x 3

Calculation,simulation Working parameters

2/5/06 A. Kluge 16

General: Chip SpecificationsChip Parameter

First ideas Specification Preliminary Design parameter

Avg Rate: avg/max

60/173 MHz/cm2 Depends on TDC, segmentation

Efficiency 99%98% for center??

Number of pixels/segment

1 (analog TDC)

7-20 (digital TDC)

Dead time of segment

100 ns for 1 TDC/pixel

7 -10 ns for shared TDC

Buffer size per segment

Readout speed/Trans-mission speed

Needs to operate in vacuum

Yes/no ??

2/5/06 A. Kluge 17

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Configuration

2/5/06 A. Kluge 18

Chip size

Readout and supply

21 mm18 mm

3 mm• Readout needs

possibly more space ->not leaving 18mm active area

• Supply from one side has strong power drop

• Thinning of long narrow chips more difficult

Readout and supply

2/5/06 A. Kluge 19

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Configuration

• Highest rate

2/5/06 A. Kluge 20

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Configuration

Max rate on one chip, but chip smaller

2/5/06 A. Kluge 21

Configuration 3 x 4• Assume matrix of 40 rows x 40 columns:

– 12 mm x 12 mm = 144 mm2

• Chip size– (12 + (2 x 3mm)) x 12 mm = 18 x 12 mm

• Pixel size 300 um x 300 um – => 40 x 40 pixels = 1600 pixels

• Max. Avg Rate of center chip: ~150 MHz/cm2

(for beam with max. 173 MHZ/cm2)– => 135 kHz/pixel– => 216 MHz/chip– => 216 MHz/chip * ~32 bit = 6.9 Gbit/s

3/4/06 P. Riedler 22

3/4/06 P. Riedler 23


Material Budget - Cooling

• Conflicting requirements on detector configuration• Material budget

– crucial issue - should be minimized (simulations)– 2x4 (or 2x5) detector configuration preferred– long chips with power/readout pads on one short side only

• Chip design– 3x4 (3x5) detector configuration preferred– shorter chips with power/readout pads on both short sides

• Cooling– same considerations as for material budget– average temperature and thermal gradients should be

minimized


Preliminary Cooling Model & Estimates (I)

GS/P326 SPIBES cooling/draft_v0/180406

Preliminary considerations on the cooling of the P326Gigatracker silicon pixel detector (SPIBES)

GeneralThe aim of this note is to overview the main requirements and constraints for the development ofthe SPIBES, and to outline concepts of possible cooling solutions. It i s a working document;assumptions and estimates need to be carefully cross-checked. It will hopefully be useful to start adiscussion at this stage of the project.

The SPIBES consists of 2 at least (3 probably) hybrid pixel detector planes. The p ixel celldimensions are 300μm x 300μm in all plane .s The active area, in which the the beam is fullycontained, is 36mm 48x mm approximately; small adjustments in the beam cross section, of theorder of ≈ 3mm, m aystill be possible by tuning t he beam optics.

A mandatory requirement is that the material budget in the active area is kept to an absoluteminimum. The SPIBES design is based on hybrid pixel detectors, consisting of assemblies ofelectronic chips bump bonded to sensors. The thickness of the sensor can hardly be reduced to lessthan 200 μm, as the signa l amplitud ewould otherwis e b e too small. In the cas eof the readout chips,it isplanned to thin th e200 mmdiameter wafers after bump deposition. Fro m the experience gainedwit hthe ALIC E pixels, it isexpect edthat pixel chip die of 100μm thickness can be obtained; that islikely to bethe limit of what can be achieved in practice within the project timescale. Thus theoverall thickness of silicon will be 300μm corresponding to a material budget of ≈ 0.32% X0. Thecontribution of the bumps (essentially P )b of 25μm at the pitch of the pixel cells, smeared over thechip are , a is well below 0.01% X0.

A major challenge derives from mechanical support and services. These include power supply and/I O signal lines, SMD passive components for termination and filteri ,ng cooling system et .c Thecontribution of these items in the active area should belimited to less than 0.1% X0 or as small asfeasible. These tight materia l budge t constraints do no t appl y outside the acti vearea, where the bulkof services coul d be located.

It is assumed that all stations will be located inside the vacuum pipe in order to avoid usingwindows. The sensor layer of each plane must be the downstream side to reduce the effects ofscattering i nthe detector materia .l

The detector will be exposed to an integrated fluence of about 2.1014 (1 MeV n equivalen /t cm2 )during the physics r .un These levels are comparable to those expected in inner layers of the LHCtrackers, and will reached in a much shorter time (a few months). In order to limit the leakagecurrent increase induced by radiation damage, the operating temperature of the sensors should bekept (wel )l below 10 degC. The syste m should however be designed to allow replacing the detectorplanes by new ones at regular intervals, if necessar ,y without breaking the vacuum.


Preliminary Cooling Model & Estimates (II)

GS/180406P326 Gigatracker - SPIBES - Cooling

Material properties

density radiation length th. conductivity CTE notesd Xo λ k/ 3g cm cm /W cmK /ppm K

Si 2.34 9.36 1.50 2.60 300@ K2.60 200@ K

/ CFC support cooling plane material characteristics may vary with supplier 55Toray M J 1.91 23.00 1.50 -1.13 used in ALICE SPD

-1100Thornel K 2.20 23.00 10.00 -1.45 λ longitudinal 8000 Thornel X panels 1.76 23.00 8.00 -1.70 λ longitudinal-carbon carbon 1.75 23.00 2.50 -1.50 λ (0.75 )longitudinal transverse

- ( 52029)non silicone thermal interface compound AOS 2.80 33.00 1.3 -02E ( )Xo estimate not measured

4 10C F 1.52 23.00 20 density at degC6 14C F 1.68 21.00 25 density at degC

( )Polyimide Kapton 1.42 28.60 1.2 -03E 20.00

Be 1.84 35.40 2.00 11.60Al 2.70 8.90 2.35 23.60Cu 8.96 1.43 4.00 16.00Sn 7.30 1.20 0.66 23.40Pb 11.35 0.56 0.35 28.90

- (63/37 / )eutectic tin lead solder for bump bonds Sn Pb 8.94 0.82 0.55 calculated

Pixel ASIClength cm 2.0width cm 1.0area 2cm 2.0

power dissipation per unit area / 2W cm 2.0thickness cm 0.01

Sensorthickness cm 0.02

( )Material budget excluding services

Silicon + pixel chip sensor % of Xo 0.32

Contribution of bump bonds to material budget chip active length cm 1.8 chip active width cm 0.9 chip active area 2cm 1.62 bump pitch cm 3.00 -02E

number of bumps 1,800 bump diameter cm 2.50 -03E volume of each bump 3cm 8.18 -09E

total volume of bumps 3cm 1.47 -05E ( )equivalent bump thickness smeared cm 9.09 -06E

( )material budget of equivalent bump thickness smeared% of Xo 1.11 -03E

Thermal impedance of bumps ( - ) bump height stand off after reflow bump bondingcm 0.0007

equivalent bump contact surface 2cm 1.17 -05E- T drop at bump degC 2.44 -01E

(1)Configuration

- Case A Single short edge chip cooling thermal grease strip width cm 0.5 thermal grease strip thickness cm 0.01

- T drop at thermal interface with cooling degC 6.2- T drop along bump bonded assembly 88.9

- Case B Cooling by coupling to a CFC plate cooled at the edges ( )CFC thermal conductivity effective /W cmK 6.00 longitudinal plate thickness cm 0.02 /plate height width cm 5.00

- (20 / )T drop across half CFC plate W plane degC 41.67 plate cooled on two opposite sides overall material budget % of Xo 0.41


Summary

• Progress in all areas– Sensors: prototyping, radiation testing, bump bonding– Chip design: decision taken on choice of technology, defined sharing of

tasks, MPW submission in preparation– Detector configuration and cooling: evaluation of options– Simulation

• Further progress critically depends on deeper understanding of material budget constraints ( ==> fast simulation, full GEANT simulation)

• Concerns on resources– Manpower: urgently need 2 (3) students at CERN (staff currently fully

booked for LHC experiment)– Funding: cost of materials, wafer processing, bump bonding, MPW

submission

Documents

Progress on Gigatracker Pixels