Programmable Logic SystemsEEE540Lecture 1

Dr. Jim Harkin

Semester 12011-2012

Contents• Learning Objectives

• Introduction/Rationale for Hardware Implementations

• Introduction to Programmable Logic

• PROMS\PLD\PALs devices

• CPLDs devices

• Additional Reading List

• Summary

Learning Objectives

(i) Understand the factors considered when realising computations on hardware

(ii) Appreciate the principle difference between the various hardware implementation mediums

(iii) Understand the different programming technologies used in programmable logic systems

(iii) Be able to differentiate between PROMs/PLA/PALs

(iv) Be able to appreciate the architecture of CPLDs

Introduction/Rationale • Hardware digital design addresses the realisation of functionality in electronic hardware.

• By tradition engineers have used general-purpose processors executing software programs to implement functionality in hardware.

• This provides an easy method of realising functionality.

• By tradition - suffers from slow speed-performance.

• Customised hardware such as ASICs provide functionality at increased performance levels.

• What are the deciding factors for realising functionality in hardware?

- software/processor verses custom hardware argument.

• Software executing on a hardware processor provides high flexibility with low performance.

• Custom hardware provides high performance with low flexibility.

- is it that simple?

• No there are more factors to be considered!!

Why Implement in Hardware?

Implementation considerations

• What should an engineer consider when selecting a implementation medium?

- Power consumption limits.

Speed performance required.

- Device area\size limits.

- Flexibility\re-use required.

- Domain specific features required and end-target application domain.

- Financial cost constraints (can depend on sales volume).

Categorizing Implementation Technologies

• Implementation technologies can be divided into several categories with varied levels of flexibility in implementation, design re-use and manufacturing cost.

• Each category provides devices with varied technology traits, e.g. speed, low-power, flexibility etc.

• Trade-off for selection of devices varies between cost of production (cost\volume ratio), design-performance specification and level of design flexibility

Implementation PathsApplication Design

New start

FPGA C/PLD

StaticFlash Fuse/anti

SoC\SiP & IP

MicrosDSP

Custom Asic

Flexible Hardware

Fixed hardware

Fixed Hardware

Performance\flexibility trade-off

E(E)PROM

StandardASIC

Processors SSI/MSISemi-customFull-custom

Gate Array Standard Cell

Implementation Trade-offs

• Provides definite implementation paths for designers with estimated costs and design-times.

• Particular devices can provide speed and low-power but without post-fabrication design flexibility.

• ASICs (semi) provide flexibility and low power for designs, but with larger financial costs and substantial design-times.

• Standard provide lower cost off the shelve computing component and shorter design-times, but possibly providing lower performance and higher power consumption.

• Financial cost plays a major role in deciding which path a initial design implementation will follow.

Standard Device Technology

• Standard devices are typically off-the-shelve computing components

• Provide low cost solutions

• Power consumption and performance vary between devices

• Devices re-programmed by software, i.e. limited flexibility

• Inherently sequential, limited parallelism exploited

• Short design time

• Several different device technologies available including: Microprocessor

Microcontroller (Harvard, 8-bit to 64-bit ) DSPs, i.e. domain-specific processors (32-bit)

Full-custom Technology

• Full-custom designs can provide optimal implementations, i.e. lowest power consumption, fastest execution speeds

• Expensive due to cost of mask designs and small volume for production; @ 40nm mask costs can exceed ~£1.6M Pounds1…32nm is approaching

• Designs cannot be altered after fabrication, i.e. no re-programmability or design flexibility

• Design times can be substantial up to 18 months

• Designs re-spins are often required increasing design time

• Example ASIC chip application include digital TV and VoIP

[1] http://www.electronicsweekly.com/Articles/2008/06/18/43977/achieving-first-time-success-at-40-nm.htm

Semi-custom Technology• Semi-custom designs provide sub-optimal implementations, i.e. power consumption can be modest compared to full-custom and execution speeds are lower

• Non-expensive compared to full-custom as cost of mask design can be amortized over large volumes for production

• Designs can be altered after fabrication, i.e. re-programmed

• Design times can be less as standard cell and gate arrays are pre-defined components that can be easily incorporated, 9-12 months

• The trade-off of performance to obtain increased flexibility and lower costs has seen the creation of programmable logic

Programmable Logic

What is Programmable Logic (PL)?

• PL is a system for encapsulating your digital circuitry into a programmable integrated circuit device.

• Definition: A logic element whose operation is not restricted to any particular function.  It may be programmed at different points of the life cycle.  • Programming stages of the life cycle: 1) at the earliest, it is programmed by the semiconductor vendor (standard cell, gate array), 2) by the designer prior to assembly or field deployment, 3) or by the user, in circuit.

Programmable Logic Devices

• There are three types of programmable logic devices available: 1) PLA/PALs 2) SPLD/CPLD {Simple(S) and Complex(C) PLDs} 3) FPGAs

• Some types are only capable of implementing small levels of digital logic.

• Others, like FPGAs, can hold a complete microprocessor-based embedded systems.

• In addition to this difference in size, there is also much variation in architectures.

Programmable Logic Devices – programmable technologies

• Programmable logic devices are available using several different programmable technologies:

fuse anti-fuse volatile non-volatile switch

Programmable Logic Devices - programmable technologies

• Fuse - This is a two-terminal programmable element that is normally a low resistive element and is programmed or "blown" resulting in an open or high impedance.   • Anti-fuse - This is a two-terminal element that is normally a high resistive element and is programmed to a low impedance. 

• Volatile memory – (uses actual memory ) The memory elements lose their contents when power is removed from the device.  SRAM-based devices are volatile and require another device to store their configuration program.

Programmable Logic Devices - programmable technologies

Fuse links

a

Fat

Logic 1

y = a & !b&

b

Fbf

Pull-up resistors

NOT

NOT

AND

a

Logic 1

y = !a & b&

b

Pull-up resistors

Programmedantifuses

NOT

NOT

AND

Anti-fuse links

Volatile memory – SRAM programmable

SRAM

Diagrams: Clive Maxwell – “The Design Warrior’s Guide to FPGAs”

Programmable Logic Devices - programmable elements

Non-volatile memory - The memory elements keep their contents when power is removed from the device, e.g. Flash, EEPROM, EPROM 

- The memory element may be one-time programmable or re-programmable. - Programmable devices can be both non-volatile and re-programmable.

• Switch - This device consists of a memory element (either volatile or non-volatile) which controls a switch. Volatile SRAM-based memory elements are commonly used today.

Classifying Devices

• Device can be classed based on their level of programmability

- One Time Programmable: Devices can be programmed only once; it's contents can not be changed. While typically these devices are fuse or anti-fuse based, they can also be low-cost EPROM devices. 

- Re-programmable: These devices can have their configuration loaded more than once. SRAM-based and Flash-based devices may be reloaded without restriction. 

Implementation PathsApplication Design

Processors SSI/MSI

StandardASIC

Semi-customFull-custom

New start

FPGA C/PLD

StaticFlash Fuse/anti

SoC\SiP & IP

MicrosDSP

Custom

E(E)PROM

Gate Array Standard Cell

Programmable Logic Devices –

• Gate arrays Transistors or gates are fabricated in a 2 dimensional array. It forms the standard base of an application specific integrated circuit (ASIC).  The device is programmed by custom metal layers inter-connecting nodes in the array. 

• Standard Cell Pre-defined cells are used in an arbitrary structure. This device differs from the gate array since each cell may be different and optimized for each "standard" function.

PROM\PALs\PALs

PROMs\PLAS\PALs What is the difference?

• PROM\PAL\PLAs are collectively know as SPLDs (simple programmable logic devices)

Programmable Logic Devices -PROMs

• Programmable read-only Memory (PROM) - The programmable element for these devices include EPROM, EEPROM, fuses and anti-fuses. 

• PLAs have mostly replaced them.

Example Boolean function

Boolean circuit Logic Table

a b c w x y

0 0 0 0 1 00 0 1 0 1 1

0 1 0 0 1 00 1 1 0 1 11 0 0 0 1 01 0 1 0 1 1

1 1 0 1 0 11 1 1 1 0 0

l

&a

b

c

w

x

y

Diagrams: Clive Maxwell – “The Design Warrior’s Guide to FPGAs”

Programmable Logic Devices -PROMs

• Implementation of Boolean function on PROM device

a b c

l l l

Address 0 &

Address 1 &

Address 2 &

Address 3 &

Address 4 &

Address 5 &

Address 6 &

Address 7 &

a !a b !b c !c

!a !c!b& &

!a c!b& &

!a !cb& &

!a cb& &

a !c!b& &

a c!b& &

a !cb& &

a cb& &

Predefined AND array

Pro

gram

mab

le O

R a

rray

w x y

Predefined linkProgrammable link

w = (a & b)

x = !(a & b)

y = (a & b) ^ c

l

&a

b

c

w

x

y

Diagrams: Clive Maxwell – “The Design Warrior’s Guide to FPGAs”

Programmable Array Logic\ Logic Arrays

• PAL\PLAs have a simple structure comprising of a large AND plane connecting to an OR plane with registered outputs, i.e. Sum-of-products (SOP)

• First appeared in the late 1970s

• Logic designs are implemented by programming the connections between device inputs, AND\OR planes and device output pins

• Degree of connectivity is low (simple routing topology!)

• Devices are based on Fuse, EEPROM and Flash technology

• Fuse (one-time programmed), EEPROM and Flash (re-programmable)

PAL\PLA

• Manufacturers include Cypress Logic, Philips, Atmel, Lattice, AMD, Xilinx

• Example device, ispGAL 22V10A device from Lattice Semiconductors

- 32-pin package (5mm x 5mm)- 1.8 volt. supply with 100 micro amp standby- 455 MHz clocking speed- Less than $1 (volume > 50K)

• General structure

• All links are programmable

a b c

&

&

&

a !a b !b c !c

N/A

Predefined AND array

Pro

gram

mab

leO

R a

rray

Predefined linkProgrammable link

l l l

w x y

N/A

N/A

Courtesy Clive Maxwell

PAL\PLA• Structure of Lattice ispGAL22V10A PAL

I\O withF\Fs

OR planeAND plane

Inter-connections

Inputs

Courtesy Lattice Data Sheet

PAL\PLA

• Provide low power consumptions but limited to the degree of logic that can be implemented.

• Low power due to simple routing topology.

• Low capacitance from switching.

• Typically contain up to several thousand logic gates (Gate count is a metric used to compare densities with ASICs).

• Generally used to implement simple glue logic, address decoders, devices interfaces.

• Hardware designs for PAL\PLAs are generally written in languages like ABEL or PALASM (hardware equivalents of assembly).

PAL\PLA

• PAL ApplicationSections of the system implemented using PALs

Diagram: Xilinx Application Note

CPLDs

Complex Programmable Logic Devices (CPLDs)

• CPLDs evolved from PAL\PLAs - as chip densities increased, it was natural for the PLD manufacturers to evolve their products into larger parts (several tens of thousands of gates).

• Larger sizes of CPLDs allow either more logic equations or more complicated designs to be realised.

• Current devices have additional logic and registers units and more complex routing topologies than PAL/PLAs.

• Complex routing provides greater flexibility.

• Clock management, clock dividers + global routing lines.

CPLDs• Sleep\standby power facilities available in modern devices.

• Core voltage supplies have dropped as low as 1.8v.

• Cheap solution for small and simple tasks, around £3-8.

• CPLD are also being used to interface between different signalling levels, e.g. TTL to LVTTL.

CPLD Structure

• Generic structure - each of the four logic blocks are equivalent to one PLD.

ProgrammableInterconnect

matrix

Input/output pinsSPLD-like

blocks

• Each logic block may also be comprised of macro cells and interconnect wiring, just like an ordinary PLD.

• Manufacturers include Xilinx, Altera, Atmel, Actel, Lattice.

1. SPLD

3. SPLD

2. SPLD

4. SPLD

Diagrams: Clive Maxwell – “The Design Warrior’s Guide to FPGAs”

Example CPLD Device• Example CPLD - Xilinx XC2C512 CoolRunner-II

- 180 Nanometer technology - clocking speed 217MHz (Max 333MHz in family)- core voltage 1.8v, (I/O requires 3.3v)- Macro cell based structure (512 capacity)- advanced routing with global clocks + clock dividers- low power, typically several hundred micro amps through DataGate feature- Flash programming (20 yrs data retention)- integrates with Xilinx FPGA software- low cost solution, less than £5 (volume >10K)

CPLDs –Xilinx CoolRunner-II

• Family of devices and parameters

Clock speed

No. of I/O available No. of marco cells in device

Courtesy Xilinx Data Sheet

CPLDs –Xilinx CoolRunner-II

• CoolRunner-II Architecture

Advanced Interconnect Matrix

Macro Cells

PLAs

I/O I/O

Courtesy Xilinx Data Sheet

CPLDs - Macro Cell (MC)

Inputs

Outputs

AdditionalLogic

FF\Latch

Feedback lines

CoolRunner-II Macro Cell Structure

• Circuit functions are implemented by configuring the muxes etc.

Courtesy Xilinx Data Sheet

CPLDs - Applications

Interface to micro-controller (FSM)

Interface to bus (change between voltage-standards)

CPLDs are still occasionally used for simple applications like address decoding, but more often contain high-performance control-logic or complex finite state machines.

Courtesy Xilinx Data Sheet

CPLDs - Applications

GPS Navigation Systems

http://www.xilinx.com/products/silicon_solutions/cplds/coolrunner_series/coolrunner_ii_cplds/teardowns/gps.html

http://www.xilinx.com/products/silicon_solutions/cplds/coolrunner_series/coolrunner_ii_cplds/teardowns/pdas.html

- Hard disk controller- GPIO interface- Timing configuration

- LCD Timing Control - GPIO Expansion - Power Management

- Level Shifting

PDA

CPLDs - Applications

http://www.xilinx.com/products/silicon_solutions/cplds/coolrunner_series/coolrunner_ii_cplds/teardowns/gsm.html

http://www.xilinx.com/products/silicon_solutions/cplds/coolrunner_series/coolrunner_ii_cplds/teardowns/printers.html

- Keypad scanner - Logic consolidation

- Controller and interface conversion - Interface expansion - Simple glue logic

PrinterGSM Phone

CPLDs - ApplicationsP1200 portable handsets (Shenzhen Huayu Communications Technology Company, China )

http://connectiononline.blogspot.com/2008/06/huayu-communications-selects-alteras.html

• Altera MAX II CPLD• Interfaces with: - Radio Frequency Identification (RFID) reader - Infrared Data (IRDA) sensor - Bluetooth interface

CPLDs - ApplicationsRobot controller CD/audio controller

http://www.youtube.com/watch?v=3Gi1x7m2RzI&mode=related&search

http://www.youtube.com/watch?v=Clix6szx16U

Summary

• Provided an introduction to hardware implementation mediums.

• Introduced PLDs and the varied number of programmable elements, PLD types and an example commercial device.

• Provided an overview of CPLDs and their advantages over traditional PLDs.

• Presented a commercial CPLD device and highlighted its features and applications.

Lecture Notes

Recommended reading – lecture notes

• Clive Maxwell – “The Design Warrior’s Guide to FPGAs” Publisher Elsevier, 2005

Library shelf number: TK7872.L64.M28

Read pages 10- 41.