PROGRAMMABLE LOGIC DESIGN WITH VHDL · PDF filePROGRAMMABLE LOGIC DESIGN WITH VHDL. VHDL Training ©1997 Cypress Semiconductor, rev 2.5.3 2 Why Use VHDL? Quick Time-to-Market ... tens

VHDL Training

©1997 Cypress Semiconductor, rev 2.5.31

PROGRAMMABLE LOGIC DESIGN WITH VHDL

VHDL Training


Why Use VHDL?

Quick Time-to-Market

Allows designers to quickly develop designs requiring tens of thousands of logic gates

Provides powerful high-level constructs for describing complex logic

Supports modular design methodology and multiple levels of hierarchy

One language for design and simulation

Allows creation of device-independent designs that are portable to multiple vendors.

Allows user to pick any synthesis tool, vendor, or device

VHDL Training


PLD Design Flow

Design Entry

Schematic Capture/HDL or Both

Front-End Simulation (optional)

Design Compilation

Synthesis, Fitting/Place&Route

Design Verification

Back-End Simulation (optional)

Device Programming

VHDL Training


Front

End

Back

End

Schematic Text

Synthesis

Fitting Place&Route

Simulation

Sim. Model

Design

Entry

Design

Compilation

SimulationJEDEC

File

Prog.

File

Design

Verification

Programmer

VHDL Training


VHDL Design Descriptions

VHDL design descriptions (referred to as "design entities") consist of an ENTITY declaration and ARCHITECTURE body pair

The ENTITY declaration describes the design I/O

The ARCHITECTURE body describes the content of the design

VHDL Training


VHDL Entity/Architecture Pairs:2-Input And Function

ENTITY and2 IS PORT (

a,b : IN std_logic;

f: OUT std_logic);

END and2;

ARCHITECTURE behavioral OF and2 IS

BEGIN

f <= a AND b;

END behavioral;

VHDL Training


The Entity

A “BLACK BOX”

The ENTITY describes the periphery of the black box (i.e., the design I/O)

BLACK_BOX

rst

d[7:0]

clk

q[7:0]

co

VHDL Training


Example Entity declaration

ENTITY black_box IS PORT (

clk, rst: IN std_logic;

d: IN std_logic_vector(7 DOWNTO 0);

q: OUT std_logic_vector(7 DOWNTO 0);

co: OUT std_logic);

END black_box;

More shortly

BLACK_BOX

rst

d[7:0]

clk

q[7:0]

co

VHDL Training


ENTITY entity_name IS PORT (

-- optional generics

name : mode type ;

...

) ;

END entity_name;

entity_name is an arbitrary name

generics are used for defining parameterized components

name is the signal/port identifier and may be a comma separate list for ports of identical modes and types

mode describes the direction the data is flowing

type indicates the set of values the port name may be assigned

The Entity Declaration

VHDL Training


Ports

The Entity (“BLACK BOX”) has PORTS

PORTS are points of communication

• PORTS are often associated with the device pins

PORTS are a special class of SIGNAL

PORTS have an associated SIGNAL name,mode, and type

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PORT modes

A port‟s MODE is the direction data is transferred:

IN Data goes into the entity but not out

OUT Data goes out of the entity but not in (and is not used internally)

INOUT Data is bi-directional (goes into and out of the entity)

BUFFER Data that goes out of the entity and is also fed-back internally within the entity

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IEEE 1076 Types

VHDL is a strongly typed language (you cannot assign a signal of one type to the signal of another type)

bit - a signal of type bit that can only take values of '0' or '1'

bit_vector - a grouping of bits (each can be '0' or '1')

SIGNAL a: BIT_VECTOR(0 TO 3); -- ascending range

SIGNAL b: BIT_VECTOR(3 DOWNTO 0); -- descending range

a <= "0111"; -- double quotes used for vectors

b <= "0101";

This means that: a(0) = '0' b(0) = '1'

a(1) = '1' b(1) = '0'

a(2) = '1' b(2) = '1'

a(3) = '1' b(3) = '0'

VHDL Training


INTEGER

• useful as index holders for loops, constants, generics, or high-level modeling

BOOLEAN

• can take values „TRUE‟ or „FALSE‟

ENUMERATED

• has user defined set of possible values, e.g.,

• TYPE states IS (start, slow, fast, stop);

IEEE 1076 TYPES (contd.)

VHDL Training


IEEE 1164

"Multi-value logic system for VHDL interoperability"

A package created as an aid to VHDL users

Nine values as opposed to two ('0' and '1')

Allows increased flexibility in behavioral VHDL coding, synthesis, and simulation

std_logic and std_logic_vector are used as opposed to bit and bit_vector when a multi-valued logic system is required.

std_logic and std_logic_vector are used when tri-state logic is required.

VHDL Training


1164 Types

std_logic and std_logic_vector are the industry standard logic type for digital design

All 9 values are valid in a VHDL simulator, however only:

„0‟ -- Forcing „0‟

„1‟ -- Forcing „1‟

„Z‟ -- High Impedance

„L‟ -- Weak „0‟

„H‟ -- Weak „1‟

„-‟ -- Don‟t care

are recognized for logic synthesis

VHDL Training


Entity Declaration ExampleLIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY black_box IS PORT (

clk, rst: IN std_logic;


q: OUT std_logic_vector(7 DOWNTO 0);

co: OUT std_logic);

END black_box;BLACK_BOX

rst

d[7:0]

clk

q[7:0]

co

MODETYPE

VHDL Training


Exercise #1: The Entity

Write an entity declaration for the following:

Port D is a 12-bit bus, input only

Port OE and CLK are each input bits

Port AD is a 12-bit, three-state bi-directional bus

Port A is a 12-bit bus, output only

Port INT is a three-state output

Port AS is an output also used internally

my_design

d[11:0]

oe

clk

ad[11:0]

a[11:0]

intas

VHDL Training


Exercise #1: Solution

LIBRARY ieee;


ENTITY my_design IS PORT (


oe, clk: IN std_logic;

ad: INOUT std_logic_vector(11 DOWNTO 0);

a: OUT std_logic_vector(11 DOWNTO 0);

int: OUT std_logic;

as: BUFFER std_logic);

END my_design;

-- In this presentation, VHDL keywords

-- are highlighted in bold, CAPITALS;

-- however, VHDL is not case sensitive:

-- clock, Clock, CLOCK all refer to the

-- same signal, -- means a comment

my_design

d[11:0]

oe

clk

ad[11:0]

a[11:0]

intas

VHDL Training


The Architecture

Architectures describe what is in the black box (i.e., the structure or behavior of entities)

Descriptions can be either a combination of

Structural descriptions

• Instantiations (placements of logic much like in a schematic and their connections) of building blocks referred to as components

Behavioral/Dataflow descriptions

• Algorithmic (or “high-level”) descriptions:

IF a = b THEN state <= state5;

• Boolean equations (also referred to as dataflow):

x <= (a OR b) AND c;

VHDL Training


ARCHITECTURE arch_name OF entity_name IS

-- optional signal declarations, etc.

BEGIN

--VHDL statements

END arch_name;

arch_name is an arbitrary name

optional signal declarations are used for signals local to the architecture body (that is, not the entity‟s I/O).

entity_name is the entity name

statements describe the function or contents of the entity

The Architecture Declaration

VHDL Training


Architecture Body Styles : BehavioralENTITY compare IS PORT (

a, b: IN std_logic_vector(0 TO 3);

equals: OUT std_logic);

END compare;

ARCHITECTURE behavior OF compare IS

BEGIN

comp: PROCESS (a,b)

BEGIN

IF a = b THEN

equals <= '1' ;

ELSE

equals <= '0' ;

END IF ;

END PROCESS comp;

END behavior;

VHDL Training


Architecture Body Styles : Dataflow

ENTITY compare IS PORT (



END compare;

ARCHITECTURE dataflow OF compare IS

BEGIN

equals <= '1' WHEN a = b ELSE '0' ;

END dataflow;

VHDL Training


Architecture Body Styles : Structural




END compare;

USE WORK.gatespkg.ALL ;

ARCHITECTURE structure OF compare IS

SIGNAL x : std_logic_vector (0 to 3) ;

BEGIN

u0: xnor2 PORT MAP (a(0),b(0),x(0)) ;




u4: and4 PORT MAP (x(0),x(1),x(2),x(3),equals) ;

END structure;

VHDL Training


Comparing Architecture Styles

These examples synthesize to equivalent circuits

In more elaborate designs, some descriptions may yield more efficient circuits

sloppy code = inefficient results (see section 3.3.4)

Use styles that make your designs easier to describe and maintain

Behavioral/Dataflow exploit module generation (described later)

Structural descriptions may make the design less portable (may rely on a library of vendor-specific components)

VHDL Training


Mixing Architecture Styles

The various styles may be mixed in one architecture.

ENTITY logic IS PORT (

a,b,c: IN std_logic;

f: OUT std_logic);

END logic;

USE WORK.gatespkg.ALL;

ARCHITECTURE archlogic OF logic IS

SIGNAL d: std_logic;

BEGIN

d <= a AND b;

g1: nor2 PORT MAP (c, d, f);

END archlogic;

a

b

c

d

f

LOGIC

Behavioral/Dataflow

Structural

g1

VHDL Training


VHDL Statements

There are two types of statements

Sequential

• Though hardware is concurrent, it may be modeled with algorithms, by a series of sequential statements

• By definition, sequential statements are grouped using a process statement.

Concurrent

• Statements outside of a process are evaluated concurrently during simulation

• Processes are concurrent statements

VHDL Training


Concurrent Statements

Concurrent statements include:

boolean equations

conditional/selective signal assignments (when/else, with/select)

instantiations

Examples of concurrent statements:

-- Examples of boolean equations

x <= (a AND (NOT sel1)) OR (b AND sel1);

g <= NOT (y AND sel2);

-- Examples of conditional assignments

y <= d WHEN (sel1 = '1') ELSE c;

h <= '0' WHEN (x = '1' AND sel2 = '0') ELSE

'1';

-- Examples of instantiation

inst: nand2 PORT MAP (h, g, f);

VHDL Training


The Process Statement

Used to construct algorithms/group sequential statements

Statements within a process are sequential statements they execute sequentially during simulation

An architecture can contain multiple processes. Each process is executed concurrently

Processes may be used to model combinational or synchronous logic

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The Process (contd.)

label: PROCESS (sensitivity list)

-- variable declarations

BEGIN

-- sequential statements

END PROCESS label ;

The process label and variable declarations are optional

The process executes when one of the signals in the sensitivity list has an event (changes value).

VHDL Training


Process (contd.)

Processes are executing or suspended (active or inactive/awake or asleep)

A process typically has a sensitivity list

When a signal in the sensitivity list changes value, the process is executed by the simulator

e.g., a process with a clock signal in its sensitivity list becomes active on changes of the clock signal

All signal assignments occur at the END PROCESS statement in terms of simulation

The process is then suspended until there is an event (change in value) on a signal in the sensitivity list

VHDL Training


Combinational Logic

Can be described with concurrent statements

e.g. with-select-when, when-else, boolean equations, component instantiatons

Can be described with sequential statements

e.g. if-then-else, case-when

VHDL Training


Combinational Logic w/ Boolean Equations

Boolean Equations can be used in both concurrent and sequential signal assignment statements.

A 4-1 multiplexer is shown below

x <= (a AND NOT(s(1)) AND NOT(s(0))) OR

(b AND NOT(s(1)) AND s(0)) OR

(c AND s(1) AND NOT(s(0))) OR

(d AND s(1) AND s(0)) ;

ax

muxc

b

d

s

2

VHDL Training


Selective Signal Assignment:with-select-when

Assignment based on a selection signal

WHEN clauses must be mutually exclusive

Use a WHEN OTHERS to avoid latches

Only one reference to the signal, only one assignment operator (<=)

WITH selection_signal SELECT

signal_name <= value_1 WHEN value_1 of selection_signal,

value_2 WHEN value_2 of selection_signal,

...

value_n WHEN value_n of selection_signal,

value_x WHEN OTHERS;

VHDL Training


Combinational Logic w/ Selective Signal Assignment

The same 4-1 multiplexer is shown below

with s select

x <= a when “00” ,

b when “01” ,

c when “10” ,

d when others ;

VHDL Training


More on with-select-when

You can use a range of values

with int_value select

x <= a when 0 to 3,

b when 4 | 6 | 8 ,

c when 10 ,

d when others ;

VHDL Training


Conditional Signal Assignment:when-else

Signal is assigned a value based on conditions

Any simple expression can be a condition

Priority goes in order of appearance

Only one reference to the signal, only one assignment operator (<=)

Use a final ELSE to avoid latches

signal_name <= value_1 WHEN condition1 ELSE

value_2 WHEN condition2 ELSE

...

value_n WHEN conditionn ELSE

value_x ;

VHDL Training


Combinational Logic w/ Conditional Signal Assignment

The same 4-1 multiplexer is shown below

x <= a when (s = “00”) else

b when (s = “01”) else

c when (s = “10”) else

d ;

VHDL Training


Combinational Logic w/ Conditional Signal Assignment

The when conditions do not have to be mutually exclusive (as in with-select-when)

A priority encoder is shown below

j <= w when (a = „1‟) else

x when (b = „1‟) else

y when (c = „1‟) else

z when (d = „1‟) else

„0‟ ;

VHDL Training


Combinational Logic w/ Sequential Statements

Grouped together with Processes

Processes are concurrent with one another and with concurrent statements

Order of sequential statements does make a difference in synthesis

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Sequential Statementsif-then-else

Used to select a set of statements to be executed

Selection based on a boolean evaluation of a condition or set of conditions

IF condition(s) THEN

do something;

ELSIF condition_2 THEN -- optional

do something different;

ELSE -- optional

do something completely different;

END IF ;

VHDL Training


if-then-else

Absence of ELSE results in implicit memory

4-1 mux shown below

mux4_1: process (a, b, c, d, s)

begin

if s = “00” then x <= a ;

elsif s = “01” then x <= b ;

elsif s = “10” then x <= c ;

else x <= d ;

end process mux4_1 ;

VHDL Training


Sequentional Statements: Case-When

CASE selection_signal

WHEN value_1_of_selection_signal =>

(do something) -- set of statements 1

WHEN value_2_of_selection_signal =>

(do something) -- set of statements 2

...

WHEN value_N_of_selection_signal =>

(do something) -- set of statements N

WHEN OTHERS =>

(do something) -- default action

END CASE ;

VHDL Training


The CASE Statement: 4-1 Mux

ARCHITECTURE archdesign OF design IS

SIGNAL s: std_logic_vector(0 TO 1);

BEGIN

mux4_1: PROCESS (a,b,c,d,s)

BEGIN

CASE s IS

WHEN "00" => x <= a;

WHEN "01" => x <= b;

WHEN "10” => x <= c;

WHEN OTHERS => x <= d;

END CASE;

END PROCESS mux4_1;

END archdesign;

VHDL Training


Sequential Statements: An Example

mux: PROCESS (a, b, s)

BEGIN

IF s = '0' THEN

x <= a;

ELSE

x <= b;

END IF;

END PROCESS mux;

Note: logic within a process can be registered or combinatorial

Note: the order of the signals in the sensitivity list is not important

Note: the process mux is sensitive to signals a, b, and s; i.e., whenever one or more of those signals changes value, the statements inside of the process are executed

x(3 DOWNTO 0)

s

a(3 DOWNTO 0)

b(3 DOWNTO 0)

VHDL Training


Signal Assignment in ProcessesWhich Circuit is Correct?

PROCESS

BEGIN

WAIT UNTIL clock = '1' ; -- implied sensitivity list

b <= a;

c <= b;

END PROCESS ;

a

clock

c

a c

b

clock

VHDL Training


Signal Assignment in Processes (contd.)

Signals are not updated immediately. Rather, they are scheduled.

The signals are not updated until time advances (after the End Process statement)

Therefore, two registers will be synthesized

Note: In some instances, the use of concurrent statements outside the process may alleviate the problem, but this is not possible with registered logic.

VHDL Training


VARIABLES

When a concurrent signal assignment cannot be used, the previous problem can be avoided using a VARIABLE

Variables can only exist within a PROCESS, they cannot be used to communicate information between processes

Variables can be of any valid data type

The value assigned to a variable is available immediately

The variable assignment statement is used to assign values to variables, e.g.,

c := a AND b;

VHDL Training


Using Variables vs. Signals

Solution using a variable within a process:

-- assume a and c are signals defined elsewhere

PROCESS

VARIABLE b : std_logic ;

BEGIN

WAIT UNTIL clock = '1' ;

b := a ; -- this is immediate

c <= b ; -- this is scheduled

END PROCESS ;

VHDL Training


Native Operators Logical - defined for type bit, bit_vector, boolean*

AND, NAND

OR, NOR

XOR, XNOR

NOT

Relational - defined for types bit, bit_vector, integer*

= (equal to)

/= (not equal to)

< (less than)

<= (less than or equal to)

> (greater than)

>= (greater than or equal to)

* overloaded for std_logic, std_logic_vector

VHDL Training


Native Operators (contd.)

Unary Arithmetic - defined for type integer*

- (arithmetic negate)

Arithmetic - defined for type integer*

+ (addition), * (multiplication)

- (subtraction)

Concatenation - defined for strings

&

Note, a STRING is any sequence of characters, therefore a std_logic_vector is an example of a STRING

* overloaded for std_logic, std_logic_vector

VHDL Training


Overloaded Operators

In VHDL, the scope of all of the previous operators can be extended (or overloaded) to accept any type supported by the language, e.g.,-- assume a declaration of a 16-bit vector as

SIGNAL pc IS std_logic_vector(15 DOWNTO 0);

-- then a valid signal assignment is

pc <= pc + 3;

-- assuming the '+' operator has been overloaded to -

-- accept std_logic_vector and integer operands

The std_logic_1164 package defines overloaded logical operators (AND, OR, NOT, etc.,) for the std_logic and std_logic_vector types

In this training, you will learn to use overloaded operators, but not to define them

VHDL Training


Module Generation

In Warp release 4.0, a package called „std_arith‟ can be used to overload the arithmetic (+, -, etc.) and relational operators (=, /=, <, etc.,) for std_logic, std_logic_vector and integer types

Using this package causes adders, counters, comparators, etc., to automatically replace the operators in the design. These are optimized for the target architecture and synthesis goal (area/speed)

• This is known as module generation

VHDL Training


Using Tri-State Logic

ENTITY test_three IS

PORT( oe : in std_logic;

data : out std_logic_vector(0 to 7));

END test_three;

ARCHITECTURE archtest_three OF test_three IS

BEGIN

PROCESS (oe)

BEGIN

IF (oe = '1') THEN

data <= "01100100";

ELSE

data <= "ZZZZZZZZ";

END IF;

END PROCESS;

END archtest_three;

VHDL Training


Behavioral Don’t Cares

Warp uses explicit "don‟t care" conditions to produce optimal logic equations

IF (a = '1') AND (b = '1') THEN

x <= c;

ELSE

x <= '-';

END IF;

Produces the equation x = c

To assign don‟t cares in VHDL: mysig <= '-';

'X' means "unknown" and is not useful for synthesis

VHDL Training


Comparing Vectors to Strings-more on don't cares-

Comparing "1101" to "11-1" will return FALSE

Use std_match(a,"string")

Must include std_arith package

Example:

...

signal a : stdlogic_vector (1 to 4) ;

...

IF (std_match(a,"10-1")) THEN

x <= '1' ;

END IF ;

VHDL Training


Legal VHDL Identifiers

Letters, digits, and underscores only (first character must be a letter)

The last character cannot be an underscore

Two underscores in succession are not allowed

Using reserved words is not allowed

Examples

Legal

• tx_clk, Three_State_Enable, sel7D, HIT_1124

Not Legal

• _tx_clk, 8B10B, large#num, register, clk_

VHDL Training


Exercise #2: Architecture Declaration of a Comparator

The entity declaration is as follows:

LIBRARY ieee;




aeqb: OUT std_logic);

END compare;

Write an architecture that causes aeqb to be asserted when a is equal to b

Multiple solutions exist

aeqba(0 TO 3)

b(0 TO 3)

VHDL Training


Three possible solutions

Concurrent statement solution using a conditionalassignment:

Concurrent statement solution using booleanequations:

ARCHITECTURE archcompare OF compare IS

BEGIN

aeqb <= '1' WHEN a = b ELSE '0';

END archcompare;


BEGIN

aeqb <= NOT(

(a(0) XOR b(0)) OR

(a(1) XOR b(1)) OR

(a(2) XOR b(2)) OR

(a(3) XOR b(3)));

END archcompare;

VHDL Training


Three possible solutions (contd.)

Solution using a process with sequential statements:


BEGIN

comp: PROCESS (a, b)

BEGIN

IF a = b THEN

aeqb <= '1';

ELSE

aeqb <= '0';

END IF;

END PROCESS comp;

END archcompare;

aeqba(0 TO 3)

b(0 TO 3)

VHDL Training


Warp Tools: Galaxy

Menus

Project Management

Compiler Options

Control File

Compiling a Design

Error Tracking

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Menus

Project Menu - Creating, opening, saving projects

Files menu - Adding/deleting files from a project, file ordering, locking down pins, nodes, and FF locations

Info menu - Report file and control file viewing/editing, tool versions, source file statistics

Search menu - Allows searching of all VHDL and project files

Tools Menu - Launches Nova

Fonts Menu - Sets fonts for editor and error tracking

Help - On-line help

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Project Menu

VHDL Training


Files Menu

VHDL Training


Project Management

Galaxy project terminology

Creating a project

Adding/Deleting files from a project

File ordering

VHDL Training


Galaxy Project Terminology

Project - The VHDL design files, project file, synthesis control file, report file, and compiler outputs form the Galaxy “project”

Project File (.wpr) - A binary file that stores information regarding:

user environment (fonts etc.)

synthesis options

order of compilation for design files

library names and locations

Project Directory - The directory where the project file and source files reside

VHDL Training


A New Design

First step in a new design is to create a project

Project->New

Second step: Edit design files in the VHDL editor

Third step: Add design files to the project

Only .vhd files in the same directory as the project (.wpr) will be available

Files added/removed by Files->Add, Files -> Add all and Files->Remove

File ordering controlled by Files->Move Up and Files->Move Down

Top level file should be at the bottom of the list

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Compiler Options - Generic

Used for selecting

global synthesis and

reporting options

VHDL Training


Compiler Options - Generic

Optimization - effort level of compiler

“Exhaustive” is highest level of optimization

Run Options - error and message reporting

Using Quiet option speeds up compilation!

Goal

Global area or speed

Goal directives applied at lower levels have precedence

VHDL Training


Compiler Options - Device

Used to select target device,

device-specific synthesis

options, and timing

simulation outputs for

PLDs/CPLDs

VHDL Training


Compiler Options - Device

Selecting a target device

Output formats

JEDEC Normal - required for programmers

Post-JEDEC Sim

• VHDL and Verilog timing models for PLDs/CPLDs

VHDL Training


Compiling a design

Smart Compile

Compiles all project files in specified order

Knows if a file has been modified

Makes recompiling large designs easy

Compile Selected

Compiles only the selected file

Useful for code verification or to simply compile a file to a library

VHDL Training


Error Tracking

Galaxy has an integrated VHDL syntax error tracking/location mechanism

Highlighting an error and clicking on magnifying glass launches editor with cursor at location of error

Up and down arrows bring you to previous/next error

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Control File (.ctl)

Holds all synthesis directives for the design

Allows VHDL files to be device-independent

Automatically included in the project directory

Must have same base name as top-level file

Can edit file from Info->Control File

Supports simpler directive syntax

Supports use of wildcards

You can place a directive on all signals/entities

VHDL Training


VHDL Editor

Used for editing design files

Allows searching all project files

Provides VHDL Browser (VHDL templates)

Allows you to compile the file you are editing by using VHDL->Compile

A much improved editor will be available with release 4.2 (send in those registration cards)

VHDL Training


Report File

Two output options: detailed or concise (default)

Shows where UltraGenTM modules were synthesized

Shows timing, device resource utilization, and pinout.

VHDL Training


Back Annotation

Back Annotation means passing design information back to a previous design stage

Physical Information back annotation

• Pin numbers (schematic or control file)

• FLASH370 node numbers (control file)

Simulation value back annotation (schematic)

For control file, use Files->Annotate in Galaxy

VHDL Training


On-line Help and Documentation

On-line help is available from the Help menu in Galaxy

Shows how to create projects and compile designs

Describes the use of compiler options and synthesis directives

All Warp documentation is also available on-line (700+ pages!)

Files are in Adobe Acrobat format

User can install Acrobat reader from Warp CD

VHDL Training


Exercise #3:The Schematic

en(1)

en(2)

en(3)

en[0:3]

dir

en(0)

dir

gnd

dir

CY74FCT373T

CY74FCT245T

PLD

CY74FCT373T

CY74FCT373T

addr[1:0]

nvalid

nOE

LE

nOE

LE

nOE

LE

data[7:0]

status[7:0] control[7:0]

T/R

nOEgnd

VHDL Training


Exercise #3 Use Warp to compile the VHDL design description

of the truth table below:

addr nvalid

b"00" '0'

b"00" '1'

b"01" '0'

b"01" '1'

b"10" '0'

b"10" '1'

b"11" '0'

b"11" '1'

dir

L

H

H

H

L

H

H

H

en(0) en(1) en(2) en(3)

L L H L

H L H L

H H H L

H L H L

H L L L

H L H L

H L H H

H L H L

Write the Architecture for the given Entity (next)

Save design in file named “ex3.vhd”

VHDL Training


Exercise #3:The Entity Declaration

the entity declaration is as follows:

LIBRARY ieee;


ENTITY ex3 IS PORT (

addr: IN std_logic_vector(1 DOWNTO 0);

nvalid: IN std_logic;

en: BUFFER std_logic_vector(0 TO 3);

dir: OUT std_logic

);

END ex3;

en

diraddr

nvalid

PLD

VHDL Training


Exercise #3: Instructions

Synthesize the design using Warp

Click on the Galaxy icon in the Warp R4 group

Create a new project

Use the VHDL Editor to create your file

• click on new in the Edit portion of the Galaxy window

• optionally, open ex3.vhd

Select the Add... item from the Edit menu to add your .vhd file to the project.

Highlight the file and click on “set top”

Use the device menu to select the 22v10 as the target device

VHDL Training


Exercise #3Instructions (contd.)

Click on smart in the compile section of Galaxy

Correct any VHDL syntax errors

Click on the magnifying glass button to locate your error.

Save and re-compile until all errors are gone

Simulate the design using the Nova functional simulator

Select Nova from the Tools menu

Use Nova Quick Reference handout for simulation (please review first)

VHDL Training


Exercise #3: SolutionThe Architecture

The architecture is as follows:

ARCHITECTURE archex3 OF ex3 IS

BEGIN

en(0) <= '0' WHEN (addr = "00" AND nvalid = '0') ELSE '1';

en(1) <= (NOT addr(1)) AND addr(0) AND (NOT nvalid) ;

en(2) <= '0' WHEN (addr = "10" AND nvalid = '0') ELSE '1';

en(3) <= addr(1) AND addr(0) AND (NOT nvalid);

dir <= '0' WHEN (addr = "00" AND nvalid = '0') OR

(addr = "10" AND nvalid = '0') ELSE '1' ;

END archex3;

VHDL Training


Aggregates and Subscripts

Aggregate assignment concatenates signals together

Good for creating a bus from several inputs

Concatenation operator can be used as well

Same number of array elements on both sides of <=

tmp <= (a,b,c,d); tmp <= a & b & c & d;

Signals can be “pulled” from larger vectors

Good for grouping outputs as an “alias”

Sizes on both sides must match

rw <= ctrl(0); ce <= ctrl(1); oe <= ctrl(2);

highcount <= count(7 DOWNTO 4);

VHDL Training


Exercise #3: Alternate Solution

Using With/Select and aggregates


SIGNAL control : std_logic_vector(2 DOWNTO 0);

SIGNAL outputs : std_logic_vector(0 TO 4);

BEGIN

control <= addr & nvalid;

WITH control SELECT

outputs <= "00100" WHEN "000",

"10101" WHEN "001",

"11101" WHEN "010",

"10101" WHEN "011",

"10000" WHEN "100",

"10101" WHEN "101",

"10111" WHEN "110",

"10101" WHEN "111",

"-----" WHEN OTHERS;

en <= outputs(0 TO 3);

dir <= outputs(4);

END archex3;

VHDL Training


Designs that use Registers

There are two methods of utilizing and generating flip-flops:

Instantiate (place) a flip-flop or a component that contains a flip-flop

Use a process that is sensitive to a clock edge

VHDL Training


Instantiating a registered component

Example: Using LPM library

LIBRARY ieee;


USE WORK.lpmpkg.all ;

ENTITY registered IS PORT (

d, clk: IN std_logic;

q: OUT std_logic);

END registered;

ARCHITECTURE archregistered OF registered IS

BEGIN

flipflop: Mff generic map (lpm_width=>1,lpm_fftyp=>lpm_dff)

PORT MAP (data=>d,clock=>clk,enable=>one,q=>q);

END archregistered;

qd

clk

VHDL Training


Registers in Behavioral VHDL

Example: a D-type flip-flop

ENTITY registered IS PORT (

d, clk: IN std_logic;

q: OUT std_logic);

END registered;

ARCHITECTURE archregistered OF registered IS

BEGIN

flipflop: PROCESS (clk)

BEGIN

IF clk’EVENT AND clk = '1' THEN

q <= d;

END IF;

END PROCESS flipflop;

END archregistered;

VHDL Training


Registers in Behavioral VHDL

The synthesis compiler infers that a register is to be created for which signal q is the output because

The clock (clk) is in the sensitivity list

The construct, clk‟event and clk = „1‟, appears in the process

The clk‟event and clk = „1‟ statement implies that subsequent signal assignments occur on the rising-edge of the clock

The absence of an “else” clause in the “if-then” statement implies that if the clk‟event and clk = „1‟ condition is not fulfilled (i.e. not a rising-edge), qwill retain its value until the next assignment occurs (this is referred to as implied memory)

VHDL Training


A Registered Process (1) A 4-bit counter with synchronous reset

USE WORK.std_arith.ALL;

...

upcount: PROCESS (clk)

BEGIN

IF clk’EVENT AND clk= '1' THEN

IF reset = '1' THEN

count <= "0000"; -- or x"0" instead

ELSE

count <= count + 1;

END IF;

END IF;

END PROCESS upcount;

This process is only sensitive to changes in “clk”, i.e., it will become active only when the clock transitions

VHDL Training


A Registered Process (2) A 4-bit counter with asynchronous reset


...

upcount: PROCESS (clk, rst)

BEGIN

IF rst = '1' THEN

count <= x"0";

ELSIF clk’EVENT AND clk = '1' THEN

count <= count + 1;

END IF;


This process is sensitive to changes in both clk and rst, i.e., it will become active during clock or reset transitions.

VHDL Training


A Registered Process (3) A 4-bit loadable counter with asynchronous reset


...

upcount: PROCESS (clk, rst)

BEGIN

IF rst = '1' THEN

count <= x"0" ;

ELSIF clk’EVENT AND clk = '1' THEN

IF load = '1' THEN

count <= data;

ELSE

count <= count + 1;

END IF;

END IF;


VHDL Training


The WAIT statement

This is another method to activate a process

The WAIT statement is a sequential statement which suspends the execution of a process until the condition specified becomes valid (true) i.e., an implied sensitivity list, e.g.,

sync: PROCESS

BEGIN

WAIT UNTIL clock='1';

IF enable='1' THEN

q_out <= d_in;

ELSE

q_out <= '0';

END IF;

END PROCESS sync;

D

enable

d_in

clock

Qq_out

VHDL Training


Implicit memory

Signals in VHDL have a current value and may be scheduled for a future value

If the future value of a signal cannot be determined, a latch will be synthesized to preserve its current value

Advantages:

Simplifies the creation of memory in logic design

Disadvantages:

Can generate unwanted latches, e.g., when all of the options in a conditional sequential statement are not specified

VHDL Training


Implicit memory:Example of incomplete specification

Note: the incomplete specification of the IF...THEN... statement causes a latch to be synthesized to store the previous state of „c‟

ARCHITECTURE archincomplete OF

incomplete IS

BEGIN

im_mem: PROCESS (a,b)

BEGIN

IF a = '1' THEN c <= b;

END IF;

END PROCESS im_mem;

END archincomplete;

a

c

b

VHDL Training


Implicit memory:Example of complete specification

The conditional statement is fully specified, and this causes the process to synthesize to a single gate

ARCHITECTURE archcomplete OFcomplete IS

BEGIN

no_mem: PROCESS (a, b)

BEGIN

IF a = '1' THEN c <= b;

ELSE c <= '0';

END IF;

END PROCESS no_mem;

END archcomplete;

bc

a

VHDL Training


The rules to avoid implicit memory

To avoid the generation of unexpected latches

always terminate an IF...THEN... statement with an ELSE clause

cover all alternatives in a CASE statement

• define every alternative individually, or

• terminate the CASE statement with a WHEN OTHERS... clause, e.g.,CASE select IS

WHEN b"100" => key <= first;

x <= a AND b;

WHEN b"010" => key <= second;

WHEN b"001" => key <= third;

WHEN OTHERS => key <= none;

END CASE;

VHDL Training


Exercise #4

Making use of the previous examples, write an entity/architecture pair for the following design:

ENR

DIN

Q

REGISTER

4

4

Q

P

P=Q

COMPARATOR

4

COUNT

CLOCK

ENC

LD

DATA

ENR

RESET (sync)

ENC

LD

DIN

Q

COUNTER

RST

VHDL Training


Exercise #4: Instructions

The target device is a CY7C371I-110JC

Compile, synthesize, and simulate your solution with Warp

Create a new project for this exercise in the directory

Select New from the File menu in Galaxy

Hints:

Use 2 processes and a concurrent statement

Use code for register, counter, and comparator shown previously

Incorporate count enable logic in count process

VHDL Training


Exercise #4: SolutionLIBRARY ieee;



clock, reset, enc, enr, ld: IN std_logic;

data: IN std_logic_vector (3 DOWNTO 0);

count: BUFFER std_logic_vector(3 DOWNTO 0));

END ex4;

USE WORK.std_arith.ALL; -- for counter and ultragen


SIGNAL comp: std_logic;

SIGNAL regout: std_logic_vector (3 DOWNTO 0);

BEGIN

reg: PROCESS (clock)

BEGIN

IF clock'EVENT AND clock = '1' THEN

IF enr = '1' THEN

regout <= data;

END IF;

END IF;

END PROCESS reg;

VHDL Training


Exercise #4: Solution (contd.)

cntr: PROCESS (clock)

BEGIN


IF reset = '1' THEN

count <= "0000";

ELSIF ld = '1' THEN

count <= data;

ELSIF enc = '1' AND comp = '0' THEN

count <= count + 1;

END IF;

END IF;

END PROCESS cntr;

comp <= '1' WHEN regout = count ELSE '0';

END archex4;

VHDL Training


State machines

Moore Machines

A finite state machine in which the outputs change due to a change of state

Mealy Machines

A finite state machine in which the outputs can change asynchronously i.e., an input can cause an output to change immediately

VHDL Training


Moore machines

Outputs may change only with a change of state

Multiple implementations include:

Arbitrary state assignment

• outputs must be decoded from the state bits

• combinatorial decode

• registered decode

Specific state assignment

• outputs may be encoded within the state bits

• one-hot encoding

VHDL Training


Moore state machine implementations (1)

Outputs decoded from state bits

Combinatorial decode

• Outputs are decoded combinatorially from the current state

• outputscomb = f(present state)

Inputs LogicState

Registers

Output

Logic

Outputs

VHDL Training


Moore state machine implementations (2)

Outputs decoded from state bits

Registered decode

• Outputs are registered; decode of outputs is in parallel with decode of next state

• outputsreg = f(previous state, inputs)

Outputs

State

Registers

Output

Logic

Output

Registers

Inputs

Next

State

Logic

Current State

VHDL Training


State Output 1 Output 2 State Encoding

s1 0 0 00

s2 1 0 01

s3 0 1 10

Moore State Machine Implementations (3)

Outputs encoded within state bits

Example:

Note: Both bits of the state encoding are used as outputs

StateRegisters

OutputsInputs

Logic

VHDL Training


Example: A wait state generator

State diagram:

RESET

(async)

IDLE

00

REQ

ACK

10

RETRY

01

REQ

PWAIT

PWAIT

retry_out='1'

ack_out='1'

VHDL Training


Example: The entity declaration

The entity declaration remains essentially the same for each implementation (except for the entity name)e.g.,

LIBRARY ieee;


ENTITY moore1 IS PORT (

clock, reset: IN std_logic;

req, pwait: IN std_logic;

retry_out, ack_out: OUT std_logic);

END moore1;

VHDL Training


Example: Solution 1

Combinatorial outputs decoded from the state bits

ARCHITECTURE archmoore1 OF moore1 IS

TYPE fsm_states IS (idle, retry, ack);

SIGNAL wait_gen : fsm_states;

BEGIN

fsm: PROCESS (clock, reset)

BEGIN

IF reset = '1' THEN

wait_gen <= idle; -- asynchronous reset

ELSIF clock'EVENT AND clock = '1' THEN

CASE wait_gen IS

WHEN idle => IF req = '0' THEN wait_gen <= retry;

ELSE wait_gen <= idle;

END IF;

WHEN retry => IF pwait='1' THEN wait_gen <= ack;

ELSE wait_gen <= retry;

END IF;

VHDL Training


Example: Solution 1 (contd.)

WHEN ack => wait_gen <= idle;

WHEN OTHERS => wait_gen <= idle;

END CASE;

END IF;

END PROCESS fsm;

retry_out <= '1' WHEN (wait_gen = retry) ELSE '0';

ack_out <= '1' WHEN (wait_gen = ack) ELSE '0';

END archmoore1;

VHDL Training


Example: Solution 2 Registered outputs decoded from the state bits



SIGNAL wait_gen: fsm_states;

BEGIN


BEGIN

IF reset = '1' THEN

wait_gen <= idle;

retry_out <= '0';

ack_out <= '0';


retry_out <= '0'; -- a default assignment, could do ack_out too

CASE wait_gen IS


retry_out <= '1';

ack_out <= '0';


ack_out <= '0';

END IF;

VHDL Training


Example: Solution 2 (contd.)WHEN retry => IF pwait = '1' THEN wait_gen <= ack;

ack_out <= '1';


retry_out <= '1';

ack_out <= '0';

END IF;


ack_out <= '0';


ack_out <= '0'; -- note must define what

-- happens to ‘ack_out’

END CASE; -- here or a latch will

END IF; -- be synthesized to

END PROCESS fsm; -- preserve it’s current

END archmoore2; -- state

VHDL Training


Example: Solution 3

Outputs encoded within the state bits


SIGNAL wait_gen: std_logic_vector(1 DOWNTO 0);

CONSTANT idle: std_logic_vector(1 DOWNTO 0) := "00";

CONSTANT retry: std_logic_vector(1 DOWNTO 0) := "01";

CONSTANT ack: std_logic_vector(1 DOWNTO 0) := "10";

BEGIN


BEGIN

IF reset = '1' THEN

wait_gen <= idle;


CASE wait_gen IS



END IF;

VHDL Training


Example: Solution 3 (contd.)

WHEN retry => IF pwait = '1' THEN wait_gen <= ack;


END IF;



END CASE;

END IF;

END PROCESS fsm;

retry_out <= wait_gen(0);

ack_out <= wait_gen(1);

END archmoore3;

VHDL Training


State Machines: One-hot Encoding

One state per flip-flop

in FPGA-type architectures

• reduces the next state logic

• requires fewer levels of logic cells

• enables high-speed state machines (> 100MHz)

in CPLDs

• reduces the number of product terms

• can eliminate „expander‟ product terms (i.e. reduce delays, and increase operating speed)

• but, uses more macrocells

VHDL Training


Example: One-hot-one Solution



ATTRIBUTE state_encoding OF fsm_states:TYPE IS one_hot_one;


BEGIN


BEGIN

IF reset = '1' THEN

wait_gen <= idle;


CASE wait_gen IS



END IF;

VHDL Training


Example: One-hot-one Solution (contd.)

WHEN retry => IF pwait = '1' THEN wait_gen <= ack;


END IF;



END CASE;

END IF;

END PROCESS fsm;

-- Assign state outputs

retry_out <= '1' WHEN (wait_gen = retry) ELSE '0';

ack_out <= '1' WHEN (wait_gen = ack) ELSE '0';

END archmoore4;

VHDL Training


Moore Machines: Summary Outputs decoded from the state bits

• flexibility during the design process

• using enumerated types allows automatic state assignment during compilation

Outputs encoded within the state bits

• manual state assignment using constants

• the state registers and the outputs are merged

• reduces the number of registers

• but, may require more product terms

One-Hot encoding

• reduces next state decode logic

• high speed operation

• but, uses more registers

VHDL Training


Mealy Machines

Outputs may change with a change of state OR with a change of inputs

Mealy outputs are non-registered because they are functions of the present inputs

Inputs

State

Registers

Logic Outputs

VHDL Training


Example: The Wait State Generator

State diagram:

PWAIT

RESET

(async)

IDLE

0

RETRY

1

REQ

PWAIT

if, ENABLE='0'

RETRY_OUT='1'

REQ

VHDL Training


Example: Mealy Machine SolutionARCHITECTURE archmealy1 OF mealy1 IS

TYPE fsm_states IS (idle, retry);


BEGIN


BEGIN

IF reset = '1' THEN

wait_gen <= idle;


CASE wait_gen IS



END IF;

WHEN retry => IF pwait = '1' THEN wait_gen <= idle;


END IF;


END CASE;

END IF;

END PROCESS fsm;

retry_out <= '1' WHEN (wait_gen = retry AND enable='0') ELSE '0';

END archmealy1;

VHDL Training


Exercise #5

Design a state machine to implement the function shown below:

hold extendsamplePOS

POS

RESET

RESET

if, busy='0'

track='1'clear='0'

track='1'

VHDL Training


Exercise #5: Solution

LIBRARY ieee;



clock, pos,

busy, reset: IN std_logic;

clear, track: OUT std_logic);

END ex5;


TYPE states IS (hold, sample, extend);

ATTRIBUTE state_encoding OF states:TYPE IS one_hot_one;

SIGNAL fsm: states;

BEGIN

clear <= '0' WHEN fsm = sample ELSE '1';

track <= '1' WHEN (fsm = sample) OR

(fsm = extend AND busy = '0') ELSE '0';

VHDL Training


Exercise #5: Solution (contd.)

sync: PROCESS (clock)

BEGIN


IF reset = '1' THEN

fsm <= hold; -- synchronous reset

ELSE

CASE fsm IS

WHEN hold => IF pos = '0'

THEN fsm <= sample;

ELSE fsm <= hold;

END IF;

WHEN sample => fsm <= extend;

WHEN extend => fsm <= hold;

WHEN OTHERS => fsm <= hold;

END CASE;

END IF; -- reset = '1'

END IF; -- clk'EVENT AND clk = '1'

END PROCESS sync;

END archex5;

VHDL Training


Hierarchical design methodology

Advantages:

Allows the re-use of common building blocks

Components (VHDL models or schematic symbols) can be created, tested and held for later use

Smaller components can be more easily integrated with other blocks

Designs are more readable

Designs are more portable

The design task can be split among several members of a team

Documents

PROGRAMMABLE LOGIC DESIGN WITH VHDL · PDF filePROGRAMMABLE LOGIC DESIGN WITH VHDL. VHDL Training ©1997 Cypress Semiconductor, rev 2.5.3 2 Why Use VHDL? Quick Time-to-Market ... tens