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Prof. Brian L. Evans
PhD StudentsKarl Nieman, Marcel Nassar, and Jing Lin
Department of Electrical and Computer Engineering The University of Texas at Austin
Austin, TX
May 6, 2013
Sponsored by National Instruments Academic Lead User Program
FPGA Implementation of a Message-Passing OFDM Receiver for Impulsive Noise Channels
2
Outline• Part I
• Smart grid communications
• Impulsive noise mitigation
• System design and implementation
• Part II• Demonstration
• Part III• Feedback for NI• Next Steps
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IEEE Signal Processing MagazineSpecial Issue on Signal Processing Techniques for the Smart Grid, September 2012.
Background | System Design and Implementation | Demo | Conclusion
3
Local utility
MV-LV transformer
Smart meters
Data concentrator
Smart Grid Communications
Home area data networksconnect appliances, EV charger and smart meter via powerline or wireless links
Smart meter communicationsbetween smart meters and data concentrator via powerline or wireless links
Communication backhaulcarries traffic between concentrator and utility on wired or wireless links
Low voltage (LV)under 1 kV
Medium Voltage (MV)1 kV – 33 kV
Background | System Design and Implementation | Demo | Conclusion
4
• Uses orthogonal frequency division multiplexing (OFDM)
• Communication challenges
o Channel distortiono Non-Gaussian, impulsive noise
Powerline Communications (PLC)Categories Band Bit Rates Coverage Enables Standards
Narrowband 3-500 kHz
up to 800 kbps
Multi-kilometer
Smart meter communication
• (ITU) PRIME, G3• ITU-T G.hnem• IEEE P1901.2
Broadband 1.8-250 MHz
up to200 Mbps <1500 m Home area
data networks•HomePlug•ITU-T G.hn•IEEE P1901
Background | System Design and Implementation | Demo | Conclusion
5
Impulsive Noise in PLC
Outdoor medium-voltage line (St. Louis, MO)
Cyclostationary noise becomes impulsive after interleaving
Interleave
Indoor low-voltage line (UT Campus)
= 1 MHz
Background | System Design and Implementation | Demo | Conclusion
6
Impulsive Noise in OFDM Systems
• FFT spreads received impulsive noise across all FFT bins
• SNR of each FFT bin is decreased• Receiver communication performance degrades
IFFT Filter + FFTEqualizer
and detectorVector
of symbolamplitudes(complex)
Channel
Receiver𝐬 𝐲
Gaussian () + ImpulsiveNoise ()
Background | System Design and Implementation | Demo | Conclusion
Impulsive Noise Mitigation (Denoising)
• FFT bins (tones)• Transmitter null tones have zero power• Received null tones contain noise
• Impulsive noise estimation• Exploit sparse structure of null tones• is over complete dictionary• is sparse vector• is complex Gaussian ()
7
IFFT Filter + + FFTEqualizer
and detector
Impulsive noise
estimation
Gaussian () + ImpulsiveNoise ()
Vectorof symbolamplitudes(complex)
+
-
Channel
Receiver
Ω is set of null tones (i.e. ) is DFT matrix
𝐬 𝐲
�̂�
||
¿
+¿
Background | System Design and Implementation | Demo | Conclusion
Approximate Message Passing (AMP)
= number of null tones
= FFT size
8
• Reconstruct time-domainnoise from frequency-domain null tones
• Iterate until convergence
• Algorithm consists of:• Mostly scalar arithmetic• FFT/IFFTs• Exponential
• Targeted at G3-PLC signaling structure
Background | System Design and Implementation | Demo | Conclusion
Project GoalsFrom theory to implementation:• Understand computational requirements• Determine real-time constraints in target application• Find feasible solution
Steps involved:• Develop floating-point model and simulator• Convert to fixed-point data and arithmetic• Hardware/software partitioning• Implementation
9Background | System Design and Implementation | Demo | Conclusion
Mapping to Fixed-Point• Variables sized using MATLAB Fixed-Point Toolbox• Most variables sized to 16-bit wordlengths
10
sizing for using graphical tool
Background | System Design and Implementation | Demo | Conclusion
AMP-Enhanced OFDM Testbed
11
RT controller
LabVIEW RT
data symbol generation
FlexRIO FPGA Module 1 (G3TX)
LabVIEW DSP Design Module
data and reference
symbol interleave reference
symbol LUT
43.2 kSps
8.6 kSps
zero padding
(null tones)
generatecomplex
conjugate pair
103.6 kSps
256 IFFT w/ 22 CP insertion
368.3 kSps
NI 5781
16-bit DAC 10 MSps
RT controller
LabVIEW RT
BER/SNR calculation w/ and w/o AMP
FlexRIO FPGA Module 2 (G3RX)
LabVIEW DSP Design Module
NI 5781
14-bit ADCsample
rate conversion
10 MSps 400 kSps
time and frequency
offset correction
400 kSps
256 FFT w/ 22 CP removal,
noise injection
368.3 kSps
FlexRIO FPGA Module 3 (AMPEQ)
LabVIEW DSP Design Module
null tone and active
tone separation
184.2 kSps
51.8 kSps channel estimation/
ZFequalizationAMP noise
estimate
Subtract noise
estimate from active
tones
data and reference
symbol de- interleave
51.8 kSps
8.6 kSps
Host Computer
LabVIEW
43.1 kSps
43.1 kSps
sample rate
conversion400 kSps 51.8 kSps
256 FFT, tone select 51.8 kSps368.3 kSps
testbench control/data visualization
diffe
renti
al M
CX p
air
TX Chassis RX Chassis1 × PXIe-10821 × PXIe-81331 × PXIe-7965R1 × NI-5781 FAM
differential MCX pair(quadrature component = 0)
1 × PXIe-10821 × PXIe-81332 × PXIe-7965R1 × NI-5781 FAM
Background | System Design and Implementation | Demo | Conclusion
12
AMPEQ.lvdsp(first half)
Background | System Design and Implementation | Demo | Conclusion
(second half)
Results• System implemented using G3-PLC signaling structure
MHz, (real-valued), active tones
• Receiver w/ AMP was mapped across two FPGAs• ‘G3RX’ – Downsampling, IFFT, time/frequency offset correction• ‘AMPEQ’ – AMP algorithm, equalization, and detection
13Background | System Design and Implementation | Demo | Conclusion
Utilization Trans. Rec. AMP+Eq
FPGA 1 2 3
total slices 32.6% 64.0% 94.2%
slice reg. 15.8% 39.3% 59.0%
slice LUTs 17.6% 42.4% 71.4%
DSP48s 2.0% 7.3% 27.3%
blockRAMs 7.8% 18.4% 29.1%
Received QPSK constellation at equalizer output
conventional receiver with AMP
Resource Utilization
Conclusions
Background | System Design and Implementation | Demo | Conclusion 16
• Used LabVIEW DSP Designer to implement real-time PLC OFDM impulsive noise mitigation test system
• Achieved measured performance of up to 8 dB of impulsive noise mitigation across typical PLC SNR range
• Paper summarizing project submitted to 2013 IEEE Asilomar Conference on Signals, Systems and Computers:http://users.ece.utexas.edu/~bevans/papers/2013/fpgaReceiver
(in progress) publishing LV project and simulations