Click here to load reader
Upload
chgk16
View
83
Download
1
Tags:
Embed Size (px)
DESCRIPTION
Xilinx Product Guide
Citation preview
Product Selection Guides
table of contents february 2013
1Important: Verify all data in this document with the device data sheets found at www.xilinx.com
Zynq-7000 All Programmable SoCs ............................................................................................. 2
7 Series FPGAs ................................................................................................................................................ 3
Virtex-6 FPGAs .............................................................................................................................................. 6
Spartan-6 FPGAs ........................................................................................................................................ 7
Virtex-5 FPGAs ............................................................................................................................................... 8
CPLD Products ............................................................................................................................................ 10
Configuration Storage Solutions ........................................................................................................ 11
ISE Design Suite ........................................................................................................................................13
Aerospace & Defense ................................................................................................................................14
Automotive ...................................................................................................................................................... 23
Xilinx Boards and Kits ............................................................................................................................. 28
Xilinx IP Cores, Reference Designs, and Instructor Led Training Courses ............ 31
Xilinx Productivity Advantage ............................................................................................................. 32
Zynq-7000 all Programmable socs
2Important: Verify all data in this document with the device data sheets found at www.xilinx.com
Device NameP t N b XC7Z045XC7Z010 XC7Z020 XC7Z030
Zynq-7000 All Programmable SoC5407-Z 0307-Z0207-Z0107-Z
Part NumberProcessor Core
Processor Extensions
Maximum Frequency
L1 Cache
L2 Cache
On-Chip Memory
External Memory Support (1)Processing System
Dual ARM Cortex-A9 MPCore with CoreSight
NEON & Single / Double Precision Floating Point for each processor
32 KB Instruction, 32 KB Data per processor
512 KB
256 KB
DDR3, DDR2, LPDDR2
zHG 1zHM 008
XC7Z045XC7Z010 XC7Z020 XC7Z030
y pp
External Static Memory Support (1)
DMA Channels
Peripherals
Peripherals w/ built-in DMA(1)
Security(2)
Processing System to Programmable Logic Interface Ports (Primary Interfaces & Interrupts Only)
2x AXI 32b Master, 2x AXI 32b Slave,4x AXI 64b/32b Memory
AXI 64b ACP16 I t t
2x Quad-SPI, NAND, NOR
2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO
8 (4 dedicated to Programmable Logic)
2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO
AES and SHA 256b Decryption and Authentication for Secure Boot
Xilinx 7 Series Programmable Logic Equivalent
Programmable Logic Cells (Approximate ASIC Gates(3))
Look-Up Tables (LUTs)
Flip-Flops
Extensible Block RAM (# 36 Kb Blocks)
Programmable DSP Slices (18x25 MACCs)
Peak DSP Performance (Symmetric FIR)
00900402208
sCAMG 433,1sCAMG 395sCAMG 672sCAMG 001
002,734002,751004,601002,53
)545( BK 081,2)562( BK 060,1
16 Interrupts
Programmable Logic
AGPF 7-xetniKAGPF 7-xetniKAGPF 7-xitrAAGPF 7-xitrA
28K Logic Cells (~430K) 85K Logic Cells (~1.3M) 125K Logic Cells (~1.9M)
240 KB (60) 560 KB (140)
002,35006,71
350K Logic Cells (~5.2M)
006,812006,87
( y )
PCI Express (Root Complex or Endpoint)
Agile Mixed Signal (AMS) / XADC(1)
Security(2)
Commercial (0C to 85C)
Extended (0C to 100C)
Industrial (-40C to 100C)
Package Type(4) CLG225(1) CLG400 CLG400 CLG484 FBG484 FBG676 FFG676 FBG676 FFG676 FFG900
Size (mm) 13x13 17x17 17x17 19x19 23x23 27x27 27x27 27x27 27x27 31x31
8x 2neG4x 2neG
2x 12 bit, MSPS ADCs with up to 17 Differential Inputs
AES and SHA 256b Decryption and Authentication for Secure Programmable Logic Configuration
Speed Grades
-1
-2, -3
-1, -2
Size (mm) 13x13 17x17 17x17 19x19 23x23 27x27 27x27 27x27 27x27 31x31
Pitch (mm) 0.8 0.8 0.8 0.8 1.0 1.0 1.0 1.0 1.0 1.0
Processing System User I/Os (excludes DDR dedicated I/Os)(5) 32 54 54 54 54 54 54 54 54 54
Multi-Standards and Multi-Voltage SelectIOTM Interfaces(1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V)
54 100 125 200 100 100 100 100 100 212
Multi-Standards and Multi-Voltage High Performance SelectIO Interfaces(1.2V, 1.35V, 1.5V, 1.8V) 63 150 150 150 150 150
Serial Transceivers 4 4 4 8 8 16
Packages
Maximum Transceiver Speed (Speed Grade Dependant) N/A N/A N/A N/A 6.6 Gb/s 6.6 Gb/s 12.5 Gb/s 6.6 Gb/s 12.5 Gb/s 12.5 Gb/s
XMP087 (v1.6.1)
Notes: 1. Z-7010 in CLG225 has restrictions on PS peripherals, Memory interfaces and I/Os. Please refer to the Technical Reference Manual for more details.
2. Security block is shared by the Processing System and the Programmable Logic.
3. Equivalent ASIC gate count is dependent of the function implemented. The assumption is 1 Logic Cell = ~15 ASIC Gates.
4. Devices in the same package are pin-to-pin compatible. FBG676 and FFG676 are also pin-to-pin compatible.
5. Static memory interface combined with the usage of many peripherals could require more than 54 I/Os. In that case, the designer can use the Programmable Logic SelectIO interface.
6. Preliminary product information. Subject to change. Please contact your Xilinx representative for the latest information.6. Preliminary product information. Subject to change. Please contact your Xilinx representative for the latest information.
Virtex-7 fPgas
3Important: Verify all data in this document with the device data sheets found at www.xilinx.com
XC7V585T XC7V2000T XC7VX330T XC7VX415T XC7VX485T XC7VX550T XC7VX690T XC7VX980T XC7VX1140T XC7VH580T XC7VH870T
XCE7V585T XCE7V2000T XCE7VX330T XCE7VX415T XCE7VX485T XCE7VX550T XCE7VX690T XCE7VX980T XCE7VX1140T 91,050 305,400 51,000 64,400 75,900 86,600 108,300 153,000 178,000 90,700 136,900
582,720 1,954,560 326,400 412,160 485,760 554,240 693,120 979,200 1,139,200 580,480 876,160
728,400 2,443,200 408,000 515,200 607,200 692,800 866,400 1,224,000 1,424,000 725,600 1,095,200
6,938 21,550 4,388 6,525 8,175 8,725 10,888 13,838 17,700 8,850 13,275
795 1,292 750 880 1,030 1,180 1,470 1,500 1,880 940 1,410
28,620 46,512 27,000 31,680 37,080 42,480 52,920 54,000 67,680 33,840 50,760
8121428102024121414281gnikcolC
850 1,200 700 600 700 600 1,000 900 1,100 600 650
408 576 336 288 336 288 480 432 528 288 312
1,260 2,160 1,120 2,160 2,800 2,880 3,600 3,600 3,360 1,680 2,520
3 4 4
2 2 2 3 3 4 2 3
1 1 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 1 1
36 36 56
28 48 80 80 72 96 48 72
GTZ 28.05 Gb/s Transceivers 8 16
-1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2
-2L, -3 -2L, -2G -2L, -3 -2L, -3 -2L, -3 -2L, -3 -2L, -3 -2L -2L, -2G -2L, -2G -2L, -2G
-1, -2 -1 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1 -1
Package(5) Area
Flip chip, fine pitch BGA (1.0 mm ball spacing)
FFG1157 35 x 35 mm 0, 600 (20, 0) 0, 600 (0, 20) 0, 600 (0, 20) 0, 600 (20, 0) 0, 600 (0, 20)
FFG1761 42.5 x 42.5 mm 100, 750 (36, 0) 50, 650 (0, 28) 0, 700 (28, 0) 0, 850 (0, 36)
FHG1761 45 x 45 mm 0 850 (36 0)
Part Number
EasyPath Cost Reduction Solutions(1)
FootprintCompatible
LogicResources
Slices
Logic Cells
CLB Flip-Flops
MemoryResources
Maximum Distributed RAM (Kb)
Block RAM/FIFO w/ ECC (36 Kb each)
Total Block RAM (Kb)
CMTs (1 MMCM + 1 PLL)
I/O ResourcesMaximum Single-Ended I/O
Maximum Differential I/O Pairs
GTH 13.1 Gb/s Transceivers(3)
Speed Grades
Commercial
Extended(4)
Industrial
Embedded IP Resources
DSP48E1 Slices
PCI Express Gen2
PCI Express Gen3
Agile Mixed Signal (AMS) / XADC
GTX 12.5 Gb/s Transceivers(2)Configuration AES / HMAC Blocks
Virtex-7 FPGAsOptimized for Highest System Performance and Capacity
)V0.1()V9.0 ,V0.1()V9.0 ,V0.1(
Available User I/O: 3.3V SelectI/OTM Pins, 1.8V SelectI/O Pins (GTX, GTH Transceivers) 1.8V SelectIO Pins (GTH, GTZ)
FHG1761 45 x 45 mm 0, 850 (36, 0)
)0 ,61( 0021 ,0mm 54 x 545291GLF
)84 ,0( 053 ,0)84 ,0( 053 ,0)0 ,84( 053 ,0)84 ,0( 053 ,0mm 53 x 538511GFF
FFG1926 45 x 45 mm 0, 720 (0, 64) 0, 720 (0, 64)
FLG1926 45 x 45 mm 0, 720 (0, 64)
)08 ,0( 006 ,0)08 ,0( 006 ,0)0 ,65( 006 ,0)84 ,0( 006 ,0mm 54 x 547291GFF
FFG1928 45 x 45 mm 0, 480 (0, 72)
FLG1928 45 x 45 mm 0, 480 (0, 96)
FFG1930 45 x 45 mm 0, 700 (24, 0) 0, 1000 (0, 24) 0, 900 (0, 24)
FLG1930 45 x 45 mm 0, 1100 (0, 24)
Ceramic flip chip, fine pitch BGA (1.0 mm ball spacing)
HCG1155 35 x 35 mm 400 (24, 8)
HCG1931 45 x 45 mm 600 (48, 8) 650 (48, 8)
HCG1932 45 x 45 mm 300 (48, 8) 300 (72, 16)
XMP084 (v4.6)Notes: 1. EasyPath solutions provide a fast and conversion-free path for cost reduction.
2. 12.5 Gb/s support in "-3E", "-2GE" speed/temperature grade; 10.3125 Gb/s support in "2C", "-2LE", and "-2I" speed grade.3. 13.1 Gb/s support in "-3E". "-2GE" speed grade; 11.3 Gb/s support in "2C" , "-2LE" and "-2I" speed/temperature grades.4. -2G only applies to Stacked Silicon Interconnect devices and supports 12.5G GTX, 13.1G GTH, 28.05G GTZ with -2 fabric.5. Leaded package options ("FFxxxx"/"FLxxxx"/"FHxxxx"/"HCxxxx") available for all packages.
Compatible
FootprintCompatible
FootprintCompatible
FootprintCompatible
Kintex-7 fPgas
4Important: Verify all data in this document with the device data sheets found at www.xilinx.com
XC7K70T XC7K160T XC7K325T XC7K355T XC7K410T XC7K420T XC7K480T
T084K7ECXT024K7ECXT014K7ECXT553K7ECX
056,47051,56055,36056,55059,05053,52052,01
65,600 162,240 326,080 356,160 406,720 416,960 477,760
82,000 202,800 407,600 445,200 508,400 521,200 597,200
887,6839,5366,5880,5000,4881,2838
559538597517544523531
083,43060,03026,82047,52020,61007,11068,4
880160186secruoseR kcolC
004004005003005004003
291291042441042291441
029,1086,1045,1044,1048006042
1111111
1111111
Configuration AES / HMAC Blocks 1111111
232361426188
2- ,1-2- ,1-2- ,1-2- ,1-2- ,1-2- ,1-2- ,1-
3- ,L2-3- ,L2-3- ,L2-3- ,L2-3- ,L2-3- ,L2-3- ,L2-
2- ,1-2- ,1-2- ,1-2- ,1-2- ,1-2- ,1-2- ,1-
Package(4) Dimensions (mm)
FBG484 23 x 23 185, 100 (4) 185, 100 (4)
)8( 051 ,052)8( 051 ,052)8( 051 ,052)8( 001 ,00272 x 72676GBF
)8( 051 ,052)8( 051 ,052)8( 051 ,05272 x 72676GFF
FBG900 31 x 31 )61( 051 ,053)61( 051 ,053
FFG900 31 x 31 )61( 051 ,053)61( 051 ,053
FFG901 31 x 31 )82( 0 ,083)82( 0 ,083)42( 0 ,003
FFG1156 35 x 35 400, 0 (32) 400, 0 (32)
XMP085 (v3.5)FBG 1.0mm Lidless flip-chip; FFG: 1.0mm Flip-chip fine-pitch
Notes: 1. EasyPath solutions provide a fast and conversion-free path for cost reduction.
4. Preliminary product information, subject to change. Please contact your Xilinx representative for the latest information.
FootprintCompatible
FootprintCompatible
2. Hard block supports PCI Express Base 2.1 specification at Gen1 and Gen2 data rates. Gen3 supported with soft IP.3. Leaded package options ("FBxxx" or "FFxxx") available for the following Kintex-7 devices: XC7K160T, XC7K325T, XC7K355T, XC7K410T, XC7K420T, XC7K480T
Speed Grades
Commercial
Extended
Industrial
Available User I/O: 3.3V SelectIOTM Pins, 1.8V SelectIO Pins (GTX Transceivers)
EmbeddedHard IP
Resources
DSP48E1 Slices
PCI Express(2)
Agile Mixed Signal (AMS) / XADC
GTX 12.5 Gb/s Transceivers
MemoryResources
Maximum Distributed RAM (Kbits)
Block RAM/FIFO w/ ECC (36Kbits each)
Total Block RAM (Kbits)
CMTs (1 MMCM + 1 PLL)
I/O ResourcesMaximum Single-Ended I/O
Maximum Differential I/O Pairs
Kintex-7 FPGAsOptimized for Best Price-Performance(1.0V, 0.9V)
Part Number
EasyPath Cost Reduction Solutions(1)
Logic Resources
Slices
Logic Cells
CLB Flip-Flops
artix-7 fPgas
5Important: Verify all data in this document with the device data sheets found at www.xilinx.com
XC7A20SL XC7A35SL XC7A50SL XC7A75SL XC7A20SLT XC7A35SLT XC7A50SLT XC7A75SLT XC7A100T XC7A200T
2,500 5,142 8,200 11,194 2,500 5,142 8,200 11,194 15,850 33,650
16,000 32,909 52,480 71,642 16,000 32,909 52,480 71,642 101,440 215,360
20,000 41,136 65,600 89,552 20,000 41,136 65,600 89,552 126,800 269,200
208 453 688 974 208 453 688 974 1,188 2,888
563531521595603521595603
1,080 2,340 3,420 4,500 1,080 2,340 3,420 4,500 4,860 13,140
Clock Resources 3 3 4 4 0164433
005003003003612612003003612612
0424412727454527274545
0470420420810210604208102106
111111
1111111111
1 1 1 1 111111
6188844
-1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2
-2L, -3 -2L, -3 -2L, -3 -2L, -3 -2L, -3 -2L, -3 -2L, -3 -2L, -3 -2L, -3 -2L, -3
-1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2 -1, -2
Package(2), (3) Dimensions (mm)
25 ,8425 ,8401 x 01632GPC
Speed Grades
Commercial
Extended
Industrial
Available User I/O: 3.3V SelectI/O HR I/O, 3.3V SelectI/O HD I/O Pins (GTP Transceivers) Available User I/O: 3.3V SelectI/O HR I/O Pins (GTP Transceivers)
EmbeddedHard IP
Resources
DSP48E1 Slices
PCI Express(1)
Agile Mixed Signal (AMS) / XADC
Configuration AES / HMAC Blocks
GTP Transceivers (6.6 Gb/s Max Rate)
Artix-7 FPGAsOptimized for Lowest Cost and Lowest Power Applications(1.0V, 0.9V)
I/O ResourcesMaximum Single-Ended I/O
Maximum Differential I/O Pairs
Part Number
Logic Resources
Slices
Logic Cells
CLB Flip-Flops
MemoryResources
Maximum Distributed RAM (Kbits)
Block RAM/FIFO w/ ECC (36Kbits each)
Total Block RAM (Kbits)
CMTs (1 MMCM + 1 PLL)
sAGPF TLS 7-xitrAsAGPF LS 7-xitrAAdvance Advance
Artix-7 T FPGAs
801 ,801801 ,80151 x 51523GSC
651 ,441651 ,44191 x 91484GSC
01 x 01732GPC 48, 52 (1) 48, 52 (1)
51 x 51623GSC 108, 77 (4) 108, 77 (4) 108, 77 (4) 108, 77 (4)
91 x 91584GSC 108, 108 (4) 108, 108 (4) 126, 108 (6) 126, 108 (6)
72 x 72776GGF 144, 156 (8) 144, 156 (8)
51 x 51423GSC 210 (0)
71 x 71652GTF 170 (0)
91 x 91484GBS 285 (4)
32 x 32484GGF 285 (4)
32 x 32484GBF 285 (4)
72 x 72676GGF 300 (8)
72 x 72676GBF 400 (8)
53 x 536511GFF 500 (16)
XMP086 (v4.2)CPG: 0.5mm Wire-bond chip-scale; CSG: 0.8mm Wire-bond chip-scale; FTG: 1.0mm Wire-bond fine-pitch; SBG: 0.8mm Lidless flip-chip; FGG: 1.0mm Wire-bond fine-pitch; FBG 1.0mm Lidless flip-chip; FFG: 1.0mm Flip-chip fine-pitch
Notes:2. Leaded package option available for all packages.3. Device migration is available within the Artix-7 family for like packages but is not supported between other 7 series families.
FootprintCompatible
FootprintCompatible
1. Supports PCI Express Base 2.1 specification at Gen1 and Gen2 data rates.
Virtex-6 fPgas
6Important: Verify all data in this document with the device data sheets found at www.xilinx.com
;&9/;7 ;&9/;7 ;&9/;7 ;&9/;7 ;&9/;7 ;&9/;7 ;&9/; ;&96;7 ;&96;7 ;&9+;7 ;&9+;7 ;&9+;7 ;&9+;7;&(9/;7 ;&(9/;7 ;&(9/;7 ;&(9/;7 ;&(9/;7 ;&(9/;7 ;&(9/; ;&(96;7 ;&(96;7 ;&(9+;7 ;&(9+;7 ;&(9+;7 ;&(9+;7 &ORFN5HVRXUFHV / / / / / / / / / / / / / / / / / / &RQILJXUDWLRQ &RQILJXUDWLRQ 0HPRU\ 0E(WKHUQHW0$&%ORFNV*7;/RZ3RZHU7UDQVFHLYHUV*7++LJK6SHHG7UDQVFHLYHUV&RPPHUFLDO,QGXVWULDO(PEHGGHG+DUG,35HVRXUFHV%ORFN5$0),)2Z(&&.EHDFK7RWDO%ORFN5$0.E0L[HG0RGH&ORFN0DQDJHUV00&0
6SHHG*UDGHV0D[LPXP6LQJOH(QGHG,20D[LPXP'LIIHUHQWLDO,23DLUV'63(6OLFHV([WHQGHG3&,([SUHVV,QWHUIDFH%ORFNV
;,/,1;9,57(;)3*$6
(DV\3DWK)3*$&RVW5HGXFWLRQ6ROXWLRQV6OLFHV/RJLF&HOOV&/%)OLS)ORSV9LUWH[/;7)3*$V2SWLPL]HGIRU+LJK3HUIRUPDQFH/RJLFDQG'63ZLWK/RZ3RZHU6HULDO&RQQHFWLYLW\99 9LUWH[6;7)3*$V2SWLPL]HGIRU8OWUD+LJK3HUIRUPDQFH'63ZLWK/RZ3RZHU6HULDO&RQQHFWLYLW\99 9LUWH[+;7)3*$V2SWLPL]HGIRU&RPPXQLFDWLRQV6\VWHPVWKDW5HTXLUH+LJKHVW%DQGZLGWK6HULDO&RQQHFWLYLW\93DUW1XPEHU0D[LPXP'LVWULEXWHG5$0.E/RJLF5HVRXUFHV0HPRU\5HVRXUFHV,25HVRXUFHV
;03Y ,PSRUWDQW9HULI\DOOGDWDLQWKLVGRFXPHQWZLWKWKHGHYLFHGDWDVKHHWVIRXQGDWZZZ[LOLQ[FRP
&RQILJXUDWLRQ 3DFNDJH $UHD)) [PP )) [PP )) [PP )) [PP )) [PP )) [PP )) [PP )) [PP )) [PP ;03Y1RWHV $VLQJOH9LUWH[)3*$&/%FRPSULVHVWZRVOLFHVHDFKFRQWDLQLQJIRXULQSXW/87VDQGHLJKWIOLSIORSVWZLFHWKHQXPEHUIRXQGLQD9LUWH[)3*$VOLFHIRUDWRWDORIHLJKWLQSXW/87VDQGIOLSIORSVSHU&/%9LUWH[)3*$ORJLFFHOOUDWLQJVUHIOHFWWKHLQFUHDVHGORJLFFDSDFLW\RIIHUHGE\WKHLQSXW/87DUFKLWHFWXUH'LJLWDOO\&RQWUROOHG,PSHGDQFH'&,LVDYDLODEOHRQ,2VRIDOOGHYLFHV2QH6\VWHP0RQLWRUEORFNLVLQFOXGHGLQDOOGHYLFHV$OOSURGXFWVDUHDYDLODEOH3EIUHHDQG5R+6&RPSOLDQW))*$YDLODEOH8VHU,26HOHFW,2,QWHUIDFH3LQV*7;/RZ3RZHU7UDQVFHLYHUV*7++LJK6SHHG7UDQVFHLYHUV))$3DFNDJHV)))OLSFKLSILQHSLWFK%*$PPEDOOVSDFLQJ
(DV\3DWK)3*$VSURYLGHDFRQYHUVLRQIUHHORZULVNSDWKIRUYROXPHSURGXFWLRQ&RQILJXUDWLRQ 0HPRU\ 0E
6XSSRUWHG,2VWDQGDUGVLQFOXGH+7/9&0269999+67/,999+67/,,99+67/,,,99/9'6([WHQGHG/9'656'6%XV/9'6/93(&/667/,99667/,,99DQG667/96XSSRUWHG,2VWDQGDUGVLQFOXGH+7/9'6/9'6(;756'6%/9'68/9'6/93(&//9&026/9&026/9&026/9&026/977/3&,3&,3&,;*7/*7/+67/,999+67/,,99+67/,,,99+67/,999667/,667/,,667/,DQG667/,,;03Y ,PSRUWDQW9HULI\DOOGDWDLQWKLVGRFXPHQWZLWKWKHGHYLFHGDWDVKHHWVIRXQGDWZZZ[LOLQ[FRP
sPartan-6 fPgas
7Important: Verify all data in this document with the device data sheets found at www.xilinx.com
;&6/; ;&6/; ;&6/; ;&6/; ;&6/; ;&6/; ;&6/; ;&6/; ;&6/;7 ;&6/;7 ;&6/;7 ;&6/;7 ;&6/;7 &ORFN5HVRXUFHV / /1 /1 /1 /1 /1 /1 /1 1 1 1 1 1/ /1 /1 /1 /1 /1 /1 /1 1 1 1 1 1&RQILJXUDWLRQ 3DFNDJH %RG\$UHD&3* [PP 74* [PP
6SDUWDQ/;)3*$V2SWLPL]HGIRU/RZHVW&RVW/RJLF'63DQG0HPRU\99 6SDUWDQ/;7)3*$V2SWLPL]HGIRU/RZHVW&RVW/RJLF'63DQG0HPRU\ZLWK+LJK6SHHG6HULDO&RQQHFWLYLW\90D[LPXP8VHU,26HOHFW,2,QWHUIDFH3LQV*737UDQVFHLYHUV&KLS6FDOH3DFNDJHV&3*3EIUHHZLUHERQGFKLSVFDOH%*$PPEDOOVSDFLQJ74)33DFNDJHV74*3EIUHHWKLQ4)3PPOHDGVSDFLQJ,QGXVWULDO&RQILJXUDWLRQ0HPRU\0E
3DUW1XPEHU(PEHGGHG+DUG,35HVRXUFHV6SHHG*UDGHV
6OLFHV/RJLF&HOOV&/%)OLS)ORSV;,/,1;63$57$1)3*$6
'63$6OLFHV0D[LPXP'LVWULEXWHG5$0.E%ORFN5$0.EHDFK7RWDO%ORFN5$0.E&ORFN0DQDJHPHQW7LOHV&07 (QGSRLQW%ORFNIRU3&,([SUHVV0HPRU\&RQWUROOHU%ORFNV*73/RZ3RZHU7UDQVFHLYHUV&RPPHUFLDO 0D[LPXP6LQJOH(QGHG3LQV0D[LPXP'LIIHUHQWLDO3DLUV/RJLF5HVRXUFHV0HPRU\5HVRXUFHV,25HVRXUFHV
;03Y ,PSRUWDQW9HULI\DOOGDWDLQWKLVGRFXPHQWZLWKWKHGHYLFHGDWDVKHHWVIRXQGDWZZZ[LOLQ[FRP
&6* [PP &6* [PP &6* [PP )7* [PP )** [PP )** [PP )** [PP ;03Y1RWHV (DFKVOLFHFRQWDLQVIRXU/87VDQGHLJKWIOLSIORSV6SDUWDQ)3*$ORJLFFHOOUDWLQJVUHIOHFWWKHLQFUHDVHGORJLFFDSDFLW\RIIHUHGE\WKHQHZLQSXW/87DUFKLWHFWXUH%ORFN5$0DUHIXQGDPHQWDOO\.ELQVL]H(DFKEORFNFDQDOVREHXVHGDVWZRLQGHSHQGHQW.EEORFNV(DFK&07FRQWDLQVWZR'&0VDQGRQH3//(DFK'63$VOLFHFRQWDLQVDQ[PXOWLSOLHUDQDGGHUDQGDQDFFXPXODWRU7KH/;GHYLFHSLQRXWVDUHQRWFRPSDWLEOHZLWKWKH/;7GHYLFHSLQRXWV&3*DQG74*GRQRWKDYHPHPRU\FRQWUROOHUVXSSRUW1LVQRWDYDLODEOHIRUWKHVHSDFNDJHV&6*KDV;PHPRU\FRQWUROOHUVXSSRUWLQWKH/;DQG/;GHYLFHV7KHUHLVQRPHPRU\FRQWUROOHULQWKH/;GHYLFHV'HYLFHVLQWKH)**DQG&6*SDFNDJHVKDYHVXSSRUWIRUWZRPHPRU\FRQWUROOHUV'HYLFHVZLWK1VSHHGJUDGHGRQRWVXSSRUW0&%IXQFWLRQDOLW\
&KLS6FDOH3DFNDJHV&6*3EIUHHZLUHERQGFKLSVFDOH%*$PPEDOOVSDFLQJ%*$3DFNDJHV)7*3EDQG3EIUHHZLUHERQGILQHSLWFKWKLQ%*$PPEDOOVSDFLQJ%*$3DFNDJHV)**3EDQG3EIUHHZLUHERQGILQHSLWFK%*$PPEDOOVSDFLQJ
;03Y ,PSRUWDQW9HULI\DOOGDWDLQWKLVGRFXPHQWZLWKWKHGHYLFHGDWDVKHHWVIRXQGDWZZZ[LOLQ[FRP
Virtex-5 fPgas
8Important: Verify all data in this document with the device data sheets found at www.xilinx.com
;&9/; ;&9/; ;&9/; ;&9/; ;&9/; ;&9/; ;&9/; ;&9/;7 ;&9/;7 ;&9/;7 ;&9/;7 ;&9/;7 ;&9/;7 ;&9/;7 ;&9/;7 ;&(9/; ;&(9/; ;&(9/; ;&(9/; ;&(9/; ;&(9/;7 ;&(9/;7 ;&(9/;7 ;&(9/;7 ;&(9/;7 &RQILJXUDWLRQ &/%)OLS)ORSV3KDVH/RFNHG/RRS3//30&'
9LUWH[/;)3*$V2SWLPL]HGIRU+LJK3HUIRUPDQFH/RJLF9 9LUWH[/;7)3*$V2SWLPL]HGIRU+LJK3HUIRUPDQFH/RJLFZLWK/RZ3RZHU6HULDO&RQQHFWLYLW\93RZHU3&3URFHVVRU%ORFNV(QGSRLQW%ORFNVIRU3&,([SUHVV
3DUW1XPEHU(DV\3DWK)3*$&RVW5HGXFWLRQ6ROXWLRQV6OLFHV/RJLF&HOOV0D[LPXP'LVWULEXWHG5$0.E5RFNHW,2*7;+LJK6SHHG7UDQVFHLYHUV&RPPHUFLDO,QGXVWULDO&RQILJXUDWLRQ0HPRU\0E
;,/,1;9,57(;)3*$6
6SHHG*UDGHV,25HVRXUFHV&ORFN5HVRXUFHV0HPRU\5HVRXUFHV 5RFNHW,2*73/RZ3RZHU7UDQVFHLYHUV
%ORFN5$0),)2Z(&&.EHDFK7RWDO%ORFN5$0.E/RJLF5HVRXUFHV(WKHUQHW0$&%ORFNV0D[LPXP6LQJOH(QGHG3LQV0D[LPXP'LIIHUHQWLDO,23DLUV'63(6OLFHV(PEHGGHG+DUG,35HVRXUFHV
'LJLWDO&ORFN0DQDJHUV'&0
;03Y ,PSRUWDQW9HULI\DOOGDWDLQWKLVGRFXPHQWZLWKWKHGHYLFHGDWDVKHHWVIRXQGDWZZZ[LOLQ[FRP
3DFNDJH $UHD)) [PP )) [PP )) [PP )) [PP )) [PP )) [PP )) [PP )) [PP )) [PP)) [PP ;03Y1RWHV (DV\3DWK)3*$VSURYLGHDFRQYHUVLRQIUHHORZULVNSDWKIRUYROXPHSURGXFWLRQ$VLQJOH9LUWH[)3*$&/%FRPSULVHVWZRVOLFHVHDFKFRQWDLQLQJIRXULQSXW/87VDQGIRXUIOLSIORSVWZLFHWKHQXPEHUIRXQGLQD9LUWH[)3*$VOLFHIRUDWRWDORIHLJKWLQSXW/87VDQGHLJKWIOLSIORSVSHU&/%9LUWH[)3*$ORJLFFHOOUDWLQJVUHIOHFWWKHLQFUHDVHGORJLFFDSDFLW\RIIHUHGE\WKHLQSXW/87DUFKLWHFWXUH'LJLWDOO\&RQWUROOHG,PSHGDQFH'&,LVDYDLODEOHRQ,2VRIDOOGHYLFHV2QH6\VWHP0RQLWRUEORFNLVLQFOXGHGLQDOOGHYLFHV$OOSURGXFWVDUHDYDLODEOH3EIUHHDQG5R+6&RPSOLDQW))*
$YDLODEOH8VHU,26HOHFW,2,QWHUIDFH3LQV *73*7;6HULDO7UDQVFHLYHUV))$3DFNDJHV)))OLSFKLSILQHSLWFK%*$PPEDOOVSDFLQJ6XSSRUWHG,2VWDQGDUGVLQFOXGH+7/9'6/9'6(;756'6%/9'68/9'6/93(&//9&026/9&026/9&026/9&026/977/3&,3&,3&,;*7/*7/+67/,999+67/,,99+67/,,,99+67/,999667/,667/,,667/,DQG667/,,;03Y ,PSRUWDQW9HULI\DOOGDWDLQWKLVGRFXPHQWZLWKWKHGHYLFHGDWDVKHHWVIRXQGDWZZZ[LOLQ[FRP
Virtex-5 fPgas
9Important: Verify all data in this document with the device data sheets found at www.xilinx.com
;&96;7 ;&96;7 ;&96;7 ;&96;7 ;&9);7 ;&9);7 ;&9);7 ;&9);7 ;&9);7 ;&97;7 ;&97;7 ;&(96;7 ;&(96;7 ;&(96;7 ;&(9);7 ;&(9);7 ;&(9);7 ;&(9);7 ;&(97;7 ;&(97;7 &RQILJXUDWLRQ 3DFNDJH $UHD ,QGXVWULDO(WKHUQHW0$&%ORFNV0D[LPXP'LIIHUHQWLDO,23DLUV
&/%)OLS)ORSV'63(6OLFHV3RZHU3&3URFHVVRU%ORFNV&RPPHUFLDO
;,/,1;9,57(;)3*$6
(QGSRLQW%ORFNVIRU3&,([SUHVV(PEHGGHG+DUG,35HVRXUFHV6SHHG*UDGHV $YDLODEOH 8VHU ,2 6HOHFW,2 ,QWHUIDFH 3LQV *73*7; 6HULDO 7UDQVFHLYHUV
/RJLF5HVRXUFHV0HPRU\5HVRXUFHV&ORFN5HVRXUFHV,25HVRXUFHV&RQILJXUDWLRQ0HPRU\0E
9LUWH[);7)3*$V2SWLPL]HGIRU(PEHGGHG3URFHVVLQJZLWK+LJK6SHHG6HULDO&RQQHFWLYLW\9 9LUWH[7;7)3*$V2SWLPL]HGIRU8OWUD+LJK%DQGZLGWK93DUW1XPEHU 9LUWH[6;7)3*$V2SWLPL]HGIRU'63ZLWK/RZ3RZHU6HULDO&RQQHFWLYLW\95RFNHW,2*7;+LJK6SHHG7UDQVFHLYHUV
0D[LPXP'LVWULEXWHG5$0.E%ORFN5$0),)2Z(&&.EHDFK7RWDO%ORFN5$0.E'LJLWDO&ORFN0DQDJHUV'&06OLFHV(DV\3DWK)3*$&RVW5HGXFWLRQ6ROXWLRQV/RJLF&HOOV3KDVH/RFNHG/RRS3//30&'0D[LPXP6LQJOH(QGHG3LQV5RFNHW,2*73/RZ3RZHU7UDQVFHLYHUV
;03Y ,PSRUWDQW9HULI\DOOGDWDLQWKLVGRFXPHQWZLWKWKHGHYLFHGDWDVKHHWVIRXQGDWZZZ[LOLQ[FRP
3DFNDJH $UHD)) [PP)) [PP)) [PP)) [PP)) [PP)) [PP )) [PP )) [PP )) [PP )) [PP ;03Y1RWHV (DV\3DWK)3*$VSURYLGHDFRQYHUVLRQIUHHORZULVNSDWKIRUYROXPHSURGXFWLRQ9LUWH[)3*$ORJLFFHOOUDWLQJVUHIOHFWWKHLQFUHDVHGORJLFFDSDFLW\RIIHUHGE\WKHQHZLQSXW/87DUFKLWHFWXUH'LJLWDOO\&RQWUROOHG,PSHGDQFH'&,LVDYDLODEOHRQ,2VRIDOOGHYLFHV2QH6\VWHP0RQLWRUEORFNLQFOXGHGLQDOOGHYLFHV$OOSURGXFWVDUHDYDLODEOH3EIUHHDQG5R+6&RPSOLDQW))*6XSSRUWHG,2VWDQGDUGVLQFOXGH+7/9'6/9'6(;756'6%/9'68/9'6/93(&//9&026/9&026/9&026/9&026/977/3&,3&,3&,;*7/*7/+67/,999+67/,,99+67/,,,99+67/,999667/,667/,,667/,DQG667/,,$VLQJOH9LUWH[)3*$&/%FRPSULVHVWZRVOLFHVHDFKFRQWDLQLQJIRXULQSXW/87VDQGIRXUIOLSIORSVWZLFHWKHQXPEHUIRXQGLQD9LUWH[)3*$VOLFHIRUDWRWDORIHLJKWLQSXW/87VDQGHLJKWIOLSIORSVSHU&/%))$3DFNDJHV)))OLSFKLSILQHSLWFK%*$PPEDOOVSDFLQJ $YDLODEOH 8VHU ,2 6HOHFW,2 ,QWHUIDFH 3LQV *73*7; 6HULDO 7UDQVFHLYHUV
;03Y ,PSRUWDQW9HULI\DOOGDWDLQWKLVGRFXPHQWZLWKWKHGHYLFHGDWDVKHHWVIRXQGDWZZZ[LOLQ[FRP
cPlD ProDucts
10Important: Verify all data in this document with the device data sheets found at www.xilinx.com
;,/,1;&3/'352'8&76&RRO5XQQHU,,)DPLO\
;03Y ,PSRUWDQW9HULI\DOOGDWDLQWKLVGRFXPHQWZLWKWKHGHYLFHGDWDVKHHWVIRXQGDWZZZ[LOLQ[FRP
;&&$ ;&&$ ;&& ;&& ;&& ;&& &ORFN5HVRXUFHV 3URGXFW7HUPV3HU0DFURFHOO*OREDO&ORFNV3URGXFW7HUP&ORFNV3HU)XQFWLRQ%ORFN3DUW1XPEHU6\VWHP*DWHV0DFURFHOOV/RJLF5HVRXUFHV 3DFNDJH $UHD,25HVRXUFHV ,QSXW9ROWDJH&RPSDWLEOH2XWSXW9ROWDJH&RPSDWLEOH0LQ3LQWR3LQ/RJLF'HOD\QV&RPPHUFLDO6SHHG*UDGHV)DVWHVWWR6ORZHVW0D[LPXP,2 0D[LPXP8VHU,2V4)13DFNDJHV4)*4XDGIODWQROHDGPPOHDGVSDFLQJ,QGXVWULDO6SHHG*UDGHV)DVWHVWWR6ORZHVW6SHHG*UDGHV 4) [PP 4) [PP 94 [PP 94 [PP &3 [PP &3 [PP J S J94)33DFNDJHV949HU\WKLQ4)394PPOHDGVSDFLQJ94PPOHDGVSDFLQJ&KLS6FDOH3DFNDJHV&3:LUHERQGFKLSVFDOH%*$PPEDOOVSDFLQJ74 [PP74 [PP 34 [PP )7 [PP )*$3DFNDJHV)*:LUHERQGILQHSLWFK%*$PPEDOOVSDFLQJ)%*$3DFNDJHV )*:LUHERQGILQHOLQH%*$PPEDOOVSDFLQJ
74)33DFNDJHV747KLQ4)3PPOHDGVSDFLQJ34)33DFNDJHV34:LUHERQGSODVWLF4)3PPOHDGVSDFLQJ)* [PP ;03Y1RWHV VSHHGJUDGHLVRQO\DYDLODEOHLQ)7*SDFNDJH$OOSDFNDJHVDUHDYDLODEOHLQ3E)UHHDQG5R+6FRPSOLDQWYHUVLRQV$UHDGLPHQVLRQVIRUOHDGIUDPHSURGXFWDUHLQFOXVLYHRIWKHOHDGV2QO\DYDLODEOHLQ5R+6FRPSOLDQWDQG+DORJHQIUHHSDFNDJHV)%*$ 3DFNDJHV )* :LUH ERQG ILQH OLQH %*$ PP EDOO VSDFLQJ
;03Y ,PSRUWDQW9HULI\DOOGDWDLQWKLVGRFXPHQWZLWKWKHGHYLFHGDWDVKHHWVIRXQGDWZZZ[LOLQ[FRP
configuration solutions
11Important: Verify all data in this document with the device data sheets found at www.xilinx.com
;LOLQ[&RQILJXUDWLRQ0HPRU\&URVV5HIHUHQFH 3DUW1XPEHU ;&)6 ;&)6 ;&)6 ;&)3 ;&)3 ;&)3 ;&);;&9/;7 ;&)3 ;&6/; ;&)6 ;&6$ ;&)6 'HQVLW\ 0E 0E 0E 0E 0E 0E 0E;&9/;7 ;&); ;&6/; ;&)6 ;&6$ ;&)6 -7$*3URJUDPPDEOH
configuration solutions
12Important: Verify all data in this document with the device data sheets found at www.xilinx.com
&RQILJXUDWLRQ+DUGZDUH3URGXFWV .H\&RQILJXUDWLRQ6ROXWLRQV$SSOLFDWLRQ1RWHV
;LOLQ['RZQORDG&DEOH&KDUW &RQILJXUDWLRQ$SSOLFDWLRQ1RWHVIRU,Q6\VWHP3URJUDPPLQJDQG5HPRWH8SGDWH3ODWIRUP&DEOH86%,, ;LOLQ[,Q6\VWHP3URJUDPWPLQJ8VLQJDQ(PEHGGHG0LFURFRQWUROOHUDPLFURSURFHVVRUVROXWLRQ;$33+:86%,,* (PEHGGHG,Q6\VWHP3URJUDPPLQJ-7$*$&(3OD\HU6ROXWLRQ;$33&RQQHFWLRQWR3& 86%%DVLF6SHHGRU86%+LJK6SHHG 0XOWLSOH%RRWZLWK3ODWIRUP)ODVK3520VDQG6SDUWDQ()3*$V;$33,29ROWDJH6XSSRUW 9999DQG9 $&3/'%DVHG&RQILJXUDWLRQDQG5HYLVLRQ0DQDJHUIRU;LOLQ[3ODWIRUP)ODVK3520VDQG)3*$V;$330XOWLSOH&DEOH0DQDJHPHQW
Design tools ise Design suite
13Important: Verify all data in this document with the device data sheets found at www.xilinx.com
ISE Design Suite Device Support
ISE WebPACK Tool ISE Design Suite Logic Edition
Embedded EditionDSP Edition
ISE Design Suite Comparison Table ISE WebPACK
Tool
Logic Edition
Embedded Edition
DSPEdition
System Edition
DSP Edition System Edition (Device Limited)
)miSI( rotalumiS ESI htiw slooT noitadnuoF ESIsAGPF 4-xetriV sAGPF 4-xetriV looT sisylanA ngiseD daehAnalPllA :XL 52XLV4CX ,51XLV4CX :XL rezylanA cigoL orP epocSpihCllA :XS 52XSV4CX :XS tiklooT O/I laireS orP epocSpihCllA :XF 21XFV4CX :XF
Embedded Development Kit (EDK) * * * )KDS( tiK tnempoleveD erawtfoSsAGPF 5-xetriVsAGPF 5-xetriV
LX: XC5VLX30, XC5VLX50 LX: All System Generator for DSP LX: XC5VLX30, XC5VLX50 LX: All System Generator for DSP LXT: XC5VLX20T - XC5VLX50T LXT: All * Device Limited to Zynq-7000 EPP Z7010, Z7020, Z7030 devices only FXT: XC5VFX30T SXT: All
FXT: AllsAGPF 6-xetriVsAGPF 6-xetriV Targeted Stand-Alone Products
)KDS( tiK tnempoleveD erawtfoSllA T57XLCX ChipScope Pro and ChipScope Pro Serial I/O Toolkit
Virtex-7 FPGAs None
Virtex-7 FPGAs All Embedded Development Kit (EDK)
Kintex FPGAsKintex-7 FPGAs
XC7K70T XC7K160TKintex-7 FPGAs
All System Generator for DSP
UsageEmbedded software developers who do not require ISE tools
Lab Environments
ISE WebPACK Tool Users
Virtex FPGAs
XC7K70T, XC7K160T All
Artix FPGAsArtix-7 FPGAs: XC7A100T, XC7A200T
Artix-7 FPGAs: All
Zynq Extensible Processing Platform
Zynq-7000 EPP: XC7Z010, XC7Z020, XC7Z030
Zynq-7000 EPP: All
llA :sAGPF 3-natrapSsAGPF 3-natrapS XC3S50 - XC3S1500Spartan-3A FPGAs AllSpartan-3AN FPGAs
Spartan-3A FPGAs: AllSpartan-3AN FPGAs: AllSpartan-3 DSP FPGAs: AllSpartan-3E FPGAs: All -B
it*
it* 2/64
-bit
2/65
-bit
-bit
AllSpartan-3A DSP FPGAs XC3SD1800ASpartan-3E FPGAs All Spartan-6 FPGAs XC6SLX4 - XC6SLX75TXA (Xilinx Automotive) Spartan-3 FPGAs AllXA (Xilinx Automotive) Spartan-6 FPGAs
Spartan-6 FPGAs: AllXA (Xilinx Automotive)
ows XP Professiona
l 32/64
-
ows 7 Professiona
l 32/64
-B
ows Server 2
008
Hat Enterprise Linu
x 5 WS3
Hat Enterprise Linu
x 6 WS3
Linu
x Enterprise 11
32/64
Spartan FPGAs
FPGAs All ISE Design Suite
Operating System Support Windo
Windo
Windo
Red
HRed
H
SUSE
ISE Design Entry and Implementation Tools ISE Simulator (ISim)
ISE WebPACK ChipScope Pro and ChipScope Pro Serial I/O Toolkit
Embedded Development Kit (EDK) and Platform Studio XC9500 Series Software Development Kit (SDK)
System Generator for DSP
CoolRunner XPLA3CoolRunner-II CPLDs All
All (Except 9500XV Family)
XMP075 (v3.0)
*US and Japanese: Full Support. Chinese: Limited Support.
Zynq-7000q all Programmable socs
14Important: Verify all data in this document with the device data sheets found at www.xilinx.com
Device Name Z-7045Part Number XQ7Z045
Zynq-7000Q All Programmable SoC 0307-Z0207-Z
XQ7Z020 XQ7Z030Part Number XQ7Z045Processor Core
Processor Extensions
Maximum Frequency
L1 Cache
L2 Cache
On-Chip Memory
External Memory SupportProcessing System
Dual ARM Cortex-A9 MPCore with CoreSight
NEON & Single / Double Precision Floating Point for each processor
32 KB Instruction, 32 KB Data per processor
512 KB
256 KB
DDR3, DDR2, LPDDR2
733 MHz
XQ7Z020 XQ7Z030
External Static Memory Support
DMA Channels
Peripherals
Peripherals w/ Built-in DMA
Security(1)
Processing System to Programmable Logic Interface Ports (Primary Interfaces & Interrupts Only)
2x AXI 32b Master, 2x AXI 32b Slave,4x AXI 64b/32b Memory
AXI 64b ACP16 Interrupts
2x Quad-SPI, NAND, NOR
8 (4 dedicated to Programmable Logic)
2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO
2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO
AES and SHA 256b Decryption and Authentication for Secure Boot
Xilinx 7 Series Programmable Logic Equivalent Kintex-7Q FPGA
Programmable Logic Cells (Approximate ASIC Gates(2)) 350K Logic Cells (~5.2M)
Look-Up Tables (LUTs) 218,600
Flip-Flops 437,200
Extensible Block RAM (36 Kb Blocks) 2,180 KB (545)
Programmable DSP Slices (18x25 MACCs) 900
PCI Express (Root Complex or Endpoint) x8 Gen2
Analog Mixed Signal (AMS) / XADC
560 KB (140)
006,87002,35
106,400
AGPF Q7-xetniKAGPF Q7-xitrA
16 Interrupts
Programmable Logic
2x 12 bit MSPS ADCs with up to 17 Differential Inputs
400
2neG 4x
157,200
1,060 KB (265)
220
)M9.1~( slleC cigoL K521)M3.1~( slleC cigoL K58
Analog Mixed Signal (AMS) / XADC
Security(1)
Q-Temp (40C to 125C)
Industrial (40C to 100C)
Package Type(3) 484LC004LC RB484(5) 676FR676FR
72x7272x7232x3291x9171x71)mm( eziS
0.10.10.18.08.0)mm( hctiP
2x 12 bit, MSPS ADCs with up to 17 Differential Inputs
AES and SHA 256b Decryption and Authentication for Secure Programmable Logic Configuration
-1Speed Grades
-1, -2
Processing System User I/Os (excludes DDR dedicated I/Os)(4) 4545454545
Multi-Standards and Multi-Voltage SelectIOTM Interfaces(1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V)
001001001002521
Multi-Standards and Multi-Voltage High Performance SelectIO Interfaces(1.2V, 1.35V, 1.5V, 1.8V) 05105136
844sreviecsnarT laireS
s/bG 5213.01s/bG 5213.01s/bG 6.6A/NA/N)tnednepeD edarG deepS( deepS reviecsnarT mumixaM
XMP092 (v1.0)
Packages
Notes: 1. Security block is shared by the Processing System and the Programmable Logic.
2. Equivalent ASIC gate count is dependent of the function implemented. The assumption is 1 Logic Cell = ~15 ASIC Gates.
3. Devices in the same package are pin-to-pin compatible.
5. RB484 is a ruggedized version of FB484 (4-corner lid added).
6. Preliminary product information. Subject to change. Please contact your Xilinx representative for the latest information.
4. Static memory interface combined with the usage of many peripherals could require more than 54 I/Os. In that case, the designer can use the Programmable Logic SelectIO interface.
Virtex-7q t Defense-graDe fPgas
15Important: Verify all data in this document with the device data sheets found at www.xilinx.com
XQ7V585T XQ7VX330T XQ7VX485T XQ7VX690T XQ7VX980T
91,050 51,000 75,900 108,300 153,000582,720 326,400 485,760 693,120 979,200728,400 408,000 607,200 866,400 1,224,0006,938 4,388 8,175 10,888 13,838
005,1074,1030,105759728,620 27,000 37,080 52,920 54,000
8102414181secruoseR kcolC009000,1007007058234084633633804
1,260 1,120 2,800 3,600 3,60043332
Virtex-7Q T FPGAs
PCI Express Gen 3 Interface Blocks
Part Number
Logic ResourcesSlices(1)
I/O Resources
Embedded Hard IP
Mixed Mode Clock Managers (MMCM)
Maximum Single-Ended I/O(3)
Maximum Differential I/O Pairs DSP48E1 Slices
PCI Express Gen 2 Interface Blocks
Logic Cells(2)
CLB Flip-Flops
MemoryResources
Maximum Distributed RAM (Kb) Block RAM/FIFO w/ ECC (36 Kb each)
Total Block RAM (Kb)
11111111118263426382L2-L2-L2-L2-1-2- ,1-2- ,1-2- ,1-2- ,1-1-1-1-
Package Dimensions (mm))02 ,0( 006 ,0)02 ,0( 006 ,0 )0 ,02( 006 ,053 x 53 7511FR
RF1761 42.5 x 42.5 100, 750 (36, 0) 50, 650 (0,28) 0, 700 (28,0) 0, 850 (0,36) )42,0( 009,0 )42,0(0001 ,0 )0,42( 007 ,054 x 54 0391FR
XMP091 (v1.0)
Notes:
6. This is preliminary product information, subject to change . Please contact A&D Marketing for the latest information.
2. Virtex-7 FPGA logic cell ratings reflect the increased logic capacity offered by the 6-input LUT architecture. 3. Refer to data sheet for details on I/O standards support. 4. 10.3125 Gb/s support in -2 speed grade. 5. 11.3 Gb/s support in -2 speed grade.
1. A single Virtex-7 FPGA CLB comprises two slices, with each containing four 6-input LUTs and eight Flip-Flops, for a total of eight 6-LUTs and 16 Flip-Flops per CLB.
Available User I/O: 3.3V SelectIO Pins, 1.8V SelectIO Pins (GTX, GTH Transceivers)
GTH 11.3 Gb/s Transceivers(5)
Analog Front End (XADC) / SysMon Blocks Hard IP
ResourcesConfiguration AES / HMAC Blocks
GTX 10.3125 Gb/s Transceivers(4)
Extended Temp (0 to +100C)Industrial Temp (40 to +100C) Military Temp (55 to +125C)
Speed Grades
Kintex-7q t Defense-graDe fPgas
16Important: Verify all data in this document with the device data sheets found at www.xilinx.com
T014K7QXT523K7QX
055,36059,05027,604080,623004,805006,704
366,5000,4597544026,82020,61
Clock Resources 0101005005042042
840 1 540
Kintex-7Q T FPGAs
Part Number
Logic ResourcesSlices
Logic Cells CLB Flip-Flops
MemoryResources
Maximum Distributed RAM (Kb) Block RAM/FIFO w/ ECC (36 Kb each)
Total Block RAM (Kb) Mixed Mode Clock Managers (MMCM)
Maximum Single-Ended I/O Maximum Differential I/O Pairs
DSP48E1 Slices
I/O Resources
840 1,5401111116161L2-L2-2- ,1-2- ,1-
1-1-
)mm( snoisnemiD egakcaP
)8( 051 ,052)8( 051 ,05272 x 72676FR )61( 051 ,053)61( 051 ,05313 x 13009FR XMP090 (v1.0)
Notes:
Extended Temp (0 to +100C) Industrial Temp (40 to +100C)
2. This is preliminary product information, subject to change. Please contact A&D Marketing for the latest information.
Available User I/O: 3.3V SelectIO Pins, 1.8V SelectIO Pins (GTX Transceivers)
1. Supports PCI Express Base 2.1 specification at Gen1 and Gen2 data rates.
Military Temp (55 to +125C) Speed Grades
DSP48E1 SlicesPCI Express(1)
Analog Front End (XADC) / SysMon Blocks Embedded Hard IP
Resources Configuration AES / HMAC Blocks GTX 10.3125 Gb/s Transceivers
artix-7q t Defense-graDe fPgas
17Important: Verify all data in this document with the device data sheets found at www.xilinx.com
T002A7QXT001A7QX
056,33058,51063,512044,101002,962008,621
888,2881,1563531041,31068,4
Clock Resources 016004582291731047042
111111842- ,1-2- ,1-
1-1- Package(2) Dimensions (mm)
)0( 01251 x 51423SC )4( 58232 x 32484GF
RB484(3) 23 x 23 285 (4) RB676(3) 27 x 27 400 (8) RS484(4) 19 x 19 285 (4)
XMP089 (v1.0)Notes:
5. This is preliminary product information, subject to change. Please contact A&D Marketing for the latest information.
1. Supports PCI Express Base 2.1 specification at Gen1 and Gen2 data rates.2. Design migration is available within the Artix-7Q family for like packages, but is not supported between other 7 Series families. (CS: 0.8 mm wire-bond chip-scale. FG: 1.0 mm wire-bond fine-pitch.)3. RB484 & RB676 are ruggedized versions (4-corner lid added) of FB484 and FB676 packages. (FB: 1.0 mm flip-chip bare-die.)4. RS484 is a ruggedized version (4-corner lid added) of SB484 package. Feasibility of this lid is in process. (SB: 0.8 mm flip-chip bare-die.)
Industrial Temp (40 to 100C) Military Temp (55 to 125C)
Available User I/O: 3.3V SelectIO Pins (GTP Transceivers)
EmbeddedHard IP
Resources
DSP48E1 Slices
PCI Express(1)
Analog Front End (XADC) / SysMon Blocks Configuration AES / HMAC Blocks
Speed Grades
Artix-7Q T FPGAs
Part Number
Slices slleC cigoLsecruoseR cigoL
CLB Flip-Flops
GTP 5.4/ 6.6 Gb/s Transceivers
MemoryResources
Maximum Distributed RAM (Kb) Block RAM/FIFO w/ ECC (36 Kb each)
Total Block RAM (Kb) Mixed Mode Clock Managers (MMCM)
I/O ResourcesMaximum Single-Ended I/O
Maximum Differential I/O Pairs
sPartan-6q Defense-graDe fPgas
18Important: Verify all data in this document with the device data sheets found at www.xilinx.com
;46/; ;46/; ;46/;7 ;46/;7;,/,1;$(5263$&('()(16(62/87,2163DUW1XPEHU 6SDUWDQ4)3*$V'HIHQVH*UDGH)3*$V
;03Y ,PSRUWDQW9HULI\DOOGDWDLQWKLVGRFXPHQWZLWKWKHGHYLFHGDWDVKHHWVIRXQGDWZZZ[LOLQ[FRP
4 4 4 4 &ORFN5HVRXUFHV /RJLF&HOOV&/%)OLS)ORSV/RJLF5HVRXUFHV(PEHGGHG+DUG,35HVRXUFHV '63$6OLFHV,QWHUIDFH%ORFNVIRU3&,([SUHVV0HPRU\5HVRXUFHV 0D[LPXP'LVWULEXWHG5$0.E%ORFN5$0.EHDFK7RWDO%ORFN5$0.E&ORFN0DQDJHPHQW7LOHV&07 / / 3DFNDJH $UHD&6* [PP )* [PP )** [PP ;03 Y 0D[LPXP6HOHFW,2,QWHUIDFH3LQV*736HULDO7UDQVFHLYHUV0LVFHOODQHRXV 6SHHG*UDGHV([WHQGHG4&&6SHHG*UDGHV,QGXVWULDO,&&(PEHGGHG +DUG ,3 5HVRXUFHV 0HPRU\&RQWUROOHU%ORFNV*73/RZ3RZHU7UDQVFHLYHUV ;03 Y1RWHV 3EIUHHDGGLWLRQDO*QRWDYDLODEOHIRU6SDUWDQ4WHPSGHYLFHV'HYLFHVLQWKH&6*DQG)*VXSSRUWWZRPHPRU\FRQWUROOHUV'XHWRWKH*73WUDQVFHLYHUVLQWKH/;7GHYLFHVSLQRXWVIRUWKH/;DQG/;7GHYLFHVDUHQRWFRPSDWLEOH
;03Y ,PSRUWDQW9HULI\DOOGDWDLQWKLVGRFXPHQWZLWKWKHGHYLFHGDWDVKHHWVIRXQGDWZZZ[LOLQ[FRP
Virtex-5q Defense-graDe fPgas
19Important: Verify all data in this document with the device data sheets found at www.xilinx.com
;49/;7 ;49/; ;49/; ;49/;7 ;49/;7 ;49/;7 ;49/;7 ;496;7 ;496;7 ;496;7 ;49);7 ;49);7 ;49);7 ;49/;7 6OLFHV 'HIHQVH*UDGH)3*$V9LUWH[4)3*$V3DUW1XPEHU;,/,1;$(5263$&('()(16(62/87,216
;03Y ,PSRUWDQW9HULI\DOOGDWDLQWKLVGRFXPHQWZLWKWKHGHYLFHGDWDVKHHWVIRXQGDWZZZ[LOLQ[FRP
&ORFN5HVRXUFHV /RJLF5HVRXUFHV0HPRU\5HVRXUFHV 0D[LPXP'LVWULEXWHG5$0.E6OLFHV/RJLF&HOOV&/%)OLS)ORSV3KDVH/RFNHG/RRS30&'7RWDO%ORFN5$0.E'LJLWDO&ORFN0DQDJHU'&0,2 5 %ORFN5$0),)2Z(&&.EHDFK &RQILJXUDWLRQ
0D[LPXP6LQJOH(QGHG3LQV(WKHUQHW0$&%ORFNV0D[LPXP'LIIHUHQWLDO,23DLUV,25HVRXUFHV(PEHGGHG+DUG,35HVRXUFHV 5RFNHW,2*73/RZ3RZHU7UDQVFHLYHUV3RZHU3&3URFHVVRU%ORFNV,QWHUIDFH%ORFNVIRU3&,([SUHVV'63(6OLFHV5RFNHW,2*7;+LJK6SHHG7UDQVFHLYHUV&RQILJXUDWLRQ 0HPRU\ 0E&RQILJXUDWLRQ , , , , , , , , , , ,0 ,0 , ,3DFNDJH $UHD() [PP () [PP )) [PP () [PP () [PP $YDLODEOH8VHU,26HOHFW,2,QWHUIDFH3LQV*73*7;6HULDO7UDQVFHLYHUV0DQXIDFWXULQJ*UDGHV0LVFHOODQHRXV&RQILJXUDWLRQ 0HPRU\ 0E6SHHG*UDGHV () [PP )) [PP ;03Y1RWHV $VLQJOH9LUWH[4)3*$&/%FRPSULVHVWZRVOLFHVZLWKHDFKFRQWDLQLQJIRXULQSXW/87VDQGIRXUIOLSIORSVWZLFHWKHQXPEHUIRXQGLQD9LUWH[)3*$VOLFHIRUDWRWDORIHLJKW/87VDQGHLJKWIOLSIORSVSHU&/%9LUWH[)3*$ORJLFFHOOUDWLQJVUHIOHFWWKHLQFUHDVHGORJLFFDSDFLW\RIIHUHGE\WKHQHZLQSXW/87DUFKLWHFWXUH'LJLWDOO\&RQWUROOHG,PSHGDQFH'&,LVDYDLODEOHRQ,2VRIDOOGHYLFHV2QHV\VWHPPRQLWRUEORFNLQFOXGHGLQDOOGHYLFHV,2VWDQGDUGVVXSSRUWHG+7/9'6/9'6(;756'6%/9'68/9'6/93(&//9&026/9&026/9&026/9&026/977/3&,3&,3&,;*7/*7/+67/,999+67/,,99+67/,,,99+67/,999667/,667/,,667/,DQG667/,,$YDLODEOH,2IRUHDFKGHYLFHSDFNDJHFRPELQDWLRQQXPEHURI6HOHFW,2LQWHUIDFHSLQVQXPEHURI5RFNHW,2WUDQVFHLYHUV0JUDGHDYDLODEOHRQO\LQVSHHGJUDGHDQG()SDFNDJH*UDGH9 ;LOLQ[9*UDGH)ORZ0LOLWDU\&HUDPLF 7M &WR&+% 60'5DGLDWLRQ7ROHUDQWDQG1RQ5760'0LOLWDU\&HUDPLF 7M &WR&7M &WR&7 & W &0DQXIDFWXULQJ*UDGHVKWWSZZZ[LOLQ[FRPSURGXFWVPLODHURUSWSGI)OLS&KLS5DGLDWLRQ7ROHUDQW&HUDPLF'HVFULSWLRQ 7HPSHUDWXUH10 0LOLWDU\&HUDPLFRU3ODVWLF 7M &WR&, 1RWHV 3HU$'40LOLWDU\3ODVWLF,QGXVWULDO3ODVWLF 7M &WR&7M &WR&;03Y ,PSRUWDQW9HULI\DOOGDWDLQWKLVGRFXPHQWZLWKWKHGHYLFHGDWDVKHHWVIRXQGDWZZZ[LOLQ[FRP
Virtex-4q, Virtex-ii Pro xq, anD Virtex-ii xq Defense-graDe fPgas
20Important: Verify all data in this document with the device data sheets found at www.xilinx.com
;49/; ;49/; ;49/; ;49/; ;49/; ;496; ;49); ;49); ;493 ;493 ;49 ;49 ;499 9 9 9 9 9 9 9 9 9 9 9 9 &ORFN5HVRXUFHV
Virtex-5qV, Virtex-4qV, Virtex-iixqr, anD Virtex-xqr Defense-graDe fPgas
21Important: Verify all data in this document with the device data sheets found at www.xilinx.com
9LUWH[49)3*$V 9LUWH[,,;45)3*$V;459); ;459/; ;4596; ;459); ;459); ;459 ;495 ;4959 9 9 9 9 9 9 9
xilinx aerosPace anD Defense solutions
22Important: Verify all data in this document with the device data sheets found at www.xilinx.com
;4/ ;49 ;494 ;4)3 ;45/ ;4599 9 9 9 9 90 0 0 0 0 001 01 1 0 09 09 &&94 &&94 94 94 && &&3DFNDJH $UHD&& [LQ94 [PP94 [PP1RWHV ;LOLQ[FRQILJXUDWLRQ3520VKDYHDGMXVWDEOH,2YROWDJHVIRUFRPSDWLELOLW\ZLWKDOO;LOLQ[)3*$V7KH&&DQG3&SDFNDJHVDUHIRRWSULQWSLQFRPSDWLEOH)RULQIRUPDWLRQRQ'6&&TXDOLILFDWLRQFRQWDFW;LOLQ[*UDGH9 7& &WR&+ 7M &WR&% 7& &WR&1 0LOLWDU\3ODVWLF 7M &WR&0 7 & W & 3O WL 7 & W & & L
;,/,1;$(5263$&('()(16(62/87,216
'HVFULSWLRQ'HYLFH;LOLQ[9*UDGH)ORZ 0LOLWDU\&HUDPLF'HYLFH)OLS&KLS5DGLDWLRQ7ROHUDQW&HUDPLF
6SDFH*UDGH'HYLFHV5DGLDWLRQ7ROHUDQW&RQILJXUDWLRQ3520V60'5DGLDWLRQ7ROHUDQWDQG1RQ5760'0LOLWDU\&HUDPLF0LOLW & L 3O WL
'HIHQVH*UDGH&RQILJXUDWLRQ3520V0DQXIDFWXULQJ*UDGHV7RWDO,RQL]LQJ'RVHNUDG3DFNDJHV3DUW1XPEHU&RUH9ROWDJH6WRUDJH%LWV0DQXIDFWXULQJ*UDGHVKWWSZZZ[LOLQ[FRPSURGXFWVPLODHURUSWSGI 7HPSHUDWXUH
;03Y ,PSRUWDQW9HULI\DOOGDWDLQWKLVGRFXPHQWZLWKWKHGHYLFHGDWDVKHHWVIRXQGDWZZZ[LOLQ[FRP
0 7M &WR&3ODVWLF7& &WR&&HUDPLF, ,QGXVWULDO3ODVWLF 7M &WR& ;03Y1RWHV 3HU$'40LOLWDU\&HUDPLFRU3ODVWLF
;03Y ,PSRUWDQW9HULI\DOOGDWDLQWKLVGRFXPHQWZLWKWKHGHYLFHGDWDVKHHWVIRXQGDWZZZ[LOLQ[FRP
xa Zynq-7000 all Programmable socs
23Important: Verify all data in this document with the device data sheets found at www.xilinx.com
Device NameXA Zynq-7000 All Programmable SoC
Z-7010 Z-7020Device NamePart Number
Processor Core
Processor Extensions
Maximum Frequency
L1 Cache
L2 Cache
Dual ARM Cortex-A9 MPCore with CoreSight
NEON & Single / Double Precision Floating Point for each processor
32 KB Instruction, 32 KB Data per processor
512 KB
667 MHz
020Z7AX010Z7AXZ-7010 Z-7020
On-Chip Memory
External Memory Support (1)
External Static Memory Support (1)
DMA Channels
Peripherals
Peripherals w/ built-in DMA(1)
Security(2)
Processing System256 KB
DDR3, DDR2, LPDDR2
2x Quad-SPI, NAND, NOR
2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO
8 (4 dedicated to Programmable Logic)
2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO
AES and SHA 256b Decryption and Authentication for Secure Boot y
Processing System to Programmable Logic Interface Ports (Primary Interfaces & Interrupts Only)
Xilinx 7 Series Programmable Logic Equivalent
Programmable Logic Cells (Approximate ASIC Gates(3))
Look-Up Tables (LUTs)
Flip Flops
2x AXI 32b Master, 2x AXI 32b Slave,4x AXI 64b/32b Memory
AXI 64b ACP16 Interrupts
AGPF 7-xitrAAGPF 7-xitrA
)M3.1~( slleC cigoL K58 )K034~( slleC cigoL K82
002,35006,71
35 200 106 400
y
Flip-Flops
Extensible Block RAM (# 36 Kb Blocks)
Programmable DSP Slices (18x25 MACCs)
Peak DSP Performance (Symmetric FIR)
Agile Mixed Signal (AMS) / XADC(1)
Security(2)
Industrial (-40C to 100C)
2x 12 bit, MSPS ADCs with up to 17 Differential Inputs
AES and SHA 256b Decryption and Authentication for Secure Programmable Logic Configuration
Speed Grades-1
Programmable Logic )041( BK 065 )06( BK 042
02208
sCAMG 402sCAMG 47
35,200 106,400
Automotive (-40C to 125C)
Package Type(4) CLG225(1) 484GLC004GLC004GLC
91x9171x7171x7131x31)mm( eziS
8.08.08.08.0)mm( hctiP
Processing System User I/Os (excludes DDR dedicated I/Os)(5) 45454523
Multi-Standards and Multi-Voltage SelectIOTM Interfaces(1.2V, 1.35V, 1.5V, 1.8V, 2.5V, 3.3V)
00252100145
XMP088 ( 1 0)
Packages
Speed Grades-1
XMP088 (v1.0)
Notes: 1. Z-7010 in CLG225 has restrictions on PS peripherals, Memory interfaces, and I/Os. Please refer to the Technical Reference Manual for more details.
2. Security block is shared by the Processing System and the Programmable Logic.
3. Equivalent ASIC gate count is dependent of the function implemented. The assumption is 1 Logic Cell = ~15 ASIC Gates.
4. Devices in the same package are pin-to-pin compatible.
5. Static memory interface combined with the usage of many peripherals could require more than 54 I/Os. In that case, the designer can use the Programmable Logic SelectIO interface.
6. Preliminary product information. Subject to change. Please contact your Xilinx representative for the latest information.
sPartan-6 lx anD lxt fPgas
24Important: Verify all data in this document with the device data sheets found at www.xilinx.com
;$6/; ;$6/; ;$6/; ;$6/; ;$6/; ;$6/; ;$6/; ;$6/;7 ;$6/;7 ;$6/;7 &ORFN5HVRXUFHV ,4 ,4 ,4 ,4 ,4 ,4 ,4 ,4 ,4 ,44 4 4 4
sPartan-3 anD sPartan-3e fPgas
25Important: Verify all data in this document with the device data sheets found at www.xilinx.com
;$6 ;$6 ;$6 ;$6 ;$6 ;$6( ;$6( ;$6( ;$6( ;$6(. . . . . . . . . . &ORFN5HVRXUFHV ,4 ,4 ,4 ,4 , ,4 ,4 ,4 ,4 ,4
sPartan-3a anD sPartan-3a DsP fPgas
26Important: Verify all data in this document with the device data sheets found at www.xilinx.com
;$6$ ;$6$ ;$6$ ;$6$ ;$6'$ ;$6'$. . . . . . &ORFN5HVRXUFHV
xa9500xl anD coolrunner-i i families
27Important: Verify all data in this document with the device data sheets found at www.xilinx.com
;$;/ ;$;/ ;$;/ ;$&$ ;$&$ ;$& ;$& ;$& ,4 ,4 ,4 ,4 ,4 ,4 ,4 ,4
xilinx boarDs anD Kits
28Important: Verify all data in this document with the device data sheets found at www.xilinx.com
;,/,1;%2$5'6$1'.,763URGXFW1DPH 3XUSRVH 3DUW1XPEHU 'HYLFHV6XSSRUWHG )HDWXUHV9LUWH[)3*$0/(YDOXDWLRQ.LWZZZ[LOLQ[FRPPO *HQHUDOSXUSRVH)3*$(YDOXDWLRQNLW (.90/* ;&9/;7))* [3&,([SUHVV)0&+3&/3&''562',000%3ODWIRUP)ODVK%3,)ODVK0HPRU\6\VWHP$&(86%7R8$5786%+RVW'HYLFH(WKHUQHW6)3'9,2XW[&KDUDFWHU'LVSOD\9LUWH[)3*$0/&KDUDFWHUL]DWLRQ.LWZZZ[LOLQ[FRPPO *7;&KDUDFWHUL]DWLRQ.LW &.90/* ;&9/;7))* 60$SDLUV6\VWHP$&(FRQWUROOHU6XSHU&ORFNPRGXOHGLIIHUHQWLDO60$FRQQHFWRUSDLUVIRU*7;WUDQVFHLYHUFORFNLQSXWV7KUHH)0&+3&FRQQHFWRUV(DFKZLWKGLIIHUHQWLDOXVHUGHILQHGSDLUVQR*7;WUDQVFHLYHUV86%WR8$57EULGJH9LUWH[)3*$&RQQHFWLYLW\.LW 6HULDO&RQQHFWLYLW\.LWZLWK7DUJHWHG5HIHUHQFH'HVLJQ '.9&211* ;&9/;7))* 0/(.90/*6HULDO&RQQHFWLYLW\)0&0RGXOH+:)0&;0*DQG6HULDO&RQQHFWLYLW\5HIHUHQFH'HVLJQ9LUWH[)3*$(PEHGGHG.LW (PEHGGHG.LWZLWK7DUJHWHG5HIHUHQFH'HVLJQ '.9(0%'* ;&9/;7))* 0/(.90/*(PEHGGHG5HIHUHQFH'HVLJQ9LUWH[)3*$'63.LW '63.LWZLWK7DUJHWHG5HIHUHQFH'HVLJQ $(69'63/;7* ;&9/;7))* 0/(.90/*'635HIHUHQFH'HVLJQ9LUWH[)3*$%URDGFDVW&RQQHFWLYLW\.LW %URDGFDVW&RQQHFWLYLW\.LWZLWK7DUJHWHG5HIHUHQFH'HVLJQ '.9%&&1* ;&9/;7))* 0/(.90/*%URDGFDVW)0&0RGXOHDQG%URDGFDVW5HIHUHQFH'HVLJQ3URGXFW1DPH 3XUSRVH 3DUW1XPEHU 'HYLFHV6XSSRUWHG )HDWXUHV9LUWH[)3*$0/ZZZ[LOLQ[FRPPO *HQHUDOSXUSRVH)3*$GHYHORSPHQWERDUG +:90/81,* ;&9/;))* ''562',000%=%765$00%125)ODVK3ODWIRUP)ODVK3520DQG63,)ODVK0HPRU\6\VWHP$&(&RPSDFW)ODVK-7$*+HDGHURU([WHUQDO-7$*&RQQHFWRU[86%[36(WKHUQHW56[$XGLR,Q2XW'9,9*$9LGHR;*,([SDQVLRQ3RUW9LUWH[)3*$0/ZZZ[LOLQ[FRPPO *HQHUDOSXUSRVH)3*$DQG5RFNHW,2*73GHYHORSPHQWERDUG +:90/81,* ;&9/;7)) ''562',000%=%765$00%/LQHDUSODWIRUPDQG63,IODVK6\VWHP$&(&RPSDFW)ODVK-7$*+HDGHURU([WHUQDO-7$*&RQQHFWRU[86%[36(WKHUQHW56[$XGLR,Q2XW'9,9*$9LGHR;*,([SDQVLRQ3RUW0*7VXSSRUWZLWK3&,([SUHVV6)360$6*0,,9LUWH[)3*$0/ZZZ[LOLQ[FRPPO *HQHUDOSXUSRVH)3*$'63DQG5RFNHW,2*73WUDQVFHLYHUGHYHORSPHQWERDUG +:90/81,* ;&96;7)) ''562',000%=%765$00%/LQHDUSODWIRUPDQG63,IODVK6\VWHP$&(&RPSDFW)ODVK-7$*+HDGHURU([WHUQDO-7$*&RQQHFWRU[86%[36(WKHUQHW56[$XGLR,Q2XW'9,9*$9LGHR;*,([SDQVLRQ3RUW0*7VXSSRUWZLWK3&,([SUHVV6)360$6*0,,9LUWH[)3*$0/ZZZ[LOLQ[FRPPO *HQHUDOSXUSRVH)3*$33&SURFHVVRUDQG5RFNHW,2*7;WUDQVFHLYHUGHYHORSPHQWSODWIRUP +:90/81,* ;&9);7)) ''562',000%=%765$00%/LQHDUSODWIRUPDQG63,IODVK6\VWHP$&(&RPSDFW)ODVK-7$*+HDGHURU([WHUQDO-7$*&RQQHFWRU[86%[36(WKHUQHW56[$XGLR,Q2XW'9,9*$9LGHR;*,([SDQVLRQ3RUW0*7VXSSRUWZLWK3&,([SUHVV6)360$6*0,,9LUWH[)3*$0/ZZZ[LOLQ[FRPPO $GYDQFHGKDUGZDUHVRIWZDUHHPEHGGHGSURFHVVLQJGHYHORSPHQWSODWIRUP +:90/* ;&9);7))* ELWFRPSRQHQW''5PHPRU\DQGELW''5',000%&RPSDFW)ODVKFDUGDQG6\VWHP$&(&RPSDFW)ODVKFRQWUROOHUIRUFRQILJXUDWLRQ7ZRRQERDUG(WKHUQHW3+
xilinx boarDs anD Kits
29Important: Verify all data in this document with the device data sheets found at www.xilinx.com
;,/,1;%2$5'6$1'.,763URGXFW1DPH 3XUSRVH 3DUW1XPEHU 'HYLFHV6XSSRUWHG )HDWXUHV6SDUWDQ)3*$63(YDOXDWLRQ.LWZZZ[LOLQ[FRPVS *HQHUDOSXUSRVH)3*$GHYHORSPHQWERDUG (.663*(.663*--DSDQ ;&6/;&6 2QERDUGFRQILJXUDWLRQFLUFXLWU\4XDG63,IODVK0%0%SDUDOOHO%3,IODVK''5FRPSRQHQWPHPRU\0%6SDUWDQ)3*$63(YDOXDWLRQ.LWZZZ[LOLQ[FRPVS *HQHUDOSXUSRVH)3*$HYDOXDWLRQERDUG (.663*(.663*--DSDQ ;&6/;7)** 2QERDUG-7$*FRQILJXUDWLRQFLUFXLWU\0%3ODWIRUP)ODVK;/4XDG63,IODVK0%6\VWHP$&(*&RPSDFW)ODVKFDUG$YQHW6SDUWDQ/;7'HYHORSPHQW.LWKWWSZZZ[LOLQ[FRPSURGXFWVGHYNLWV$(66'(9/;7*KWP *HQHUDOSXUSRVH)3*$HYDOXDWLRQERDUG $(66'(9/;7* ;&6/;7)** 7KH;LOLQ[6SDUWDQ/;7'HYHORSPHQW.LWSURYLGHVDFRPSOHWHGHYHORSPHQWSODWIRUPIRUGHVLJQLQJDQGYHULI\LQJDSSOLFDWLRQVEDVHGRQWKH;LOLQ[6SDUWDQ/;7)3*$IDPLO\$YQHW6SDUWDQ/;(YDOXDWLRQ.LWKWWSZZZ[LOLQ[FRPSURGXFWVGHYNLWV$(66(9/;*KWP *HQHUDOSXUSRVH)3*$HYDOXDWLRQERDUG $(66(9/;* ;&6/;&6* 8WLOL]LQJ6SDUWDQ$YQHWLQWURGXFHVWKHILUVWHYHUEDWWHU\SRZHUHG;LOLQ[)3*$GHYHORSPHQWERDUGWKH;LOLQ[6SDUWDQ/;(YDOXDWLRQ.LW6SDUWDQ)3*$(PEHGGHG.LWKWWSZZZ[LOLQ[FRPSURGXFWVGHYNLWV'.6(0%'*KWP 6SDUWDQ)3*$(PEHGGHG.LW '.6(0%'*'.6(0%'*--DSDQ ;&6/;7)** (PEHGGHG'HVLJQ3ODWIRUPVHQDEOHUDSLGVRIWZDUHDSSOLFDWLRQGHYHORSPHQWDVZHOODVHDV\FXVWRPL]DWLRQRIWKHSURFHVVRUKDUGZDUHVXEV\VWHPV6SDUWDQ)3*$&RQQHFWLYLW\.LWKWWSZZZ[LOLQ[FRPSURGXFWVGHYNLWV'.6&211*KWP 6SDUWDQ)3*$&RQQHFWLYLW\.LW '.6&211*'.6&211*--DSDQ ;&6/;7)** 7KH6SDUWDQ)3*$&RQQHFWLYLW\NLWLVDFRPSOHWHHDV\WRXVH&RQQHFWLYLW\'HYHORSPHQWDQG'HPRQVWUDWLRQSODWIRUPIRUGHVLJQLQJZLWKVWDQGDUGVEDVHGSURWRFROV3&,H(WKHUQHWLPSOHPHQWLQJORZFRVWSURWRFROEULGJLQJSURYLGLQJKLJKHUHIILFLHQF\DOWHUQDWLYHWR/9'6FRPPXQLFDWLRQHWFLQPXOWLSOHPDUNHWVHJPHQWV6SDUWDQ)3*$'63.LWKWWSZZZ[LOLQ[FRPSURGXFWVGHYNLWV$(66'63/;7*KWP 6SDUWDQ)3*$'63'HYHORSPHQW $(66'63/;7* ;&6/;7 :LUHOHVVDHURVSDFHDQGGHIHQVHLQVWUXPHQWDWLRQDQGPHGLFDOLPDJLQJDSSOLFDWLRQVFRQWLQXHWRGHPDQGJUHDWHUSHUIRUPDQFHWRVXSSRUWVWDQGDUGVZKLOHKLJKOHYHOGHVLJQIORZVFRQWLQXHWRLPSURYHWRSURYLGHDQHDVLHUHQWU\SRLQWIRUXVLQJ)3*$VIRU'636SDUWDQ)3*$,QGXVWULDO(WKHUQHW.LWKWWSZZZ[LOLQ[FRPSURGXFWVGHYNLWV$(66,(./;7*KWP 6SDUWDQ)3*$,QGXVWULDO(WKHUQHW'HYHORSPHW $(66,(./;7* ;&6/;7)** 7KH6SDUWDQ)3*$,QGXVWULDO(WKHUQHW.LWLVDFRPSUHKHQVLYHGHVLJQHQYLURQPHQWIRUUDSLGSURWRW\SLQJDQGGHYHORSPHQWRIOHDGLQJHGJHLQGXVWULDODSSOLFDWLRQVLQFRQQHFWLYLW\PRWRUFRQWURODQGHPEHGGHGSURFHVVLQJ6SDUWDQ)3*$,QGXVWULDO9LGHR3URFHVVLQJ.LWKWWSZZZ[LOLQ[FRPSURGXFWVGHYNLWV$(66,9./;7*KWP 6SDUWDQ)3*$,QGXVWULDO9LGHR3URFHVVLQJ $(66,9./;7)** ;&6/;7 7KH6SDUWDQ)3*$,QGXVWULDO9LGHR3URFHVVLQJ.LWLVDFRPSUHKHQVLYHGHVLJQHQYLURQPHQWIRUUDSLGSURWRW\SLQJDQGVWUHDPOLQHGGHYHORSPHQWRIKLJKUHVROXWLRQYLGHRFRQIHUHQFLQJYLGHRVXUYHLOODQFHDQGPDFKLQHYLVLRQV\VWHPV6SDUWDQ)3*$&RQVXPHU9LGHR.LWKWWSZZZ[LOLQ[FRPSURGXFWVGHYNLWV7%6&9.KWP 6SDUWDQ)3*$&RQVXPHU9LGHR 7%6&9. ;&6/;7 6SHHGXSGHYHORSPHQWRIYLGHRDOJRULWKPVDQGLQFRUSRUDWHWKHODWHVWYLGHRLQWHUIDFHVWDQGDUGVULJKWRXWRIWKHER[7KH6SDUWDQ)3*$&RQVXPHU9LGHR.LWLVDFRPSUHKHQVLYHGHVLJQHQYLURQPHQWIRUGHYHORSLQJDQGGHEXJJLQJDGYDQFHGYLGHRDOJRULWKPV3URGXFW1DPH 3XUSRVH 3DUW1XPEHU 'HYLFHV6XSSRUWHG )HDWXUHV
6SDUWDQ)3*$'HYHORSPHQW%RDUGVDQG.LWV
6SDUWDQ)3*$'HYHORSPHQW.LWV6SDUWDQ$)3*$6WDUWHU.LWZZZ[LOLQ[FRPVDVWDUWHU /RZFRVW6SDUWDQ$)3*$ERDUGHYDOXDWLRQNLW +:63$5$6.81,* ;&6$)* (YDOXDWLRQERDUGZLWK6SDUWDQ$)3*$RQERDUG(WKHUQHW3+
xilinx boarDs anD Kits
30Important: Verify all data in this document with the device data sheets found at www.xilinx.com
;,/,1;%2$5'6$1'.,763URGXFW1DPH 3XUSRVH 3DUW1XPEHU 'HYLFHV6XSSRUWHG )HDWXUHV&RRO5XQQHU,,&3/'6WDUWHU.LW)HDWXULQJWKH'DWD*$7(/RZ3RZHU$GYDQWDJHZZZ[LOLQ[FRPSURGXFWVGHYNLWV6.&5,,/*KWP *HQHUDOSXUSRVH&3/'HYDOXDWLRQERDUG 6.&5,,/* ;&&74 &RPSOHWHRXWRIWKHER[HYDOXDWLRQSODWIRUP&RRO5XQQHU,,&3/'XWLOLW\ZLQGRZ(DV\VHWXSDQGPRQLWRULQJ'DWD*$7(HYDOXDWLRQVZLWFK)UHHUHIHUHQFHGHVLJQV3URGXFW1DPH 3XUSRVH 3DUW1XPEHU 'HYLFHV6XSSRUWHG )HDWXUHV)0&'HEXJ0H]]DQLQH&DUGZZZ[LOLQ[FRPSURGXFWVGHYNLWV+:)0&'%**KWP )0&;0'HEXJ0H]]DQLQH&DUG +:)0&;0* 9,7$)0&+3&FRQQHFWRU6LQJOHHQGHGVLJQDOVIURPWKHFDUULHUERDUGFORFNV-7$*DQGSRZHUVLQJOHHQGHG,2SDLUVRQWKH/3&SLQVVLQJOHHQGHG,2SDLUVRQWKH+3&SLQV0LFWRUFRQQHFWRUSLQVIHPDOH0LFWRUFRQQHFWRU)0&;0&RQQHFWLYLW\&DUGZZZ[LOLQ[FRP[P )0&&RQQHFWLYLW\ +:)0&;0* 7KH)0&;0&RQQHFWLYLW\&DUGLVGHVLJQHGWRSURYLGHDFFHVVWRHLJKWVHULDOWUDQVFHLYHUVRQWKH)0&+3&FRQQHFWRUIRXQGRQ;LOLQ[)0&VXSSRUWHGERDUGVLQFOXGLQJ9LUWH[0/7KHVHHLJKWVHULDOWUDQVFHLYHUVFDQEHDFFHVVHGWKURXJKRQH&;[WUDQVFHLYHUVWZR6$7$[WUDQVFHLYHUVDQGHLJKW60$[WUDQVFHLYHUVFRQQHFWRUV;03Y)0&'DXJKWHUFDUGV
&3/'6WDUWHU.LWV
;03Y ,PSRUWDQW9HULI\DOOGDWDLQWKLVGRFXPHQWZLWKWKHGHYLFHGDWDVKHHWVIRXQGDWZZZ[LOLQ[FRP
xilinx iP cores, reference Designs, anD instructor leD training courses
31Important: Verify all data in this document with the device data sheets found at www.xilinx.com
$GYDQFHG,34XLFNO\DQGHDVLO\VHDUFKIRU,3&RUHVIURP;LOLQ[DQGLWVUGSDUW\DOOLDQFHSDUWQHUVDWZZZ[LOLQ[FRPLSFHQWHU5HIHUHQFH'HVLJQV5HIHUHQFH'HVLJQVFDQEHIRXQGXQGHUWKH7RSLFVWDERIWKH'RFXPHQWDWLRQ&HQWHUZZZ[LOLQ[FRPGRFXPHQWDWLRQ)3*$&XUULFXOXP /HDUQLQJ/HYHO,6('HVLJQ7RRO)ORZ'HVLJQLQJZLWK9HULORJ'HVLJQLQJZLWK9+'/)3*$'HVLJQIRU$6,&8VHUV'HVLJQLQJZLWKWKH9LUWH[DQG6SDUWDQ)DPLOLHV(VVHQWLDOVRI)3*$'HVLJQ'HVLJQ7HFKQLTXHVIRU/RZHU&RVW'HEXJJLQJ7HFKQLTXHV8VLQJWKH&KLS6FRSH3UR7RROV'HVLJQLQJIRU3HUIRUPDQFH'HVLJQLQJZLWKWKH3ODQ$KHDG$QDO\VLVDQG'HVLJQ7RRO7057RRO$GYDQFHG)3*$,PSOHPHQWDWLRQ
;,/,1;,3&25(65()(5(1&('(6,*16DQG,16758&725/('75$,1,1*&2856(6
,QVWUXFWRU/HG7UDLQLQJ&RXUVHV5HFRPPHQGHG&RXUVHZDUH(OHFWLYH&RXUVHZDUH
;03Y ,PSRUWDQW9HULI\DOOGDWDLQWKLVGRFXPHQWZLWKWKHGHYLFHGDWDVKHHWVIRXQGDWZZZ[LOLQ[FRP
$GYDQFHG9+'/(PEHGGHG+DUGZDUH&XUULFXOXP /HDUQLQJ/HYHO(PEHGGHG6\VWHPV'HYHORSPHQW $GYDQFHG(PEHGGHG6\VWHPV'HYHORSPHQW (PEHGGHG6RIWZDUH&XUULFXOXP /HDUQLQJ/HYHO(PEHGGHG6\VWHPV6RIWZDUH'HYHORSPHQW (PEHGGHG2SHQ6RXUFH/LQX['HYHORSPHQW &RQQHFWLYLW\&XUULFXOXP /HDUQLQJ/HYHO'HVLJQLQJD/RJL&25(3&,([SUHVV6\VWHP'HVLJQLQJZLWK0XOWL*LJDELW6HULDO,2'HVLJQLQJZLWK(WKHUQHW0$&&RQWUROOHUV6LJQDO,QWHJULW\DQG%RDUG'HVLJQIRU;LOLQ[)3*$V'63&XUULFXOXP /HDUQLQJ/HYHO'63'HVLJQ8VLQJ6\VWHP*HQHUDWRU ;03Y
;03Y ,PSRUWDQW9HULI\DOOGDWDLQWKLVGRFXPHQWZLWKWKHGHYLFHGDWDVKHHWVIRXQGDWZZZ[LOLQ[FRP
xilinx ProDuctiVity aDVantage
32Important: Verify all data in this document with the device data sheets found at www.xilinx.com
;LOLQ[3URGXFWLYLW\$GYDQWDJH;3$ ZZZ[LOLQ[FRP[SD
Corporate HeadquartersXilinx, Inc.2100 Logic DriveSan Jose, CA 95124USATel: 408-559-7778www.xilinx.com
EuropeXilinx EuropeOne Logic DriveCitywest Business CampusSaggart, County DublinIrelandTel: +353-1-464-0311www.xilinx.com
JapanXilinx K.K.Art Village Osaki Central Tower 4F1-2-2 Osaki, Shinagawa-kuTokyo 141-0032 JapanTel: +81-3-6744-7777japan.xilinx.com
Asia Pacific Pte. Ltd.Xilinx, Asia Pacific5 Changi Business ParkSingapore 486040Tel: +65-6407-3000www.xilinx.com
Copyright 2013 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. ARM Cortex, MPCore, and CoreSight are trademarks of ARM in the EU and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of PCI-SIG. All other trademarks are the property of their respective owners.Distributed by:
DISCLAIMER
The information disclosed to you hereunder (the Materials) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications: http://www.xilinx.com/warranty.htm#critapps.
AUTOMOTIVE APPLICATIONS DISCLAIMER
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III) USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.