Multi-Disciplinary Engineering Design ConferenceKate Gleason College of Engineering

Rochester Institute of TechnologyRochester, New York 14623

Project Number: 07301

ADAPTABLE DATA ACQUISITION (DAQ) WITH CONTROL OUTPUT MODULE

Mohammed Al-Shehri - EE Zakariya Al-Sulaimi - EEJason Hayes - EE Andrew Keegan - EE

Henry Li - EE Daniel Pintar - CEIan Weber - CE

ABSTRACT

Although modular data acquisition systems are available on the market, users often encounter issues of cost and scalability for complex applications. The goal of this design project was to develop a versatile open-architecture data acquisition and control output system centered around the PC104 processor platform. Input and output subsystems were developed to operate together or separately with the PC104 platform and a power board. The input subsystem was designed to allow simultaneous storage of 16 TTL/CMOS digital inputs and 16 analog voltage inputs. Analog inputs were split into two 8 channel blocks, each of which being conditioned by circuitry on a user selected daughter board. The design had to accommodate analog inputs ranging from 0V to 12V with 12 bit resolution and 20K sps/ch. The output subsystem was designed to provide 16 TTL/CMOS digital outputs, 8 analog voltage outputs, and 8 analog current outputs for control applications. Voltage outputs had to operate in the range 0-5 V or +/-15 V with 12 bit resolution and 100 hz/ch. Current outputs were required to meet the 4-20 mA current loop standard with 8 bit resolution and 100 hz/ch. Initial software development was focused on demonstrating functionality. Future users will be able to customize this aspect of the DAQ system. The development and result of the 07301 project will be addressed thoroughly in this paper.

INTRODUCTION

The sponsor of this project, Dr. Hensel, was originally interested in the development of an open architecture

data acquisition system to be implemented on robotic platforms; these platforms being the culmination of several other senior design projects. When the usefulness of such a system was evaluated, it was determined that an adaptable data acquisition system could be used for many applications throughout the engineering department. The scope of the project was broadened to include general use for any design project as well as student lab and faculty bench test conditions.

The primary goal of the project was to design a system to meet the desired specifications and build one working prototype on PCB. A working prototype includes analog input with signal conditioning, digital I/O, current loop output, analog voltage output, along with all controlling and interfacing software. A secondary goal was to provide the interface and case to implement the system with the robotic platforms.

Many data acquisition and control output systems are available from manufacturers including Omega, and National Instruments. For example, National Instruments offers a USB M Series Multifunction DAQ. The system has 32 analog inputs, 4 analog outputs, and 48 digital I/O channels [1]. Nevertheless, analog inputs are expected to be pre-conditioned and the analog output does not provide many channels. Many expensive systems including input, output, and conditioning would have to be purchased for school projects and lab use. Also, software is not fully customizable with a commercial system. Clearly, a robust open-architecture solution is necessary to satisfy the largest number of possible uses.

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NOMENCLATURE

ADC: Analog-to-digital converterCPLD: Complex programmable logic deviceCSV: Comma separated variableDAC: Digital-to-analog converterDAQ: Data acquisitionI/O: Input/outputIC: Integrated circuitISA: Industry standard architecturePC104: Compact single board computerPCB: Printed circuit boardTTL/CMOS: Industry standard digital protocolUSB: Universal serial busdaughter board: An interchangeable boardhz/ch: Hertz per channelsps/ch: Samples per second per channel

CONCEPT DEVELOPMENT

Customer Needs Assessment

The first step in the concept development phase was to fully understand the customer needs. A needs assessment list was constructed with five sections; I/O capabilities, physical constraints, data capabilities, power, and PC104 processor.

Original I/O capabilities included 24 analog voltage inputs, 16 digital inputs, 24 analog voltage outputs, 24 analog current outputs and 16 digital outputs. During the design process the analog voltage and current output requirements were reduced to 8 channels due to complexity and cost. The analog voltage input requirement was later reduced to 16 channels due to space constraints of the circuit board. Table 1 displays the final I/O specifications.

Function Channels Range Performance Resolution

Analog Voltage Input

16 0-12 V 20 K sps/ch 12 bit

Digital Input

16 TTL/ CMOS

100 hz/ch N/A

Analog Voltage Output

8 0-5, +/-12 V

100 hz/ch 12 bit

Analog Current Output

8 4-20 mA

100 hz/ch 8 bit

Digital Output

16 TTL/ CMOS

100 hz/ch N/A

Table 1 – Refined Customer Specifications

The main physical requirement was that designed boards must be able to stack on the provided PC104

Lynx board supplied through VersaLogic. The dimensions of the PC104 board were approximately 4x4 inches. Figure 1 displays an image of the PC104 platform. Any daughter boards needed to be smaller than the main boards as well as being easily interchangeable. The last physical concerns were noise and temperature. It was decided that the system would operate in a case that would provide both signal shielding and general cooling, but that this was not part of the responsibility for this project.

Figure 1 – VersaLogic Lynx PC104 Platform

Desired data capabilities included conditioning of signals and storage to memory. Conditioning was to be done on the modular daughter boards. After passing through interfacing circuitry to the PC104, 2 GB of local flash memory was available to store data. This data needed to be stored in a convenient format that would later be loaded to a personal computer. Of course, it was also desirable to maximize data transfer speeds from the DAQ.

Efficiency was the foremost concern for power circuitry. Bench tests would be able to use a wall powered supply, but mobile applications would run from a rechargeable 12 V battery. The efficiency of the power circuitry would determine run time from a battery as well as the physical constraint of temperature. The desired run time for the system was one hour.

The first requirement for the PC104 processor was that it operate with less than 25% of full processor usage. This was desirable in case other boards outside of the system needed to use the same processor. Next, the PC 104 platform needed to run LINUX to maintain the goal of a fully open-architecture system. Software needed to be developed to interface from the PC104 to the designed boards as well as a computer for data storage.

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Concept Generation and Selection

The next step of the development process was to decide upon a general system architecture that would meet the customer needs. Due to the required specifications for I/O and PC104 usage there were not many possible variations in the general architecture of the system. Interfacing from the designed circuitry to the PC104 was decided to be done through CPLDs. The use of CPLDs would help in reducing the load on the PC104 processor. In order to maximize versatility it was decided that the power, input, and output subsystems would be on separate stackable boards. Breaking the system up in this manner also helped in dividing design tasks into teams.

Digital inputs were assumed to be preconditioned so interfacing with the PC104 through the input CPLD was the only design consideration. The analog inputs needed to be conditioned, filtered, changed to a digital representation, and interfaced with the PC104. The order of these requirements was decided based on data flow. The final solution involved filtering of input signal, followed by conditioning on daughter boards. The daughter board circuitry would also implement analog multiplexers so that the data would be easily convertible. The next step was to convert the serial analog signal to digital and finally to interface to the PC104 through the CPLD.

Figure 2 – High Level System Architecture

The digital output simply needed to interface with the PC104 through the output CLPD and then pass through buffers. The voltage output had to interface with the CPLD, followed by digital to analog conversion, and circuitry to make the range selectable. The current loop output would also begin at the CPLD and go through digital to analog conversion. Then the analog voltage needed to be converted to current in the specified range. Figure 2 shows a block diagram of the high level system architecture.

CIRCUIT DESIGN

Input

Every element of the input board was designed primarily to provide accurate digital signals to be collected by the PC104. Each component has the potential to distort all inputs to the DAQ board, so careful consideration was taken in choosing every part. Besides all design-based decisions listed below, factors considered in choosing every component included availability and cost.

The first component each incoming signal comes in contact with is the input connector. The main factors considered when choosing the input connectors were signal accuracy and connector size. When acquiring data from a thermocouple, it is essential to limit the distance between the thermocouple itself and the circuitry used for cold-junction compensation. Thus, thermocouples must be directly connected to the actual input board. It was decided that terminal blocks with screw-down clamping inputs would be used for all inputs. To stay within the size constraints around the perimeter of the PC104 board, it was decided to use eight two-level four-input screw-clamp terminal blocks (Phoenix Contact 1725012) as input connectors. Although these connectors are relatively bulky, they provide a direct, secure connection to the input board for any wire connection from 14 gauge down to 26 gauge.

The only other component required for digital inputs, since it was assumed that these inputs are preconditioned, was a multiplexer to reduce the number of input lines to the PC104. Since all analog inputs are split into two groups of eight multiplexed signals for conditioning, it was decided to use eight-to-one multiplexers for the digital inputs to synchronize the digital and analog input timing. To meet the sampling rate requirement of 20K sps/ch, the maximum propagation delay of each MUX was calculated to be 625 ns. A digital MUX (Fairchild MM74HC151MTC) with a propagation delay 26 ns was chosen to meet all of these specifications. All remaining parts on the input board were chosen specifically for the analog inputs.

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The next element encountered by each analog signal is the anti-aliasing filter. Aliasing is the distortion of an analog signal after being sampled by an ADC at a rate that is slow relative to the frequency of the signal. With proper design, these low-pass filters can eliminate the possibility of aliasing. In ideal conditions, the Nyquist rate can be used to determine the maximum input frequency for a given ADC. Nyquist states that the sampling frequency must be at least twice that of the analog signal frequency. When dealing with realistic conditions, signal noise and non-ideal hardware can create parasitic, high frequency signals that can cause aliasing even when following Nyquist’s rule. For this reason, it is common practice to use a 2nd order low-pass filter with a cutoff frequency approximately 1/10th that of the sampling frequency. The order of the filter directly affects the phase shift in signal frequency, the rate at which a signal attenuates at high frequencies, and the complexity of the circuit. Following this standard, a 2nd order Sallen-Key low-pass filter with a cutoff frequency of approximately 2.5 KHz was designed. Figures 3 and 4 display associated circuitry and simulation results for the filter. After conforming to standard resistor (10 KΩ) and capacitor (10 nF and 4.7 nF) values, the resulting filter had a cutoff around 2.4 KHz. It was necessary to filter each individual signal prior to being multiplexed because each MUX was to be switched at a frequency much greater than 2.4 KHz. Filtering the signals after being multiplexed would attenuate each signal down to almost 0 V. Having sixteen 2nd order filters, each consisting of two resistors, two capacitors, and an op-amp, meant that the size of each component must be kept to a minimum. Thus, it was decided to use quad op-amp chips, size 0805 resistors, and size 0603 capacitors. Using the same quad op-amp chips as the output board (Texas Instruments LM324) would reduce the cost per board if this DAQ board was to go into mass production, so these chips were used on the input board as well. Figure 3 shows the simulated behavior of this filter as frequency increases.

Frequency

100Hz 300Hz 1.0KHz 3.0KHz 10KHz 30KHz 100KHz 300KHz 1.0MHzDB(V(U1A:OUT))

-80

-60

-40

-20

-0

20

(2.3904K,-3.0112)

Fig. 3. Anti-aliasing filter AC sweep response.

The next stage on the input board is the signal conditioning. Different sensors require different signal conditioning circuitry, and some sensors have

differential inputs that occupy two input connections rather than one. To keep the board modular, it was decided to do all analog multiplexing and signal conditioning on two eight-input interchangeable daughter boards. For this project, daughter boards were designed for thermocouples, which are differential sensors, and single input sensors that require no external conditioning. The thermocouple daughter board consists of a 4:1*2 MUX (Analog Devices AD7502 with two sets of inputs, four inputs each, and two outputs) and a cold-junction compensation chip (Analog Devices AD595), compatible with types K and T thermocouples, with serial output that also provides gain for the small thermocouple signal. The other daughter board consists only of an eight-to-one analog MUX (Analog Devices ADG408). Both analog multiplexers chosen have switching rates fast enough to maintain the 20 ksps/ch specification

Since this board was designed to accommodate any type of sensor, the magnitude of each input signal can vary considerably. A programmable gain chip (Analog Devices AD526), with selectable gain of 1X, 2X, 4X, 8X, and 16X, was chosen to boost the input signals if needed. This chip can be controlled completely with software and does not require any external hardware circuitry.

The final component of the input board before each signal is transferred to the PC104 is the ADC. The main specifications to be met with the ADC were having 12 bit inputs at a sampling rate of 20 ksps/ch. Since the inputs have already been multiplexed, a 12 bit, serial in, serial out ADC (Texas Instruments TLV2541) with a sampling rate of 200 ksps (resulting in 25 ksps/ch when sampling from eight sensors) was chosen. This concludes the design of the input board. Figure 4 shows the actual input board with daughter boards.

Fig. 4. Input Board with Daughter Boards

Output

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The initial goal for the analog voltage output was to have 8 channels that could either output with a range of 0-5 V or with a range of +/-12 V. After initial design attempts it became apparent that any design with a selectable output would be both complex and costly. Mainly due to cost, the design was changed to have 4 channels in the 0-5 V range and 4 channels in the +/-12 V range. The CPLD provides a serial digital input to a 12 bit resolution DAC from Analog Devices after receiving data from the PC104. The DAC selected for the voltage output was able to sink and source 10mA/ch as specified in the project readiness package. Once the serial data is converted to analog voltage, 4 channels are fed directly to an output connector. These lines are the 0-5V outputs. The +/-12 V range is accomplished by using the other four DAC outputs along with the 0-5 V outputs lines as reference in an operational amplifier configuration. Basically, the +/-12 V outputs are scaled from the 0-5 V lines.

The current loop outputs were designed to comply with the industry standard 4-20 mA range. In general, current levels are much easier to maintain that voltage over wires which travel a long distance to a control destination. Similar to the voltage output, the CPLD communicates a serial digital signal from the PC104 to a DAC. In this case the DAC had 8 bit resolution and was from Texas Instruments. The DAC outputs voltages which are used to produce a proportional current by way of operational amplifiers in a transconductance configuration. Each voltage-to-current transition makes use of a 249 Ω resistor with 1% tolerance. The output current is simply the voltage from the DAC divided by the 249 Ω resistor. Of course, a 250 Ω precision resistor would be ideal, but the slight decrease in accuracy was worth the significant cost savings. The controlling software is responsible for assuring that the output does not go out of range. As long as the DAC output voltages stay in the range 1-5 V, the current output will be in the range 4-20 mA. Actual output ranges were calculated to be 0.996-4.980 V corresponding to 4.000-20.001 mA if the resistor is exactly 249 Ω.

Fig. 5 – Current Output DAC TimingFigure 5 displays a timing diagram for the output DAC. Each segment represents one data word being transferred to an internal register in the DAC. A falling edge of the frame sync control signal causes the process to start. After all of the bits in the sixteen bit

word have transferred, the internal register shifts data to a channel specific holding register based on the four most significant bits, D15 to D12. Eight of the remaining bits, specifically D11 to D4, describe the output voltage. The remaining four bits are ignored for the 8-bit resolution model. A load sequence is initiated when all eight holding registers contain values. It takes approximately 3 us from the falling edge of the a_i_ldac_L signal for the settled output voltage to be simultaneously generated on each channel. Once the voltages are present, they remain constant until the next falling edge of the load D/A signal.

The total time required to fill all eight holding registers is 6.75 us. Each channel would operate just over 100 kHz with a load sequence that accounts for the 3 us settling time. The DAC timing for the analog voltage output is essentially identical to that of the current output. However, the data word representation is different. The analog voltage output requires 12 bits of resolution so bits D11 to D0 are all used to describe the voltage. Bits D14 to D 12 are used to route incoming data according to the register map. The most significant bit, D15, is set to logic 0 for normal operating conditions. The analog voltage DAC will enter a control mode when bit D15 is high.

Digital outputs run directly from the CPLD to buffers from Texas Instruments and then to an output connector. The buffers serve to protect and ensure proper drive of the digital outputs. The buffers were actually high-speed CMOS logic hex inverting Schmitt triggers. The max propagation delay of 205 ns should have little effect in most applications.

All connectors chosen for the output board were 2.00 mm right-angle headers. The input board was designated as the top of the stack due to daughter boards so all parts on the output board had a vertical limit of 0.6 in., the approximate height of the PC104 connector. If desired, a breakout board could easily be designed that would take a ribbon cable connection from the output board and space the lines apart to terminal blocks. Figure 6 displays the prototype output PCB board.

Fig. 6 – Populated Output Board

Power Management

Copyright © 2007 by Rochester Institute of Technology

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There are two main goals of the power subsystem: voltage conversion and normalized voltage at a designated level. The desired voltage levels for the entire DAQ are 5 V, +15 V, -15 V, and a reference 5 V. It is given that the input to the DAQ is a single 12 V DC source under battery operated conditions. The power regulation has to accommodate the possible voltage drop from the input. The power subsystem is responsible for the power supply of all boards including the PC104.

Voltage conversion involves both step-down and step-up DC to DC. For step-down, the Buck converter is used to convert 12 V to 5 V. The converter chosen has a wide range of input, which goes from 5.5 V to 36 V. The current rating of the converter is 3 A, which covers the requirement of the totally current drawn Input, Output, and PC104 boards. The output of the Buck converter also goes to a reference 5 V and the Boost converter.

The Boost converter is used to step-up from 5 V to +15 V, which are required for amplifiers. The input to the Boost is 5 V, which comes directly from the Buck converter. In addition to flexibility, the values of the output can be adjusted simply by changing the bulk resistors on the board. To obtain a clean DC output, two high value capacitors are placed in parallel to reduce the output ripple. Having high capacitance at the output would slow down the transient response. The board is designed to optimize the balance between output ripple and transient response. This design can be easily optimized in respect to the tolerance ratings in the design specification.

The layout of the board uses conducting plates with round corners to ensure good conductions. The Buck converter is rated up to 95% power efficiency. The Boost converter also has a high efficiency of 85%.

Fig. 7 – Populated Power Board

SOFTWARE DESIGN

CPLD

The goal of the CPLD design for both the input and the output board was to make the circuitry on each of the boards independent of the program running on the CPLD. A CPLD was chosen because it doesn’t need extra FLASH memory to keep the program when the power is turned off, which in turn would cut down on the number of components populating each board. The initial CPLD chosen was a 288 gate, 5 V CPLD. It was chosen due to the large number of gates and because the on-board circuitry runs off of 5V. However, it was determined that the physical size of the CPLD was too large to fit on the boards. Instead, a 144 gate, 5V CPLD was chosen. The smaller size would fit better with the rest of the devices. Unfortunately, the HDL design is too large to fit on a CPLD and an FPGA with external memory would have been better suited for the task.

Due to time constraints, the design for the input board was split up into three modules to be loaded into the CPLD. Each of these three modules read from a set of four inputs. One set is for digital inputs, another for the analog daughter board 1, and the last for the analog daughter board 2.

The digital module sends the control signals to the digital multiplexer to cycle through the four inputs to be read. The CPLD then reads the data serially for twelve, 16 MHz clock cycles, with one bit of data read each clock cycle. The data is then stored, 12 bits in parallel. The PC104 interface then waits for the PC104 to request a piece of data by sending the read signal low. The interface then reads the address bus, and depending on that picks the appropriate data in storage to send to the PC104.

The both of the analog modules behave similarly to the digital module. The only difference is that the reader block of the module also contains an enable signal for the analog to digital converters for each corresponding module. Also the reader block for the analog modules contains a 4 us delay for each data read. This ensures that the data going into the digital to analog converters is valid. After the 4 us delay, the modules read their respective inputs serially for 12 bits and stores the data in parallel. The PC104 interface behaves the same way as that from the digital module.

PC104One of the main goals of the project was to use all open source tools and software. The PC104 required an operating system to run algorithms and to control the data flow throughout the system. Keeping in mind the limited storage capacity of the PC104, Voyage, an open source embedded version of the Linux operating system was chosen. It is based off the Debian Linux distribution and is considered a lightweight operating

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system due to the exclusion of many non-essential applications such as a graphical desktop.

Using the C programming language, an application was created that would accomplish three main tasks. First, it is responsible for communicating with the end-user. It would collect the relevant information needed for the collection of data such as the number of inputs being used, the sample rate, and run time. A simple text menu was created that presented the user with a list of options and settings. It is also used to begin data collection and is the vehicle that sends collected data to a PC.

Its second task is to communicate to the PC104 via the ISA bus. This is done by sending an address, which indicates to the PC104 which data it wants to receive. When the appropriate write and read bits are set, the CPLD responds with the data. This ask and receive method is used for every piece of data that the PC104 requires. This is done because of the many available configurations that are available to the user.

Its third task is to organize the data in a way so that it would be relevant to the end-user. Since the data is organized in an array format, it is an easy task to transform the data into a format that is easily read by a PC. It can be formatted in an open source spreadsheet format such as a comma separated values file.

PCB LAYOUT

Printed circuit board layouts were done using PCB123 schematic capture and layout programs. Originally, OrCAD Capture CIS was used for schematic capture of the subsystems. An attempt was made to produce layout netlist files through this software, but many errors with IC model parameters impeded the process. The next step taken was to redraw all schematics in the PCB123 software. Blocks containing pin assignments were made for all of the ICs. Once the schematics were complete, netlists were output and uploaded into the PCB123 layout software. Conveniently, a board template with the PC104 dimensions and ISA bus connector were available. However, IC footprints found on the web were not in a compatible format. Each IC footprint was made manually using the physical specifications found in datasheets.

The input and output boards required six layers for adequate routing of traces. Each board used one layer for ground and one layer for power in order to reduce the number of traces. Layout of traces from the CPLD to the ISA bus was very similar for the two boards. This accounted for about half of the pins on the CPLD. The other half differed based on the design of the input and output subsystems. The power board layout also made use of the PC104 template but only required two layers. The polygon function was used throughout

the power board layout to ensure robustness of design. The usual traces may not have been sufficient for power lines carrying a heavy load. Figure 8 shows a sample of the layouts. The thermocouple and pass through daughter board layouts were done on 2x2 in. boards with two layers.

Fig. 8 –PCB Layouts

RESULTS AND CONCLUSIONS

Method

Most hardware testing was done on breadboards because controlling software for the active components was still in development stages. The design and function of ADC and DAC components have been tested by their respective manufacturers. They will work as long as the correct software control is applied and part is not defective. Initial tests of the ADC and DAC components were set up in Quartus II by interfacing with an Altera University Program Design Laboratory Package. It was assumed during hardware test that the ADC and DAC components would perform as expected. Therefore, the input subsystem was set up on a breadboard starting with anti-aliasing filters and ending with the daughter board circuitry. Thermocouple inputs were tested. The output board was tested by breadboarding each op-amp configuration separately. Again, it was assumed that the correct voltages would be output by each DAC. The power board was the only PCB tested because it didn’t require any software control to function. The main power components were tested on a breadboard separately to assure proper function before the PCB was even designed.

For the software portion of the project, a Xilinx CPLD design board was used to provide the CPLD. The CPLD on the board that was used was the Coolrunner

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II chip. The design loaded into the chip was a sample code to recognize addresses from the PC104 and provide dummy data to the PC104. The PC104 program was set up to provide the addresses for the CPLD and read the respective data. After data was read the program created a .CSV file for data verification. The first column of the .CSV will contain data from address 1, the second column from address 2, and so on until column and address 8.

Outcome

On the input side, anti-aliasing did work with a cutoff frequency near 2.5 kHz. Variable gain successfully multiplied input signals accurately up to 16X. Thermocouple sensing worked at 0.01V/degC. All multiplexers including pass through worked.

The current output worked with very low error up to about 400 Ω (calculated was 680 Ω) assuming correct input from the DAC. The 0-5 V voltage outputs are directly from DAC. An op-amp configuration scaled 0-5 V line to approx +/-13 V. Resistor values can easily be changed to get the desired +/-12 V range.

For the power board, the main +5 V line worked with a degraded supply as low as 6 V. Boost conversion was successful for -15 V, but the +15 V line did not work. Surface mount issues are the most likely cause of any power board failures. Solder and trace shorts, or damaged components should be investigated.

On the software end, sample data successfully was read and stored in .CSV format. A power issue with CPLD test board sometimes interfered with operation of code causing it to crash. A proof of the concept has been achieved, and future development should go on without any major problems.

Overall, the design of each subsystem was proven to be functional. However, a significant amount of troubleshooting and tweaking will be necessary before a working system can be implemented by other design teams. The project concept was certainly feasible.

RECOMMENDED FUTURE WORK

The selected CPLD was found to be insufficient to handle all of the simultaneous data flow. A FPGA could be integrated into the design to solve this problem. The desire to load data from the PC104 to the PC was not met due to time restrictions. This minor software development should be fairly easy to implement. Additionally, software to allow real time transfer of data to the output needs to be developed. This was not a requirement for the 07301 project.

Physically, it would be beneficial to space out the daughter board connectors on the input board. Currently, two daughter boards will fit at the same time but part and connector placement must be carefully designed to avoid shorting. Additional physical work includes the design and fabrication of a breakout board. This board would take header connections from the output board and route traces to terminal blocks. There was not enough space on the board for terminal blocks due the requirement to make the system stackable.

It is important to note that the board layouts were done in separate files. The time restriction of the quarter made it impossible to combine boards in a single file because each group member was simultaneously working on their respective subsystems. In the future, board layouts with the same number of layers should be combined into one file to save money. For example, the power board and daughter board layouts could have been ordered with one file. If done correctly, the boards will be carefully cut apart after production. Possible issues with this approach include confusion when initially sorting parts for the layout and the inability to use board templates.

ACKNOWLEDGMENTS

The team would like to thank Dr. Edward Hensel, sponsor and customer of the project, as well as Professor George Slack for project guidance and technical input. Significant technical contributions were made by Prof. John Wellin (application perspective, sensors), Dr. Mark Hopkins (anti-aliasing filters), Dr. Marcin Lukowiak (CPLD implementation), Mr. Dave Hassett (CPLD design), Mr. Scott Ingram (CPLD Design), Mr. John Martellaro (Linux), Dr. Eric Peskin (UP board), Dr. Daniel Phillips (functionality), and Dr. Dorin Patru (A/D D/A conversion). Mr. Ali Almaher assisted the team by designing the DAQ logo. Also, Mr. Ken Snyder assisted the team with ordering of PCB boards and parts. The team would like to extend its thanks to, Dr. James Moon, Dr. Roy Melton, and Dr. Pratapa Reddy for attending design reviews and lending their professional opinions. Finally, special thanks to Sunstone Circuits for donations toward PCB prototype boards.

REFERENCES

[1] “NI USB-6229 - USB M Series Multifunction DAQ,” 2007. http://www.ni.com/dataacquisition

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