Principles Of Digital Design - CECSgajski/eecs31/slides/Digital_Design_-_Flip-Flops... · Principles of Digital Design Created Date: 10/31/2011 11:41:48 AM

Copyright © 2010-2011 by Daniel D. Gajski EECS31/CSE31, University of California, Irvine

Principles Of Digital Design

Flip-Flops

Clocks

Latches Flip-flops State diagrams

Copyright © 2010-2011 by Daniel D. Gajski EECS31/CSE31, University of California, Irvine 2

Logic gates and flip-flops

Topic preview

Boolean algebra

Finite-state machine

Logic design techniques

Binary system and data

representation

Generalized finite-state machines

RTL Combinatorial components

Sequential design techniques

RTL storage components

Register-transfer design

Processor components


Sequential components contain memory elements The output values of sequential components depend on the

input values and the values stored in the memory elements The values in the memory elements define the state of

sequential components Example : Ring counter that starts the answering machine after

4 rings Sequential components can be (1) asynchronous or (2) synchronous Asynchronous sequential components change their state and

output values as a response to change in input values Synchronous sequential components change their state and

output values at fixed points of time defined by the clock signal

Sequential components


Clock period ( measured in micro, nano seconds ) is the time between successive transitions in the same direction Clock frequency ( measured in MHz, GHz ) is the reciprocal of clock period Clock width is the time interval during which clock is equal to 1 Duty cycle is the ratio of the clock width and clock period Clock signal is active high if the changes occur at the rising edge or during the clock width Clock signal is active low otherwise

Clock period

Clock width

Rising edge Falling edge

Clock signal


SR-latch ( NOR implementation ) •SR-latch has two states: (1) set state (Q=1) and (2) reset state (Q=0)

Timing diagram

Undefined

Undefined

S

R

Q

Q’

2.8

2.8

2.8

2.8

1.4

1.4

1.4

1.4

1.4

1.4

1.4

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

S

R

Q’

Q

Logic schematic

1.4

1.4

0 0 1 (hold) 0

Q’ (next)

Truth table

1 1 0 0

S

1 0 1 0

R

X X X

0

Q Q (next)

1

0 (?) 0 0 (set) 1

0 0 (hold) 1

1 (reset)


Gated SR-latch •Control signal C activates the latch

S

R

C Q

Q’

Graphic symbol 1 1 0 0

0 1 X X X 1

0 1 0

0 0 1 X X 0 X X Q S R

(?) NA 1 (set) 1 1

(reset) 0 1 1 0 1 0

Q(next)

(hold) (hold)

(inactive) (inactive)

1 1 0 0 C

Truth table

C

S

R

Q 2.0 4.0 2.0 4.0

reset state set state reset state

Timing diagram

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13

tsetup thold

Logic schematic

S

R Q

Q’

C

2.0

2.0


Gated D-latch

D

C

Q

Q’

Graphic symbol

1 X X

0 1 X 0 X Q D

1 0 1 0

Q(next)

1 1 0 0 C

Truth table

•Setup time is minimum time inputs must be stable before C

•Hold time is minimum time inputs must be stable after C

•Q follows D while C is asserted as long as D satisfies setup and hold time restrictions

Timing diagram tsetup thold

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9

C

D

Q 3.0 4.0 2.0 4.0

reset state set state reset state

tsetup thold tsetup thold

Logic schematic

D Q

Q’

C

2.0

2.0


Flip Flops

• Latches are level-sensitive since they respond to input changes during clock width.

• Latches are difficult to work with for this reason.

• Flip-Flops respond to input changes only during the change in clock signal.

• They are easy to work with though more expensive than latches.

• Several styles of flip-flops are available.

(1) master-slave (MS)

(2) edge-triggered (ET)

(3) …


Erroneous shifting with D-latches

Note: Low-to-high delay is 4.0ns. High-to-low delay is 3.0ns.

Logic schematic

D

C

Q2 4.0/3.0

D

C

Q3 4.0/3.0

D

C

Q1 4.0/3.0

Y X

Clk

•Erroneous operation is possible with level-sensitive latches

Timing diagram

X

Clk

4.0

4.0

4.0

3.0

3.0

3.0

t0 t1 t2 t3 t4 t5 t6 t7

Q1

Q2

Q3


Master-slave flip-flop •In a MS flip-flop D is sampled and stored at the rising edge (low-to-high) of the Clk signal

Logic schematic

Q D

C 4.0/3.0

D

C 4.0/3.0

D

Clk

Master latch

Slave latch

Qm Qs

Timing diagram

Clk

D

4.0 3.0 4.0

4.0 3.0 5.0 4.0 Qm

Qs

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9


Shifting with master-slave flip-flops

Timing diagram

X

Clk

4.0

4.0

3.0

3.0

5.0 4.0

4.0 3.0

5.0 4.0

4.0

Q1m

Q1s

Q2m

Q2s

Q3m

Q3s

t0 t1 t2 t3 t4 t5 t6 t7

Logic schematic

Y X

Clk

D

C 4.0/3.0

D

C 4.0/3.0

Q1n Q1s

Master-slave flip-flops

D

C 4.0/3.0

D

C 4.0/3.0

Q2n Q2s


D

C 4.0/3.0

D

C 4.0/3.0

Q3n Q3s



Flip-flop types

S

R

Clk Q

Q’

D Clk

Q

Q’

Flip-flop name

Flip-flop symbol

Characteristic table

Characteristic equation

Excitation table

1 1 0 0 S

1 0 1 0 R Q(next)

Q 0

NA 1

1 0

D Q(next)

0 1

1 1 0 0 Q

1 0 1 0

Q(next) R S X 0 0 1

0 X 1 0

1 1 0 0 Q

1 0 1 0

Q(next) D 0 1

1 0

Q(next)=S+R’Q

SR=0

Q(next)=D

SR

D

Note: For master-slave flip-flops data inputs must satisfy set-up and hold time constraints.

S=0

Q=0 Q=1

S,R=1,0

S,R=0,1

D=0

Q=0 Q=1

D=1

D=0

State diagram

State diagram D=1

R=0


A latch / flip-flop with asynchronous inputs

D Q

Q’

C

PRS

CLR

D latch Graphic symbol

D

C

Q

Q’

PRS

CLR


Summary

We introduced memory elements Latches (asynchronous) Flip-flops (synchronous)

We presented several ways to describe memory

elements Characteristic tables Characteristic equations State diagrams Timing diagrams

We introduced the concept of a state diagram >> FSM

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Principles Of Digital Design - CECSgajski/eecs31/slides/Digital_Design_-_Flip-Flops... · Principles of Digital Design Created Date: 10/31/2011 11:41:48 AM