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Inventing the Future of Computing
Presenting the ParallellaAndreas Olofsson
ARM Festival at MITMay 19th, Cambridge, MA
What is Adapteva
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Company History:• Fabless semiconductor company founded in 2008 • 16-core 65nm Epiphany-III chip product sampling since May 2011• 64-core 28nm Epiphany-IV chip product sampling since July 2012• Parallella open computing platform launched in October 2012
Notable Achievements:• #1 in microprocessor energy efficiency• 4 chips on $2.5M in raised capital• $2M in total revenue to date• 5K customers, 6,300 boards pre-sold• 18 Patents pending
The Mobile Energy Crisis: IT’S REAL!!
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1990 1995 2000 2005 2010 2015 2020 2025 2030
System ProcessingNeedsLegacy ProcessingEfficiency
“The Efficiency Gap”Von NeumannSaturation
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Power Consumption
Thermal Density
Memory Bottlenecks
Latency Wall
Wiring
Frequency Wall
Yield Issues
Time to Market
Software Complexity
Amdahl’s Law
Trends that will shape the future of computing
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The Solution: True Heterogeneous Computing
SYSTEM‐ON‐CHIP
BIGCPU
FPGA
BIGCPU
BIGCPU
BIGCPU
100’s of small RISC CPUsGPU Analog
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The Accelerator Challenge
LimitedAccelerator
ApplicationMove Data
Application
Context SwitchMove Data
Context SwitchMove Data
Context Switch
LimitedAccelerator
Application
Context SwitchMove Data
Something Else
Something Else
Status Quo Approach (~1.3X speedup)
“Smart”Coprocessor
ApplicationMove Data
Application
Context SwitchMove Data
Context Switch
Something Else
Smart Coprocessor (>10X speedup?)
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Epiphany Multicore Technology
10X Boost in Energy Efficiency
True Task Parallel Coprocessor
Coprocessor for ARM/x86/MIPS Host
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Epiphany: A Truly Scalable Architecture
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4,096
16,384
GFLOPS
# Epiphany CoresPerformance
0.35W
1.4W
5.7W
23W
92W
10‐20x
A Single Unified Instruction Set Architecture!
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Epiphany Programming ModelsMODEL#2
WORKER BEE MODEL• Great for up to 2GFLOPS• Supports standard C/C++• “Cloud on a chip”
MODEL #1DATA PARALLEL MODEL
• openCL programmable• Easy integration with C/C++• openMP/MPI roadmap
MINICPU
MINICPU
MINICPU
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MINICPU
MINICPU
MINICPU
MINICPU
MINICPU
MINICPU
MINICPU
MINICPU
MINICPU
MINICPU
MINICPU
MINICPU
X86/ARM/FPGA Host
Task1
Task3Task4
Task2
MINICPU
MINICPU
MINICPU
MINICPU
MINICPU
MINICPU
MINICPU
MINICPU
MINICPU
MINICPU
MINICPU
MINICPU
MINICPU
MINICPU
MINICPU
MINICPU
X86/ARM/FPGA HostTask1
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Parallella: (Super) Computing Boards
Rj45
USB
GPIO
GPIO
ZYNQ(ARM)CPU
E64
1GB SDRAM
uSD
HDMI
USB
• OPEN! (and free):• Documentation• Board design files• Drivers• Software Tools
• Accessible (No NDAs!)• $100 entry point
IO IO
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Kickstarter Campaign Stats
• 5,000 customers• 6,300 boards ”pre-sold” in 4 weeks• 67 countries, all 50 US states• 50-75% of backers are developers• 4,000 more signups since Jan 1st
• Customer Application Classes:• SDR• Ray tracing/rendering• Image processing• Robotics• Gaming
• Cryptogrophy• Media Server• Distributed Computing• Signal processing• HPC
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Parallella Specifications (goals)• Zynq 7010/7020 SOC (Dual core Arm A9 with FPGA logic)• 16/64 core Epiphany accelerator (32 bit floating-point/integer)• 1GB DDR3L SDRAM• 1 Gbit Ethernet• Micro USB port (2)• Micro HMDI port• Micro SD card• 6GB/sec board connector• ~5Watt typical power
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We Need Help!
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• Plese come talk to us if you have expertise/interest in:• Linux drivers/BSPs• Ubuntu RFS• Building Beowulf type clusters, bencharmks (linpack)• OpenCL, MPI, openMP, parallel programming in general• Multicore synchronization libraries• Embedded vision applications (openCV like)• FPGA design• Board design• System validation, optimization• VLSI design• Manufacturing/test
For More Information• Epiphany Architecture Reference Manual (PDF)
• Epiphany SDK Reference Manual (PDF)
• Epiphany‐III Datasheet (PDF)
• Parallella Reference Manual (PDF)
• Using a Scalable Parallel 2D FFT for Image Enhancement (source code)
• Scalable Parallel Multiplication of Big Matrices (source code)
• Epiphany Drivers (source code)
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• Go to http://parallella.org or http://adapteva.com for more info info