Presentation ID ' 2001, Cisco Systems, Inc. All rights ...grouper.ieee.org/groups/1149/6/doc/Cisco_IBP_1149_6_Mar_08.pdf · Logic 1 or 0 Data Out Logic 1 or 0 VOUT VIN VCM VGND Common

111© 2001, Cisco Systems, Inc. All rights reserved.Presentation_ID

222Input Test Buffer Design Examples www.acextest.org

Input Test Buffer :Design Examples and Fault Syndromes

ASIC DFT Group

Sang Baeg and Sung Chung


P1149.6 AC Boundary-Scan

AC_EXTEST

1149.6

Well, AC coupling seems OK


Problem Transmission Lines

Data InLogic 1 or 0

Data OutLogic 1 or 0

VOUTVIN

VCM

VGND

Common Ground Return

Signal Line

Driver Receiver

Logic 1 or 0

Data InLogic 1 or 0

Data OutLogic 1 or 0

VOUT

VDiff

VCM

VGND

Common Ground Return

Signal LinePositive

Diff.Driver

Diff.Receiver

Logic 1 or 0VCM

Signal LineNegative

Logic 1 or 0

2 LogicStates

8 LogicStates

2 LogicStates

FaultMask

4 LogicStates


Error Population

Logical Link

Value

Physical Link and Transport Layer Value

Single Ended

Differential Signal

Possible logic stateLogic state with single

error condition

Transmitter

0 0, 1Positive 0, 0, 1, 1 Positive 0, 0, 1

Negative 0, 1, 0, 1 Negative 0, 1, 1



Receiver





Available logic states 2 4 8 6

Error Population 50% 75% 66.6%


Null Detection Range Definition

Diff. input IN_P

Diff. input IN_N

Reset withoutnull state

Inp

ut

Th

resho

ldR

ang

e

Nu

llD

etection

Ran

ge

Set withoutnull state

Null StateActive State

Set withnull state

Reset withnull state

Zero DifferentialVoltage

Out of Null detection range

Out of Null detection range

Null State

Active State

Active State

ReceiverVI H Range

ReceiverVI L Range


Null Detection Methodology

Diff.inputIN_P

Diff.inputIN_N

Inp

ut

Th

resho

ldR

ang

e

Out of Nulldetection

range


range

ZeroDifferential

Voltage

ReceiverVI L Range

ReceiverVI H Range


Nu

llD

etection

Ran

ge

Signal withoutnull state

Signal withnull state

Signal withnull rangeHysteresis

Signal withthreshold range

Hysteresis


Null Detection Window Variation

Diff.inputIN_P

Diff.inputIN_N

Input

Threshold

Range


range


range

ZeroDifferential

Voltage

ReceiverVI L Range

ReceiverVI H Range


Null

DetectionR

ange

Signal withnull state

Signal with75% input range

Hysteresis

Signal withthreshold range

Hysteresis

Signal with90% input range

Hysteresis

75% to 90% input signal range

75% to 90% input signal range


Hysteresis vs Window Comparator

• Large Hysteresis will not trigger when there is a null

• May require known initial value

• Memory effect doesn’t allow capturing of real time logic

status

• Window Comparator is preferred

With AC_EXTEST, DC Status sample is possile


Input Test Buffer: Basic Architecture

_

+

_

+

50

50

1 K

1 K

2 K

2 K

IN_P

IN_N

Reset

Set

Vicm

A

B

VaOptional

Vcom

R1

R2

R3

R4

Vicm - A >= Window

Vicm - B >= Window

_

+

_

+

IN_P

IN_NReset

Set

Common ModeVoltage Point

2 K

1 K

1 K

2 K

A

B

R1

R2

R3

R4

IN_P - A >= Window

IN_N - B >= Window

Input threshold range is 1/3 of input differential signal range


Input Test Buffer: Differential Receiver 1

_

+

_

+

50

50

1 K

1 K

2 K

2 K

IN_P

IN_N

OptionalVcom

Reset

Set

Vicm

A

B

Va

_

+

Reset

Set

R1

R2

R3

R4

Comp1

Comp2

_

+Comp3

Comp4

A - Vicm >= Window

Vicm - A >= Window

Vicm - B >= Window

B - Vicm >= Window

Set

Rst

Q

Q

Rst

Set

Q

Q

Preferred SignalRecoverinterface


_

+

B - IN_N >= Window

_

+

_

+

IN_P

IN_N

IN_P - A >= Window

Reset

Set

Common ModeVoltage Point

2 K

2 K

1 K

1 K

Va

R1

R2

R3

R4

Vicm

_

+

Set

Reset

A

B

Comp1

Comp2

Comp3

Comp4

IN_N - B >= Window

A - IN_P >= Window Rst

Set

Q

Q

Set

Rst

Q

Q



Two scan cell interface capable input test buffer examples with

differential receiver

• Both examples retain the same test

coverage

• No diagnosability improvement

• No apparent benefit


Input Test Buffer: Differential Receiver 2

_

+

_

+

50

50

1 K

1 K

1 K

1 K

IN_P

IN_N

OptionalVcom

Reset

Set

Vicm

A

B

Va

_

+Reset

_

+Set

R1

R2

R3

R4

Comp1

Comp2

Comp3

Comp4

IN_N - C >= Window

C

D

Vicm - D >= Window

Vicm - A >= Window

IN_P - B >= Window

R5

R6

1 K

1 K

Rst

Set

Q

Q

Set

Rst

Q

Q



Third and forth variation of differential input test buffer for two boundary-

scan cell interface, no coverage and diagnosability difference

_

+

_

+

_

+

50

50

1 K

1 K

1 K

1 K

IN_P

IN_N

OptionalVcom

Reset

Vicm

A

B

Va

Reset

_

+Set

R1

R2

R3

R4

Comp1

Comp2

Comp3

Comp4

C

D

Vicm - A >= Window

IN_P - B >= Window

R5

R6

1 K

1 K

Set

D - Vicm >= Window

C - IN_N >= Window

Set

Rst

Q

Q

Set

Rst

Q

Q



Two scan cell interface capable input test buffer examples with

differential receiver


Input Test Buffer: Combination

_

+

_

+

50

50

1 K

1 K

1 K

1 K

IN_P

IN_N

Vref

Reset

Set

A

BVa

_

+Reset

_

+Set

R1

R2

R3

R4

Comp1

Comp2

Comp3

Comp4

IN_N - C >= Window

C

D

B - D >= Window

C - A >= Window

IN_P - B >= Window

R5

R6

2 K

2 K

OptionalVcom

Input Test Buffer

• Combination input test

buffer with fixed Vref for

two scan cell interface

• Improved diagnosability


Input Buffer Overview

Input Test Buffer

Integrator

DetectorsSignal RecoverShort / Null DetectorAC Detector

_

+

_

+Set

ResetQ

Q

AC CouplingCapacitor

Null ReceiverTechnology

MapperShort / Null

Detector AC Detector Integrator

MSAinput ACScan Cell

AC Pattern Clock

DC ShortDetect

AC Short /Null Detect

ScanInterface

Reset

Set

Q

Q

D

Clk

Lo

gic

al L

ink

TransmissionLayer

Dif

fere

nti

alD

rive

r

LogicalLinkInput Test Buffer / Detectors / Integrator : Physical LinkPhysical

Link

SignalRecover

Detectors

DC Test

AC Test

Input Test BufferDC_Short

DC_Test_Data

No_AC_Detect

AC_Test_Data

AC_Short

DC_Data

AC_Data

Technology Mapper

AC Short / Null DetectDC Short Detect

Scan Cell


Null Receiver to Scan Cell Interface

• Null Receiver to Boundary-scan Cell

DC Boundary-scan and AC_EXTEST Diagnosis

• Signal Recover to Boundary-scan Cell

Interface to two Scan-cell per differential channel

May require AC detector / encoder circuit

• Integrator to Boundary-scan Cell

Interface to single Scan-cell per differential channel


Signal Transition and Recovery

Positive Inputsignal before

Capacitor

Positive signalafter Amplifier(Null Receiver)

Positive signal afterTechnology Mapper

Negative Inputsignal before

Capacitor

Negative signalafter Amplifier(Null Receiver)

Negative signal afterTechnology Mapper

Recovered Signalat Recover


Signal Recovery

Input Output

Reset / Set Q QB

0 / 0 Q QB

0 / 1 1 0

1 / 0 0 1

1 / 1 0 0

Input OutputRecovered

dataAC short

statusDC short

statusAC

detectorResult

Reset / Set

Q / QB

0 / 0 Q QB Hold 1 1 0/1 1

0 / 1 1 0 D 0 0 0 D

1 / 0 0 1 D 0 0 0 D

1 / 1 0 0 0 0 1 1 1


Fault Syndrome Summary

Same pulse atboth inputs

Skewed pulseat one input

No pulse or nullat one input

No pulse or nullat both inputs

Different slopat one input

Fault freenormal pulseat both inputs • Normal, out of phase pulse pair

• Same phase pulse pair

• Skew pulse at one input

• No pulse at one input

• No pulse at both inputs

• Slow or Fast signal decay at one input


Large-RC Example

Set

Reset

Q ( = 0 )

QB ( = 1 )

Sample Point

Set

Reset

Q ( = 1 )

QB ( = 0 )

Sample Point

Set

Reset

Q ( = V )

QB ( = VB )

Sample Point

Set

Reset

Q ( = 0 )

QB ( = 0 )

Sample Point

Case:Normal signalat both inputs

Case:Same signal

at both inputsV

V

V

V V

V

V

V

V

V

Set

Reset

Q ( = 1 )

QB ( = 0)

Sample Point

Set

Reset

Q ( = 0 )

QB ( = 0 )

Sample Point

Case:Skewed signal

at one input


Small-RC Example

Set

Reset

Q ( = 0 )

QB ( = 1 )

Sample Point

Set

Reset

Q ( = 1 )

QB ( = 0 )

Sample Point

Set

Reset

Q ( = V )

QB ( = VB )

Sample Point

Set

Reset

Q ( = V )

QB ( = VB )

Sample Point

Case:Normal signalat both inputs

Case:Same signal

at both inputsV

V

V

V

V

V

V

V

V

V

Set

Reset

Q ( = 1 )

QB ( = 0)

Sample Point

Set

Reset

Q ( = 0 )

QB ( = 0 )

Sample Point

Case:Skewed signal

at one input

V

V


Set Delayed Signal Recovery: Optional

Set

Reset

Q ( = 1 )

QB ( = 0 )

Sample Point

Set

Reset

Q ( = 1 )

QB ( = 0 )

Sample Point

Case:Same signal

at both inputs

Set

Reset

Q ( = 1 )

QB ( = 0 )

Sample Point

Set

Reset

Q ( = 0 )

QB ( = 0 )

Sample Point

Case:Same signal

at both inputs

Short / NullDetector

DC ShortDetect

AC Short /Null Detect

_

+

_

+Set

ResetQ

Q

Null ReceiverTechnology

MapperSignal

Recover

Input Test Buffer

AC_Short

DC_Short

AC_Test_Data

DC_Test_Data

Delay

Physical Link

Unit delay in the “Set” signal path makes the signal recovery into Set Priority Latch


Capacitive Short Detection: Optional

Set

Reset

SOT

RET

Sample Point

PatternClock

Reset

Set

Q

Q

D

Clk

Reset

Set

Q

Q

D

Clk

Set

Reset

DifferentCapacitor

Odd TCK

Even TCK

SOT(Set on Odd TCK)

RET(Reset on Even TCK)

More than ¼ Pattern Clock Cycle difference can be detected


Single Scan Cell Interface

_

+

_

+

50

50

1 K

1 K

2 K

2 K

IN_P

IN_N

Reset

Set

Vicm

A

B

VaOptional

Vcom

R1

R2

R3

R4

Vicm - A >= Window

Vicm - B >= Window

Input Test Buffer

DC Short DetectDC_Short

DC_Test_Data

Set

Rst

Q

Q

D

Clk

Q

Q No_

AC

_Det

ect

AC Short Null / Detect

AC Detector

AC_Test_Data

AC_Short

DC_Data

AC_DataD

Clk

Q

Q

D

Clk

Q

Q

01 0

1

to nextcell

AC_SyncAC_Test_Ran

from last cell

ClockDRShiftDR

AC Pattern Clock

Detectors

Integrator

Scan CellBC_4

SignalRecover


Dual Scan Cell Interface 1

_

+

_

+

50

50

1 K

1 K

2 K

2 K

IN_P

IN_N

Reset

Set

Vicm

A

B

VaOptional

Vcom

R1

R2

R3

R4

Vicm - A >= Window

Vicm - B >= Window

Input Test Buffer

DC_Data_P

AC_Data_PD

Clk

Q

Q

D

Clk

Q

Q

01 0

1

to nextcell

AC_SyncAC_Test_Ran

ClockDRShiftDR

AC Pattern Clock

Integrator

Scan CellBC_4

DC_Data_N

AC_Data_ND

Clk

Q

Q

D

Clk

Q

Q

01 0

1

from last cell

Integrator

Scan CellBC_4

Set

Rst

Q

Q

D

Clk

Q

Q No_AC_Detect

AC Detector

Detectors

SignalRecover



DC_Data_P

AC_Data_PD

Clk

Q

Q

D

Clk

Q

Q

01 0

1

to nextcell

AC_SyncAC_Test_Ran

ClockDRShiftDR

AC Pattern Clock

Integrator

Scan CellBC_4

DC_Data_N

AC_Data_ND

Clk

Q

Q

D

Clk

Q

Q

01 0

1

from last cell

IntegratorScan Cell

BC_4

Set

Rst

Q

Q

D

Clk

Q

Q

No_

AC

_Det

ect

AC Detector

Detectors

SignalRecover

Set

Rst

Q

Q

SignalRecover

_

+

_

+

50

50

1 K

1 K

1 K

1 K

IN_P

IN_N

Vref

Reset

Set

A

BVa

_

+Reset

_

+Set

R1

R2

R3

R4

Comp1

Comp2

Comp3

Comp4

IN_N - C >= Window

C

D

B - D >= Window

C - A >= Window

IN_P - B >= Window

R5

R6

2 K

2 K

OptionalVcom

Input Test Buffer




DC_Test_Data

Set

Rst

QQ

No_AC_Detect

AC Detector

AC_Test_Data

DC_Data

AC_DataD

Clk

Q

Q

D

Clk

Q

Q

01 0

1

to nextcell

AC_SyncAC_Test_Ran

ClockDR

ShiftDR

AC Pattern Clock

Detectors

Integrator

Scan CellBC_4


DC_Test_Data

Set

Rst

Q

Q

No_AC_Detect

AC Detector

AC_Test_Data

DC_Data

AC_DataD

Clk

Q

Q

D

Clk

Q

Q

01 0

1

from last cell

AC Pattern ClockDetectors

IntegratorScan Cell

BC_4

SignalRecover

SignalRecover

DClk

QQ

DClk

QQ

_

+

_

+

50

50

1 K

1 K

1 K

1 K

IN_P

IN_N

Vref

Reset

Set

A

BVa

_

+Reset

_

+Set

R1

R2

R3

R4

Comp1

Comp2

Comp3

Comp4

IN_N - C >= Window

C

D

B - D >= Window

C - A >= Window

IN_P - B >= Window

R5

R6

2 K

2 K

OptionalVcom

Input Test Buffer


1nF and 50 AC Coupling: 20 MHz TCK ?

100

0

16.66

33.33

50.00

66.66

83.33

1 2 3 4 5 6RC Time Constant

75%0.287 RC

50%0.693 RC 33.3%

1.098 RC99.2%5 RC

Am

plit

ud

e

Threshold range

For 1 nF coupling capacitor, 33% decay is 1.098 RC (54.9nS) and 50% decay takes 34.65 nS. Min TCK will be 1/(0.693 RC) = 20.88MHz

Documents

Presentation ID ' 2001, Cisco Systems, Inc. All rights ...grouper.ieee.org/groups/1149/6/doc/Cisco_IBP_1149_6_Mar_08.pdf · Logic 1 or 0 Data Out Logic 1 or 0 VOUT VIN VCM VGND Common