A B SUM CARRY

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

HALF ADDER:LOGIC DIAGRAM: TRUTH TABLE:

ADDERS design using VHDL

Dataflow Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity hadd is Port ( a : in std_logic; b : in std_logic; sum : out std_logic; carry : out std_logic);end hadd;architecture dataflow of hadd isbeginsum <= a xor b;carry <= a and b;end dataflow;

Behavioral Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity haddbehavioral is Port ( a : in std_logic; b : in std_logic; sum : out std_logic; carry : out std_logic);end haddbehavioral;architecture Behavioral of haddbehavioral isbeginp1:process (a,b)beginsum<= a xor b;carry<= a and b;end process p1;end Behavioral;

Structural Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity haddstructural is Port ( a : in std_logic; b : in std_logic; sum : out std_logic; carry : out std_logic);end haddstructural;architecture structural of haddstructural iscomponent xor2port(a,b:in std_logic; z:out std_logic);

end component;component and2port(a,b:in std_logic; z:out std_logic);

end component;beginx1: xor2 port map (a,b,sum);a1: and2 port map (a,b,carry);end structural;

and2 component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity and2 is Port ( a : in std_logic; b : in std_logic; z : out std_logic);end and2;architecture dataflow of and2 isbeginz<= a and b;end dataflow;

xor2 component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity xor2 is Port ( a : in std_logic; b : in std_logic; z : out std_logic);end xor2;architecture dataflow of xor2 isbeginz<= a xor b;end dataflow;

TEST BENCH(VHDL): LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.all;USE ieee.numeric_std.ALL;ENTITY test_bench_vhd ISEND test_bench_vhd;ARCHITECTURE behavior OF test_bench_vhd IS

COMPONENT haddPORT(

a : IN std_logic;b : IN std_logic; sum : OUT std_logic;carry : OUT std_logic);

END COMPONENT;--InputsSIGNAL a : std_logic := '0';SIGNAL b : std_logic := '0';--OutputsSIGNAL sum : std_logic;SIGNAL carry : std_logic;

BEGIN-- Instantiate the Unit Under Test (UUT)uut: hadd PORT MAP(

a => a,b => b,sum => sum,carry => carry

);tb : PROCESSBEGIN

a<='0'; b<='0'; wait for 100 ps;

a<='0'; b<='1'; wait for 100 ps; a<='1'; b<='0'; wait for 100 ps;

a<='1'; b<='1'; wait for 100 ps;

END PROCESS;END;

Simulation output:

Synthesis RTL Schematic:

MULTIPLEXER:

LOGIC DIAGRAM:

128

9

128

9

Y

D0

D1

12

D2

D3

S0

128

9

S1

12

128

9

23

45

1

TRUTH TABLE:

SELECT INPUT OUTPUT

S1 S0 Y

0 0 D0

0 1 D1

1 0 D2

1 1 D3

Dataflow Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity mux_dataflow is Port ( d : in std_logic_vector(3 downto 0); s : in std_logic_vector(1 downto 0); y : out std_logic);end mux_dataflow;architecture dataflow of mux_dataflow issignal s0bar,s1bar,p,q,r,st:std_logic;beginp<= d(0) and s0bar and s1bar;q<= d(1) and s0bar and s(1);r<= d(2) and s(0) and s1bar;st<= d(3) and s(0) and s(1);s0bar<= not s(0);s1bar<= not s(1);y<= p or q or r or st;end dataflow;

Behavioral Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity mux_behv is Port ( d : in std_logic_vector(3 downto 0); s : in std_logic_vector(1 downto 0); y : out std_logic);end mux_behv;architecture Behavioral of mux_behv isbeginp1:process(d,s)beginif (s(0)<='0' and s(1)<='0') theny<=d(0);elsif (s(0)<='0' and s(1)<='1') theny<=d(1);elsif (s(0)<='1' and s(1)<='0') theny<=d(2);elsey<=d(3);end if;end process p1;end Behavioral;

Structural Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity mux_struct is Port ( d : in std_logic_vector(3 downto 0); s : in std_logic_vector(1 downto 0); y : out std_logic);end mux_struct;architecture structural of mux_struct iscomponent not1port(a:in std_logic; z:out std_logic);end component;component and3port(a,b,c:in std_logic; z:out std_logic);end component;component or4port(a,b,c,d:in std_logic; z:out std_logic);end component;

signal s0bar,s1bar,p,q,r,st:std_logic;beginn1:not1 port map (s(0),s0bar);n2:not1 port map (s(1),s1bar);a1:and3 port map (d(0),s0bar,s1bar,p);a2:and3 port map (d(1),s0bar,s(1),q);a3:and3 port map (d(2),s(0),s1bar,r);a4:and3 port map (d(3),s(0),s(1),st);o1:or4 port map (p,q,r,st,y);end structural;

Dand3 component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity and3 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; z : out std_logic);end and3;architecture dataflow of and3 isbeginz<=a and b and c;end dataflow;

not1 component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity not1 is Port ( a : in std_logic; z : out std_logic);end not1;architecture dataflow of not1 isbeginz<= not a;end dataflow;

or4 component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity or4 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; d : in std_logic; z : out std_logic);end or4;architecture dataflow of or4 isbeginz<=a or b or c or d;end dataflow;

TEST BENCH(VHDL):LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.all;USE ieee.numeric_std.ALL;ENTITY test_vhd ISEND test_vhd;ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT mux_dataflow

PORT(d : IN std_logic_vector(3 downto 0);s : IN std_logic_vector(1 downto 0); y : OUT std_logic);

END COMPONENT;--InputsSIGNAL d : std_logic_vector(3 downto 0) := (others=>'0');SIGNAL s : std_logic_vector(1 downto 0) := (others=>'0');--OutputsSIGNAL y : std_logic;

BEGIN-- Instantiate the Unit Under Test (UUT)uut: mux_dataflow PORT MAP(

d => d,s => s,y => y

);tb : PROCESSBEGIN

d<="0101";s<="00"; wait for 100ps;d<="0011";s<="01"; wait for 100ps;d<="1110";s<="10"; wait for 100ps;END PROCESS;

END;

Simulation output:

Synthesis RTL Schematic:

DEMULTIPLEXER

LOGIC DIAGRAM:

Y0

S1 S0

Din

Enable

23

45

1

23

45

1

23

45

1

12

Y1

23

45

1

Y2

12

Y3

TRUTH TABLE:

INPUT OUTPUT

D S0 S1 Y0 Y1 Y2 Y3

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1

Dataflow Modeling:

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity demux_dataflow is Port ( d : in std_logic; s : in std_logic_vector(1 downto 0); z : out std_logic_vector(3 downto 0));end demux_dataflow;architecture dataflow of demux_dataflow issignal s0bar,s1bar:std_logic;begins0bar<= not s(0);s1bar<= not s(1);z(0)<=d and s0bar and s1bar;z(1)<=d and s0bar and s(1);z(2)<=d and s(0) and s1bar;z(3)<=d and s(0) and s(1);end dataflow;

Behavioral Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity demux_behv is Port ( d : in std_logic; s : in std_logic_vector(1 downto 0); z : out std_logic_vector(3 downto 0));end demux_behv;architecture Behavioral of demux_behv isbeginp1:process(d,s)beginif (s(0)<='0' and s(1)<='0') thenz(0)<=d;z(1)<='Z';z(2)<='Z';z(3)<='Z';elsif (s(0)<='0' and s(1)<='1') thenz(0)<='Z';z(1)<=d;z(2)<='Z';z(3)<='Z';elsif (s(0)<='1' and s(1)<='0') thenz(0)<='Z';z(1)<='Z';z(2)<=d;z(3)<='Z';

elsez(0)<='Z';z(1)<='Z';z(2)<='Z';z(3)<=d;end if;end process p1;end Behavioral;

Structural Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity demux_struct is Port ( d : in std_logic; s : in std_logic_vector(1 downto 0); z : out std_logic_vector(3 downto 0));end demux_struct;architecture structural of demux_struct iscomponent not1port(a:in std_logic; z:out std_logic);end component;component and3port(a,b,c:in std_logic; z:out std_logic);end component;signal s0bar,s1bar:std_logic;beginn1:not1 port map (s(0),s0bar);n2:not1 port map (s(1),s1bar);a1:and3 port map (d,s0bar,s1bar,z(0));a2:and3 port map (d,s0bar,s(1),z(1));a3:and3 port map (d,s(0),s1bar,z(2));a4:and3 port map (d,s(0),s(1),z(3));end structural;

and3 component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity and3 is Port ( a : in std_logic; b : in std_logic; c : in std_logic; z : out std_logic);end and3;architecture dataflow of and3 isbeginz<=a and b and c;end dataflow;

not1 component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity not1 is Port ( a : in std_logic; z : out std_logic);end not1;architecture dataflow of not1 isbeginz<= not a;end dataflow;

TEST BENCH(VHDL):LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.all;USE ieee.numeric_std.ALL;ENTITY test_vhd ISEND test_vhd;ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)COMPONENT demux_dataflowPORT(

d : IN std_logic;s : IN std_logic_vector(1 downto 0); z : OUT std_logic_vector(3 downto 0));

END COMPONENT;--InputsSIGNAL d : std_logic := '0';SIGNAL s : std_logic_vector(1 downto 0) := (others=>'0');--OutputsSIGNAL z : std_logic_vector(3 downto 0);

BEGIN-- Instantiate the Unit Under Test (UUT)uut: demux_dataflow PORT MAP(

d => d,s => s,z => z

);tb : PROCESSBEGIN

d<='1'; s<="00"; wait for 100ps;d<='0'; s<="01"; wait for 100ps;d<='1'; s<="10"; wait for 100ps;END PROCESS;

END;

Simulation output:

Synthesis RTL Schematic:

FLIP FLOPS

SR FLIPFLOP:

LOGIC DIAGRAM:

1

23

Q

R

S

1

23 Q

CP

1

23

1

23

TRUTH TABLE:

Q(t) S R Q(t+1)

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 X

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 X

Behavioral Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity srff is Port ( s : in std_logic; r : in std_logic; clk : in std_logic; rst : in std_logic; q : inout std_logic; qbar : inout std_logic);end srff;architecture Behavioral of srff isbeginprocess(s,r,clk,rst,q,qbar)beginif (rst='1') thenq<='0';qbar<='1';elsif (clk='1' and clk'event) thenif (s='0' and r='0') thenq<=q;qbar<=qbar;elsif (s='0' and r='1') thenq<='0';qbar<='1';elsif (s='1' and r='0') thenq<='1';qbar<='0';

elseq<='X';qbar<='X';end if;end if;end process;end Behavioral;

TEST BENCH(VHDL):LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.all;USE ieee.numeric_std.ALL;

ENTITY test_vhd ISEND test_vhd;ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT srffPORT(

s : IN std_logic;r : IN std_logic;clk : IN std_logic;rst : IN std_logic; q : INOUT std_logic;qbar : INOUT std_logic);

END COMPONENT;--InputsSIGNAL s : std_logic := '0';SIGNAL r : std_logic := '0';SIGNAL clk : std_logic := '0';SIGNAL rst : std_logic := '0';--BiDirsSIGNAL q : std_logic;SIGNAL qbar : std_logic;

BEGIN-- Instantiate the Unit Under Test (UUT)uut: srff PORT MAP(

s => s,r => r,clk => clk,rst => rst,q => q,qbar => qbar

);tb : PROCESS

BEGIN clk<='0'; wait for 50ps;

clk<='1'; wait for 50ps;end process;rst<='1','0' after 200ps;tb1:processbegins<= '1' , '0' after 400ps;r<= '1' , '0' after 300ps , '1' after 500ps;wait for 1ns;END PROCESS;

END;

JK FLIPFLOP:LOGIC DIAGRAM:

CP

128

9

1

23

1

23

Q

128

9 Q

K

J

TRUTH TABLE:

Q(t) J K Q(t+1)

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0

Behavioral Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity jkff is Port ( j : in std_logic; k : in std_logic; clk : in std_logic; rst : in std_logic; q : inout std_logic; qbar : inout std_logic);end jkff;architecture Behavioral of jkff isbeginprocess(j,k,clk,rst,q,qbar)beginif (rst='1') thenq<='0';qbar<='1';elsif (clk='1' and clk'event) thenif (j='0' and k='0') thenq<=q;qbar<=qbar;elsif (j='0' and k='1') thenq<='0';qbar<='1';elsif (j='1' and k='0') thenq<='1';qbar<='0';

elseq<=not q;qbar<=not qbar;end if;end if;end process;end Behavioral;

D FLIPFLOP:

LOGIC DIAGRAM:

1

23

CP

Q

1 23

1

231

23

1

23D

Q

TRUTH TABLE:

Q(t) D Q(t+1)

0 0 0

0 1 1

1 0 0

1 1 1

Behavioral Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity dff is Port ( d : in std_logic; clk : in std_logic; rst : in std_logic; q : inout std_logic; qbar : inout std_logic);end dff;architecture Behavioral of dff isbeginprocess(d,clk,rst,q,qbar)beginif (rst='1') thenq<='0';qbar<='1';elsif (clk='1' and clk'event) thenif (d='0') thenq<='0';qbar<='1';elseq<='1';qbar<='0';end if;end if;end process;end Behavioral;

T FLIPFLOP:LOGIC DIAGRAM: TRUTH TABLE:

1

231

28

9

1

23

128

9

CP

Q

T

Q

Q(t) T Q(t+1)

0 0 0

0 1 1

1 0 1

1 1 0

Behavioral Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity tff is Port ( t : in std_logic; clk : in std_logic; rst : in std_logic; q : inout std_logic; qbar : inout std_logic);end tff;architecture Behavioral of tff isbeginprocess(t,clk,rst,q,qbar)beginif (rst='1') thenq<='0';qbar<='1';elsif (clk='1' and clk'event) thenif (t='0') thenq<=q;qbar<=qbar;elseq<=not q;qbar<=not qbar;end if;end if;end process;end Behavioral;

SYNCHRONOUS COUNTER:

LOGIC DIAGRAM:

Structural Modeling:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity syncounter is Port ( clk : in std_logic; rst : in std_logic; q : inout std_logic_vector(3 downto 0));end syncounter;architecture structural of syncounter iscomponent tffport(t,clk,rst:in std_logic;q,qbar:inout std_logic);end component;component and2port(a,b:in std_logic; z:out std_logic);end component;signal x1,x2:std_logic;signal x3,x4,x5,x6:std_logic:='Z';begint1:tff port map ('1',clk,rst,q(0),x3);t2:tff port map (q(0),clk,rst,q(1),x4);t3:tff port map (x1,clk,rst,q(2),x5);t4:tff port map (x2,clk,rst,q(3),x6);a1:and2 port map (q(0),q(1),x1);a2:and2 port map (x1,q(2),x2);end structural;

tff component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity tff is Port ( t : in std_logic; clk : in std_logic; rst : in std_logic; q : inout std_logic; qbar : inout std_logic);end tff;architecture Behavioral of tff isbeginprocess(t,clk,rst,q,qbar)beginif (rst='1') thenq<='0';qbar<='1';elsif (clk='1' and clk'event) thenif (t='0') thenq<=q;qbar<=qbar;elseq<=not q;qbar<=not qbar;end if;end if;end process;end Behavioral;

and2 component source code:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity and2 is Port ( a : in std_logic; b : in std_logic; z : out std_logic);end and2;architecture dataflow of and2 isbeginz<=a and b;end dataflow;

--InputsSIGNAL clk : std_logic := '0';SIGNAL rst : std_logic := '0';--BiDirsSIGNAL q : std_logic_vector(3

downto 0);BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: syncounter PORT MAP(clk => clk,rst => rst,q => q

);tb : PROCESSBEGIN

clk<='1'; wait for 50ps;clk<='0'; wait for 50ps;END PROCESS;rst<='1','0' after 100ps;

END;

TEST BENCH(VHDL):LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.all;USE ieee.numeric_std.ALL;ENTITY test_vhd ISEND test_vhd;ARCHITECTURE behavior OF test_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT syncounterPORT(

clk : IN std_logic;rst : IN std_logic; q : INOUT std_logic_vector(3

downto 0));

END COMPONENT;

Simulation output:

Synthesis RTL Schematic: