Preliminary BIOS and Kernel Developer’s Guide (BKDG) for AMD …developer.amd.com/wordpress/media/2012/10/48751_BKDG_Fam_1… · 48751 Rev 3.00 - May 30, 2013 BKDG for AMD Family

48751 Rev 3.00 - May 30, 2013 BKDG for AMD Family 16h Models 00h-0Fh Processors

Cover Page

PreliminaryBIOS and Kernel Developer’s Guide

(BKDG)for AMD Family 16h

Models 00h-0Fh(Kabini) Processors

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Table of Contents1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.1 Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201.2 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201.3 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.3.1 Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201.3.2 Arithmetic And Logical Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211.3.3 Operator Precedence and Associativity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

1.4 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221.5 Changes Between Revisions and Product Variations . . . . . . . . . . . . . . . . . . . . . . . . 27

1.5.1 Revision Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271.5.2 Major Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281.5.2.1 Major Changes to Core/NB Performance Counters . . . . . . . . . . . . . . . . . 28

2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282.1 Processor Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282.2 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292.3 Processor Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.3.1 BSC Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302.3.2 AP Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302.3.3 Using L2 Cache as General Storage During Boot . . . . . . . . . . . . . . . . . . . . 302.3.4 Instruction Cache Configuration Register Usage Requirements . . . . . . . . . 32

2.4 Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322.4.1 L2 complex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322.4.2 Caches and TLBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332.4.2.1 Registers Shared by Cores in a L2 complex . . . . . . . . . . . . . . . . . . . . . . . 332.4.3 Virtual Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332.4.4 Processor Cores and Downcoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342.4.4.1 Software Downcoring using D18F3x190[DisCore] . . . . . . . . . . . . . . . . . 342.4.5 Physical Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352.4.6 System Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352.4.6.1 Memory Access to the Physical Address Space . . . . . . . . . . . . . . . . . . . . 352.4.6.1.1 Determining Memory Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352.4.6.1.2 Determining The Access Destination for Core Accesses . . . . . . . . . . . . 352.4.7 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362.4.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362.4.8.1 Local APIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362.4.8.1.1 Detecting and Enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362.4.8.1.2 APIC Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372.4.8.1.3 ApicId Enumeration Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372.4.8.1.4 Physical Destination Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372.4.8.1.5 Logical Destination Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372.4.8.1.6 Interrupt Delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382.4.8.1.7 Vectored Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382.4.8.1.8 Interrupt Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382.4.8.1.9 Spurious Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382.4.8.1.10 Spurious Interrupts Caused by Timer Tick Interrupt . . . . . . . . . . . . . . . 392.4.8.1.11 Lowest-Priority Interrupt Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . 392.4.8.1.12 Inter-Processor Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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2.4.8.1.13 APIC Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402.4.8.1.14 Generalized Local Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402.4.8.1.15 State at Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402.4.8.2 System Management Mode (SMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402.4.8.2.1 SMM Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402.4.8.2.2 Operating Mode and Default Register Values . . . . . . . . . . . . . . . . . . . . 412.4.8.2.3 SMI Sources And Delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412.4.8.2.4 SMM Initial State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412.4.8.2.5 SMM Save State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422.4.8.2.6 Exceptions and Interrupts in SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472.4.8.2.7 The Protected ASeg and TSeg Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . 472.4.8.2.8 SMM Special Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472.4.8.2.9 Locking SMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482.4.8.2.10 Synchronizing SMM Entry (Spring-Boarding) . . . . . . . . . . . . . . . . . . . 482.4.9 Secure Virtual Machine Mode (SVM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492.4.9.1 BIOS support for SVM Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492.4.10 CPUID Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502.4.10.1 Multi-Core Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

2.5 Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512.5.1 Processor Power Planes And Voltage Control. . . . . . . . . . . . . . . . . . . . . . . 512.5.1.1 Serial VID Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512.5.1.1.1 SVI2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522.5.1.2 Internal VID Registers and Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . 522.5.1.2.1 MinVid and MaxVid Check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522.5.1.3 Low Power Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522.5.1.3.1 PSIx_L Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522.5.1.3.1.1 BIOS Requirements for PSI0_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532.5.1.3.2 Low Power Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542.5.1.4 Voltage Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542.5.1.4.1 Hardware-Initiated Voltage Transitions . . . . . . . . . . . . . . . . . . . . . . . . . 542.5.1.4.2 Software-Initiated Voltage Transitions . . . . . . . . . . . . . . . . . . . . . . . . . 552.5.1.4.2.1 Software-Initiated NB Voltage Transitions . . . . . . . . . . . . . . . . . . . . 552.5.2 Frequency and Voltage Domain Dependencies. . . . . . . . . . . . . . . . . . . . . . 552.5.2.1 Dependencies Between Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552.5.2.2 Dependencies Between Subcomponents on VDDNB . . . . . . . . . . . . . . . . 552.5.2.3 BIOS Requirements for Power Plane Initialization . . . . . . . . . . . . . . . . . . 562.5.3 CPU Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562.5.3.1 Core P-states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562.5.3.1.1 Core P-state Naming and Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . 562.5.3.1.1.1 Software P-state Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572.5.3.1.1.2 Hardware P-state Numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572.5.3.1.2 Core P-state Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572.5.3.1.3 Core P-state Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582.5.3.1.4 Core P-state Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582.5.3.1.5 Core P-state Transition Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592.5.3.1.6 BIOS Requirements for Core P-state Initialization and Transitions . . . 592.5.3.1.7 Processor-Systemboard Power Delivery Compatibility Check . . . . . . . 602.5.3.1.8 BIOS COF and VID Requirements After Warm Reset . . . . . . . . . . . . . 622.5.3.1.8.1 Core Maximum P-state Transition Sequence After Warm Reset . . . . 622.5.3.1.8.2 Core Minimum P-state Transition Sequence After Warm Reset . . . . 622.5.3.1.8.3 ACPI Processor P-state Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

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2.5.3.1.8.4 Fixed ACPI Description Table (FADT) Entries . . . . . . . . . . . . . . . . . 642.5.3.1.8.5 XPSS (Microsoft Extended PSS) Object . . . . . . . . . . . . . . . . . . . . . . 642.5.3.2 Core C-states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642.5.3.2.1 C-state Names and Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652.5.3.2.2 C-state Request Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652.5.3.2.3 C-state Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652.5.3.2.3.1 C-state Probes and Cache Flushing . . . . . . . . . . . . . . . . . . . . . . . . . . . 652.5.3.2.3.2 Core C1 (CC1) State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662.5.3.2.3.3 Core C6 (CC6) State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662.5.3.2.3.4 Package C6 (PC6) State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662.5.3.2.4 C-state Request Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672.5.3.2.4.1 FCH Messaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672.5.3.2.4.2 Cache Flush On Halt Saturation Counter . . . . . . . . . . . . . . . . . . . . . . 672.5.3.2.5 Exiting C-states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672.5.3.2.6 ACPI Processor C-state Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682.5.3.2.6.1 _CST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682.5.3.2.6.2 _CRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682.5.3.2.6.3 Fixed ACPI Description Table (FADT) Entries . . . . . . . . . . . . . . . . . 682.5.3.2.7 BIOS Requirements for Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 682.5.3.3 Effective Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682.5.4 NB Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692.5.4.1 NB P-states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692.5.4.1.1 NB P-state Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692.5.4.1.2 BIOS NB P-state Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702.5.4.1.2.1 NB P-state COF and VID Synchronization After Warm Reset . . . . . 702.5.4.1.2.2 NB P-state Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712.5.4.1.2.3 NB P-state Configuration for Runtime . . . . . . . . . . . . . . . . . . . . . . . . 712.5.4.2 NB C-states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712.5.5 Bandwidth Requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722.5.6 GPU and Root Complex Power Management . . . . . . . . . . . . . . . . . . . . . . . 722.5.6.1 Dynamic Power Management (DPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722.5.6.1.1 Activity Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722.5.6.1.2 SCLK DPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722.5.6.1.3 LCLK DPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732.5.6.2 GPU and Root Complex Power Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . 732.5.7 DRAM Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742.5.7.1 Memory P-states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742.5.7.2 DRAM Self-Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742.5.7.3 Stutter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752.5.7.3.1 System BIOS Requirements for Stutter Mode Operation During POST 752.5.7.4 EVENT_L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752.5.8 System Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752.5.8.1 S-states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752.5.8.1.1 ACPI Suspend to RAM State (S3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752.5.9 Application Power Management (APM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 762.5.9.1 Core Performance Boost (CPB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762.5.9.1.1 C-state Boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772.5.9.2 TDP Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772.5.9.3 Bidirectional Application Power Management (BAPM) . . . . . . . . . . . . . 77

2.6 Performance Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782.6.1 Performance Monitor Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

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2.6.1.1 Core Performance Monitor Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782.6.1.2 L2I Performance Monitor Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782.6.1.3 NB Performance Monitor Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792.6.2 Instruction Based Sampling (IBS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

2.7 Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802.7.1 MMIO Configuration Coding Requirements. . . . . . . . . . . . . . . . . . . . . . . . 802.7.2 MMIO Configuration Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812.7.3 Processor Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

2.8 Northbridge (NB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812.8.1 NB Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812.8.2 NB Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822.8.2.1 Address Space Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822.8.2.1.1 DRAM and MMIO Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822.8.2.1.2 IO Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822.8.2.1.3 Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822.8.2.1.3.1 Recommended Buffer Count Settings Overview . . . . . . . . . . . . . . . . 832.8.3 Memory Scrubbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

2.9 DRAM Controllers (DCTs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842.9.1 Common DCT Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842.9.2 DCT Frequency Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852.9.3 DCT Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882.9.4 DDR Pad to Processor Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892.9.4.1 DDR Chip to Pad Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 892.9.5 DRAM Controller Direct Response Mode . . . . . . . . . . . . . . . . . . . . . . . . . 902.9.6 DRAM Data Burst Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902.9.7 DCT/DRAM Initialization and Resume . . . . . . . . . . . . . . . . . . . . . . . . . . . 922.9.7.1 Low Voltage DDR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 922.9.7.2 NB P-state Specific Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932.9.7.3 Memory P-state Specific Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 932.9.7.4 DDR Phy Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942.9.7.4.1 Phy Voltage Level Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942.9.7.4.2 DRAM Channel Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942.9.7.4.2.1 Requirements for DRAM Frequency Change During Training . . . . . 952.9.7.4.3 Phy Fence Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 962.9.7.4.3.1 Phy Fence Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972.9.7.4.4 Phy Compensation Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972.9.7.5 SPD ROM-Based Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002.9.7.6 Non-SPD ROM-Based Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 1012.9.7.6.1 TrdrdSdSc, TrdrdSdDc, and TrdrdDd (Read to Read Timing) . . . . . . 1022.9.7.6.2 TwrwrSdSc, TwrwrSdDc, TwrwrDd (Write to Write Timing) . . . . . . 1022.9.7.6.3 Twrrd (Write to Read DIMM Termination Turn-around) . . . . . . . . . . 1022.9.7.6.4 TrwtTO (Read-to-Write Turnaround for Data, DQS Contention) . . . . 1032.9.7.6.5 DRAM ODT Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1032.9.7.6.5.1 DRAM ODT Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1042.9.7.6.6 DRAM Address Timing and Output Driver Compensation Control . . 1062.9.7.7 DCT Training Specific Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 1142.9.7.8 DRAM Device and Controller Initialization . . . . . . . . . . . . . . . . . . . . . . 1142.9.7.8.1 Software DDR3 Device Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 1152.9.7.8.1.1 DDR3 MR Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1152.9.7.9 DRAM Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192.9.7.9.1 Write Levelization Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

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2.9.7.9.1.1 Write Leveling Seed Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1202.9.7.9.2 DQS Receiver Enable Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1212.9.7.9.2.1 DQS Receiver Enable Training Seed Value . . . . . . . . . . . . . . . . . . . 1222.9.7.9.3 DQS Receiver Enable Cycle Training . . . . . . . . . . . . . . . . . . . . . . . . . 1232.9.7.9.4 DQS Position Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1232.9.7.9.5 Calculating MaxRdLatency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1272.9.7.9.5.1 MaxRdLatency Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1272.9.7.10 DRAM Phy Power Savings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1282.9.8 Continuous Pattern Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1292.9.8.1 DCT Training Pattern Generation (Reliable Read Write Mode) . . . . . . . 1292.9.8.1.1 Activate and Precharge Command Generation . . . . . . . . . . . . . . . . . . 1292.9.8.1.2 Read and Write Command Generation . . . . . . . . . . . . . . . . . . . . . . . . 1302.9.8.1.3 Configurable Data Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1312.9.8.1.3.1 Static Data Pattern Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1322.9.8.1.3.2 Xor Data Pattern Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1332.9.8.1.4 Data Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1342.9.8.1.4.1 Activate and Precharge Traffic Generation . . . . . . . . . . . . . . . . . . . 1342.9.8.1.5 BubbleCnt and CmdStreamLen Programming . . . . . . . . . . . . . . . . . . . 1352.9.9 Memory Interleaving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1362.9.9.1 Chip Select Interleaving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1362.9.10 Memory Hoisting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1372.9.10.1 DramHoleOffset Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1382.9.11 DRAM CC6/PC6 Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1392.9.11.1 Fixed Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1392.9.12 DRAM On DIMM Thermal Management and Power Capping . . . . . . . . 140

2.10 Thermal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1422.10.1 The Tctl Temperature Scale. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1422.10.2 Temperature Slew Rate Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1432.10.3 Temperature-Driven Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1432.10.3.1 PROCHOT_L and Hardware Thermal Control (HTC) . . . . . . . . . . . . . . 1432.10.3.2 Local Hardware Thermal Control (LHTC) . . . . . . . . . . . . . . . . . . . . . . . 1442.10.3.3 Software P-state Limit Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1442.10.3.4 THERMTRIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

2.11 Root Complex . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1462.11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1462.11.2 Interrupt Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1462.11.2.1 IOAPIC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1472.11.3 Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1472.11.3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1472.11.3.2 Link Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482.11.4 Root Complex Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482.11.4.1 LPC MMIO Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482.11.4.2 Configuration for non-FCH Bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482.11.4.3 Link Configuration and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 1482.11.4.3.1 Link Configuration and Core Initialization . . . . . . . . . . . . . . . . . . . . . 1492.11.4.3.2 Link Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492.11.4.4 Miscellaneous Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492.11.4.4.1 Lane Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1492.11.4.4.2 Link Speed Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502.11.4.4.2.1 Autonomous Link Speed Changes . . . . . . . . . . . . . . . . . . . . . . . . . . 1502.11.4.4.3 Deemphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

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2.11.4.5 Link Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502.11.4.5.1 Link States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502.11.4.5.2 Dynamic Link-width Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502.11.4.6 Link Test and Debug Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502.11.4.6.1 Compliance Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1502.11.5 BIOS Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1512.11.6 PCIe Client Interface Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

2.12 System Management Unit (SMU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1522.12.1 Software Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

2.13 Graphics Processor (GPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1522.13.1 Graphics Memory Controller (GMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1522.13.2 Frame Buffer (FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

2.14 RAS Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1542.14.1 Machine Check Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1542.14.1.1 Machine Check Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1542.14.1.2 Machine Check Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1552.14.1.3 Error Detection, Action, Logging, and Reporting . . . . . . . . . . . . . . . . . . 1562.14.1.3.1 MCA conditions that cause Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . 1572.14.1.3.2 Error Logging During Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1572.14.1.4 MCA Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1582.14.1.5 Error Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1582.14.1.6 Handling Machine Check Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 1602.14.1.6.1 Differentiation Between System-Fatal and Process-Fatal Errors . . . . . 1622.14.1.7 Error Thresholding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1632.14.1.8 Scrub Rate Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1642.14.1.9 Error Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1652.14.1.9.1 Common Diagnosis Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1662.14.2 DRAM ECC Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672.14.2.1 ECC Syndromes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672.14.2.1.1 x4 ECC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1672.14.3 Error Injection and Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1692.14.3.1 DRAM Error Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

2.15 Fusion Controller Hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1712.15.1 MMIO Programming for Legacy Devices. . . . . . . . . . . . . . . . . . . . . . . . . 1712.15.2 USB Controllers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1712.15.2.1 USB Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1722.15.2.2 USB Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1722.15.2.3 BIOS Programming Requirements For USB Reset During S3 Resume .1722.15.2.4 Enabling the xHCI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1722.15.2.5 OHCI Arbiter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1722.15.2.6 USB2.0 Controller PHY Configuration and Calibration . . . . . . . . . . . . . 1732.15.2.7 USB2.0 Controller ISO Device CRC False Error Detection . . . . . . . . . . 1732.15.2.8 xHC USB2.0 Common PHY Calibration . . . . . . . . . . . . . . . . . . . . . . . . 1742.15.2.9 USB3.0 PHY Auto-Calibration Enablement . . . . . . . . . . . . . . . . . . . . . . 1742.15.2.10 xHCI ISO Device CRC False Error Detection . . . . . . . . . . . . . . . . . . . . 1742.15.2.11 xHCI PHY Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1752.15.2.12 xHCI Firmware Preload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1752.15.2.13 xHCI Clear Pending PME on Sx State Entry . . . . . . . . . . . . . . . . . . . . . 1752.15.2.14 xHCI Enable OHCI3/EHCI3 on S4/S5 State Entry . . . . . . . . . . . . . . . . . 1762.15.3 SATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1762.15.3.1 SATA Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

8


2.15.3.2 SATA Drive Detection in IDE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 1762.15.3.3 SATA PHY Auto-Calibration Enablement . . . . . . . . . . . . . . . . . . . . . . . 1762.15.3.4 SATA PHY Fine Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1762.15.3.5 SATA PHY Reference Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . 1772.15.3.6 SATA Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1782.15.3.6.1 SATA PHY Power Saving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1782.15.3.7 Enable Shadow Register Reload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1782.15.3.8 SATA Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1782.15.3.8.1 Line Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1782.15.3.8.2 MSI Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1782.15.3.9 Clear status of SATA PERR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1792.15.4 LPC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1792.15.4.1 Enabling LPC DMA function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1792.15.4.2 Enabling SPI 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1792.15.5 SD Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1792.15.6 HD Audio. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1792.15.6.1 HD Audio AF and MSI Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1802.15.7 ASF Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1802.15.8 Integrated Micro-Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1802.15.9 On-Chip Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1802.15.9.1 Power Saving In Internal Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 1812.15.9.2 Global A-Link / B-Link Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . 1812.15.9.3 CG_PLL CMOS Clock Driver Setting for Power Saving . . . . . . . . . . . . 1812.15.10 Scallion Gasket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1812.15.11 A-Link Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1812.15.11.1 Detection of Upstream Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1812.15.11.2 AB Memory Power Saving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1822.15.11.3 AB Internal Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1822.15.11.4 AB 32/64 Byte DMA Write Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

3 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1833.1 Register Descriptions and Mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

3.1.1 Northbridge MSRs In Multi-Core Products. . . . . . . . . . . . . . . . . . . . . . . . 1873.1.2 Software Recommendation (BIOS, SBIOS, IBIOS) . . . . . . . . . . . . . . . . . 1873.1.3 See Keyword (See:) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1883.1.4 Mapping Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1883.1.4.1 Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1883.1.4.2 Index Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1883.1.4.3 Field Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1883.1.4.4 Broadcast Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1883.1.4.5 Reset Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1893.1.4.6 Valid Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1893.1.4.7 BIOS Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

3.2 IO Space Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1893.3 Device 0 Function 0 (Root Complex) Configuration Registers . . . . . . . . . . . . . . . 1913.4 Device 0 Function 2 Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2293.5 Device 1 Function 0 (Internal Graphics) Configuration Registers . . . . . . . . . . . . . 2313.6 Device 1 Function 1 (Audio Controller) Configuration Registers . . . . . . . . . . . . . 2433.7 Device 2 Function 0 (Host Bridge) Configuration Registers . . . . . . . . . . . . . . . . . 2543.8 Device 2 Function [5:1] (Root Port) Configuration Registers . . . . . . . . . . . . . . . . 2553.9 Device 18h Function 0 Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 286

9


3.10 Device 18h Function 1 Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 2993.11 Device 18h Function 2 Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 3113.12 Device 18h Function 3 Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 4003.13 Device 18h Function 4 Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 4373.14 Device 18h Function 5 Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 4473.15 GPU Memory Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4623.16 Northbridge IOAPIC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4623.17 APIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4643.18 CPUID Instruction Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4743.19 MSRs - MSR0000_xxxx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5033.20 MSRs - MSRC000_0xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5363.21 MSRs - MSRC001_0xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5423.22 MSRs - MSRC001_1xxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5723.23 Core Performance Counter Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586

3.23.1 PMCx0[1F:00] Events (FP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5863.23.2 PMCx0[3F:20] Events (LS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5873.23.3 PMCx0[5F:40] Events (DC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5893.23.4 PMCx[8,1:0][7F:60] Events (BU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5913.23.5 PMCx[1:0][9F:80] Events (IC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5953.23.6 PMCx[1,0][DF:C0] Events (EX, DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597

3.24 L2I Performance Counter Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6003.25 NB Performance Counter Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602

3.25.1 PMCx0E[7:4] Events (Memory Controller) . . . . . . . . . . . . . . . . . . . . . . . 6023.25.2 PMCx0E[F:8] Events (Crossbar). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6023.25.3 PMCx0F[F:0] Events (ONION, Crossbar) . . . . . . . . . . . . . . . . . . . . . . . . 6053.25.4 NBPMCx1E[F:0] Events (Crossbar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6053.25.5 NBPMCx1F[F:0] Events (Memory Controller, Crossbar) . . . . . . . . . . . . 608

3.26 Fusion Controller Hub Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6113.26.1 Legacy Block Configuration Registers (IO) . . . . . . . . . . . . . . . . . . . . . . . 6113.26.2 AB Configuration Registers (Scallion) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6313.26.3 SATA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6343.26.3.1 Device 11h Function 0 (SATA) Configuration Registers . . . . . . . . . . . . 6343.26.3.2 SATA IO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6513.26.3.2.1 IDE Compatibility Mode and Native Mode (BAR0, BAR1, BAR2, BAR3) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6513.26.3.2.2 IDE Bus Master (BAR4) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 6533.26.3.3 SATA Memory Mapped AHCI Registers . . . . . . . . . . . . . . . . . . . . . . . . 6543.26.3.3.1 Generic Host Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6553.26.3.3.2 Port Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6613.26.3.3.3 Enclosure Buffer Management Registers . . . . . . . . . . . . . . . . . . . . . . . 6763.26.4 USB Controllers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6793.26.4.1 USB 1.1 (OHCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6793.26.4.1.1 Devices 16h, 13h, 12h Function 0 (OHCI) Configuration Registers . . 6793.26.4.1.2 OHCI Memory Mapped IO Registers . . . . . . . . . . . . . . . . . . . . . . . . . 6863.26.4.2 USB 2.0 (EHCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7003.26.4.2.1 Devices 16h, 13h, 12h Function 2 (EHCI) Configuration Registers . . 7003.26.4.2.2 EHCI Memory Mapped IO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 7093.26.4.3 USB 3.0 (xHCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7253.26.4.3.1 Device 10h Function 0 (xHCI) Configuration Registers . . . . . . . . . . . 7253.26.4.3.1.1 USB xHCI Capability Registers (XHCI_CAP) . . . . . . . . . . . . . . . . 7443.26.4.3.2 xHCI Power Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 744

10


3.26.5 HD Audio Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7503.26.5.1 Device 14h Function 2 (Audio Controller) Configuration Registers . . . 7503.26.6 Secure Digital (SD) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7573.26.6.1 Device 14h Function 7 Configuration Registers (SD) . . . . . . . . . . . . . . . 7573.26.6.2 SD Host Controller Configuration Registers (SDHC) . . . . . . . . . . . . . . 7623.26.7 SMBus Host Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7773.26.7.1 Device 14h Function 0 (SMBus) Configuration Registers . . . . . . . . . . . 7773.26.7.2 ASF (Alert Standard Format) Registers . . . . . . . . . . . . . . . . . . . . . . . . . 7803.26.7.3 SMBus Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7853.26.8 IOAPIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7923.26.9 LPC-ISA Bridge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7943.26.9.1 Device 14h Function 3 (LPC Bridge) Configuration Registers . . . . . . . 7943.26.9.2 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8073.26.10 High Precision Event Timer (HPET) Registers . . . . . . . . . . . . . . . . . . . . . 8173.26.11 Miscellaneous (MISC) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8203.26.12 GPIO Pin control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8433.26.12.1 GPIO Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8433.26.12.2 IOMux Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8433.26.13 Power Management (PM) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8453.26.14 Power Management Block 2 (PM2) Registers. . . . . . . . . . . . . . . . . . . . . . 8763.26.15 Standard ACPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8853.26.15.1 AcpiPmEvtBlk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8863.26.15.2 AcpiPm1CntBlk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8873.26.15.3 AcpiPm2CntBlk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8873.26.15.4 AcpiPmTmrBlk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8873.26.15.5 CpuCntBlk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8883.26.15.6 AcpiGpe0Blk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8883.26.15.7 SmiCmdBlk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8893.26.16 SMI Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8903.26.17 Watchdog Timer (WDT) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9193.26.18 Wake Alarm Device (AcDcTimer) Registers . . . . . . . . . . . . . . . . . . . . . . 919

4 Register List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 923

11


12

List of FiguresFigure 1: A L2 Complex............................................................................................................................. 29Figure 2: DQS Position Training Example Results .................................................................................. 125Figure 3: DQS Position Training Insertion Delay Recovery Example Results........................................ 126Figure 4: Memory Configuration with Memory Hole inside of Region .................................................. 138Figure 5: Memory Configuration with Memory Hole outside of Region ................................................ 139Figure 6: Tctl scale ................................................................................................................................... 143Figure 7: Root complex topology............................................................................................................. 146Figure 8: Address/Command Timing at the Processor Pins..................................................................... 327


List of TablesTable 1: Arithmetic and Logical Operators............................................................................................... 21Table 2: Functions..................................................................................................................................... 21Table 3: Operator Precedence and Associativity ...................................................................................... 22Table 4: Definitions................................................................................................................................... 22Table 5: Processor revision conventions................................................................................................... 28Table 6: SMM Initial State........................................................................................................................ 42Table 7: SMM Save State.......................................................................................................................... 42Table 8: Power Management Support....................................................................................................... 51Table 9: Software P-state Naming ............................................................................................................ 57Table 10: Software P-state Control ............................................................................................................. 58Table 11: ONION Link Definitions ............................................................................................................ 83Table 12: DCT Definitions.......................................................................................................................... 84Table 13: DDR3 UDIMM Maximum Frequency Support with 6-layer Motherboard Design FT3 package......................................................................................................................85Table 14: DDR3 UDIMM Maximum Frequency Support with 6-layer Motherboard Design FT3 package Microserver.................................................................................................86Table 15: DDR3 SODIMM Maximum Frequency Support with 6-layer Motherboard Design FT3 package ...................................................................................................................86Table 16: DDR3 UDIMM Maximum Frequency Support with 4-layer Motherboard Design FT3 package ....................................................................................................................86Table 17: DDR3 SODIMM Maximum Frequency Support with 4-layer Motherboard Design FT3 package ...................................................................................................................87Table 18: DDR3 SODIMM plus Solder-down DRAM Maximum Frequency with 6-layer Motherboard FT3 package ..............................................................................................87Table 19: DDR3 SODIMM plus Solder-down DRAM Maximum Frequency with 4-layer Motherboard FT3 package...............................................................................................87Table 20: DDR3 Solder-down DRAM Maximum Frequency Support FT3 package................................. 88Table 21: DDR3 UDIMM Maximum Frequency Support FS1b package .................................................. 88Table 22: DDR3 Population Support .......................................................................................................... 88Table 23: Package pin mapping ................................................................................................................. 89Table 24: Pad (from chiplet) pin mapping .................................................................................................. 90Table 25: DDR PLL Lock Time................................................................................................................. 95Table 26: Phy predriver calibration codes for Data/DQS at 1.5V .............................................................. 97Table 27: Phy predriver calibration codes for Data/DQS at 1.35V ............................................................ 98Table 28: Phy Predriver Calibration Codes for Data/DQS at 1.25V .......................................................... 98Table 29: Phy predriver calibration codes for Cmd/Addr at 1.5V.............................................................. 98Table 30: Phy predriver calibration codes for Cmd/Addr at 1.35V............................................................ 99Table 31: Phy Predriver Calibration Codes for Cmd/Addr at 1.25V.......................................................... 99Table 32: Phy predriver calibration codes for Clock at 1.5V...................................................................... 99Table 33: Phy predriver calibration codes for Clock at 1.35V.................................................................. 100Table 34: Phy Predriver Calibration Codes for Clock at 1.25V................................................................ 100Table 35: DDR3 ODT Pattern NumDimmSlots=1 ................................................................................... 103Table 36: DDR3 ODT Pattern NumDimmSlots=2 ................................................................................... 103

13


Table 37: BIOS recommendations for MR1[RttNom] and MR2[RttWr] UDIMM FT3 package ............ 104Table 38: BIOS recommendations for MR1[RttNom] and MR2[RttWr] SODIMM FT3 package.......... 104Table 39: BIOS recommendations for MR1[RttNom] and MR2[RttWr] SODIMM plus Solder-down DRAM FT3 package............................................................................................105Table 40: BIOS recommendations for MR1[RttNom] and MR2[RttWr] Solder-down DRAM FT3 package.................................................................................................................105Table 41: BIOS recommendations for MR1[RttNom] and MR2[RttWr] UDIMM FS1b package .......... 105Table 42: BIOS recommendations for SlowAccessMode, POdtOff, Addr/Cmd Timings and Output Driver Control UDIMM FT3 package...........................................................................107Table 43: BIOS recommendations for SlowAccessMode, POdtOff, Addr/Cmd Timings and Output Driver Control SODIMM FT3 package........................................................................109Table 44: BIOS recommendations for SlowAccessMode, POdtOff, Addr/Cmd Timings and Output Driver Control SODIMM plus Solder-down DRAM FT3 package..............................111Table 45: BIOS recommendations for SlowAccessMode, POdtOff, Addr/Cmd Timings and Output Driver Control Solder-down DRAM FT3 package...................................................... 112Table 46: BIOS recommendations for SlowAccessMode, POdtOff, Addr/Cmd Timings and Output Driver Control UDIMM FS1b package........................................................................ 113Table 47: DCT Training Specific Register Values.....................................................................................114Table 48: BIOS Recommendations for MR0[WR]....................................................................................116Table 49: BIOS Recommendations for MR0[CL[3:0]] .............................................................................116Table 50: BIOS Recommendations for MR2[ASR, SRT] .........................................................................118Table 51: DDR3 Write Leveling Seed Values........................................................................................... 121Table 52. DDR3 DQS Receiver Enable Training Seed Values................................................................. 123Table 53. Configurable Data Pattern Example with 1 Address Target ..................................................... 131Table 54. Configurable Data Pattern Circular Shift Example with 1 Address Target .............................. 132Table 55. Data Pattern Override Example with 1 Address Target ........................................................... 133Table 56. Command Generation and Data Comparison ........................................................................... 134Table 57. DDR3 Command Generation and BubbleCnt Programming.................................................... 135Table 58. Recommended Interleave Configurations................................................................................. 136Table 59. DDR3 Swapped Normalized Address Lines for CS Interleaving............................................. 137Table 60. Example storage region configuration ...................................................................................... 140Table 61: Recommended Interrupt Routing and Swizzling Configuration............................................... 147Table 62: Supported General Purpose (GPP) Link Configurations .......................................................... 148Table 63: SMU Software Interrupts .......................................................................................................... 152Table 64: Recommended Frame Buffer Configurations ........................................................................... 153Table 65: MCA register cross-reference table .......................................................................................... 155Table 66: Overwrite Priorities for All Banks ............................................................................................ 158Table 67: Error Code Types ...................................................................................................................... 159Table 68: Error codes: transaction type (TT) ............................................................................................ 159Table 69: Error codes: cache level (LL).................................................................................................... 159Table 70: Error codes: memory transaction type (RRRR)........................................................................ 159Table 71: Error codes: participation processor (PP) ................................................................................. 160Table 72: Error codes: memory or IO (II)................................................................................................. 160Table 73: Error codes: Internal Error Type (UU)...................................................................................... 160Table 74: Error Scope Hierarchy .............................................................................................................. 162

14


Table 75: Recommended Scrub Rates per Node....................................................................................... 164Table 76: Registers Commonly Used for Diagnosis................................................................................. 166Table 77: x4 ECC Correctable Syndromes ............................................................................................... 168Table 78: USB Port Mapping.................................................................................................................... 171Table 79: USB Port to EHCI[3:1]xB4[PortNumber] Mapping ................................................................ 173Table 80: USB Port to D10F0x4C_x4000_0000[PortNumber] Mapping ................................................ 175Table 81: HD Audio AF and MSI Capability Settings ............................................................................. 180Table 82: ASF Remote Control Commands ............................................................................................. 180Table 83: Terminology in Register Descriptions ...................................................................................... 185Table 84: Reset values for D0F0x64_x3[4:0] ........................................................................................... 196Table 85: Register Mapping for D0F0xBC_x3FD[8C:00:step14]............................................................ 206Table 86: Register Mapping for D0F0xBC_x3FD[94:08:step14] ............................................................ 207Table 87: Register Mapping for D0F0xBC_x3FD[9C:10:step14]............................................................ 207Table 88: Index addresses for D0F0xE4_x0110_001[8:7,3:2] ................................................................. 214Table 89: Index address mapping for D0F0xE4_x0130_0[C:8]00........................................................... 216Table 90: Index address mapping for D0F0xE4_x0130_0[C:8]03........................................................... 217Table 91: Index address mapping for D0F0xE4_x0130_0[C:8]05........................................................... 217Table 92: Lane index addresses for D0F0xE4_x0130_802[4:1] .............................................................. 221Table 93: Reset Mapping for D0F0xE4_x0130_802[4:1] ........................................................................ 221Table 94: Field mapping for D0F0xE4_x0130_802[4:1] ......................................................................... 221Table 95: Lane index addresses for D0F0xE4_x0130_802[8:5] .............................................................. 222Table 96: Reset Mapping for D0F0xE4_x0130_802[8:5] ........................................................................ 222Table 97: Field mapping for D0F0xE4_x0130_802[8:5] ......................................................................... 222Table 98: Register Mapping for D2F[5:1]x00 .......................................................................................... 255Table 99: Link controller state encodings ................................................................................................. 276Table 100: Register Mapping for D18F0x[5C:40]...................................................................................... 287Table 101: Register Mapping for D18F0x[E4,C4,A4,84] .......................................................................... 291Table 102: Register Mapping for D18F0x[EC,CC,AC,8C]........................................................................ 291Table 103: Register Mapping for D18F0x[F0,D0,B0,90]........................................................................... 292Table 104: Link Buffer Definitions............................................................................................................. 293Table 105: Register Mapping for D18F0x[F4,D4,B4,94]........................................................................... 294Table 106: Register Mapping for D18F0x[F8,D8,B8,98]........................................................................... 295Table 107: Register Mapping for D18F0x[11C,118,114,110].................................................................... 296Table 108: Register Mapping for D18F0x[18C:170].................................................................................. 297Table 109: Onion Definitions...................................................................................................................... 297Table 110: Register Mapping for D18F1x[17C:140,7C:40]....................................................................... 299Table 111: Register Mapping for D18F1x[7:4][8,0]................................................................................... 300Table 112: Register Mapping for D18F1x[7:4][C,4] .................................................................................. 300Table 113: Register Mapping for D18F1x[2CC:2A0,1CC:180,BC:80] ..................................................... 301Table 114: Register Mapping for D18F1x[2B:1A,B:8][8,0] ...................................................................... 302Table 115: Register Mapping for D18F1x[2B:1A,B:8][C,4]...................................................................... 302Table 116: Register Mapping for D18F1x[1F:1E,D:C][8,0] ...................................................................... 304Table 117: Register Mapping for D18F1x[1F:1E,D:C][C,4]...................................................................... 305Table 118: Register Mapping for D18F1x[1DC:1D0,EC:E0] .................................................................... 305

15


Table 119: Register Mapping for D18F1x2[1C:00].................................................................................... 309Table 120: Register Mapping for D18F1x2[1,0][8,0]................................................................................. 309Table 121: Register Mapping for D18F1x2[1,0][C,4] ................................................................................ 310Table 122: DIMM, Chip Select, and Register Mapping ..............................................................................311Table 123: DDR3 DRAM Address Mapping.............................................................................................. 315Table 124: Valid Values for Memory Clock Frequency Value Definition ................................................. 322Table 125: Index Mapping for D18F2x9C_x0000_0[3:0]0[3:1]_dct[0]_mp[1:0]...................................... 326Table 126: Byte Lane Mapping for D18F2x9C_x0000_0[3:0]0[3:1]_dct[0]_mp[1:0] .............................. 326Table 127: Index Mapping for D18F2x9C_x0000_0[3:0]0[7:5]_dct[0]_mp[1:0]...................................... 328Table 128: Byte Lane Mapping for D18F2x9C_x0000_0[3:0]0[7:5]_dct[0]_mp[1:0] .............................. 329Table 129: Index Mapping for D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0]......................................... 333Table 130: Byte Lane Mapping for D18F2x9C_x0000_00[2A:10]_dct[0]_mp[1:0] ................................. 334Table 131: Index Mapping for D18F2x9C_x0000_00[4A:30]_dct[0]_mp[1:0]......................................... 335Table 132: Byte Lane Mapping for D18F2x9C_x0000_00[4A:30]_dct[0]_mp[1:0] ................................. 336Table 133: Index Mapping for D18F2x9C_x0000_00[52:50]_dct[0] ........................................................ 336Table 134: Byte Lane Mapping for D18F2x9C_x0000_00[52:50]_dct[0]................................................. 337Table 135: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]02_dct[0] ...................................................... 337Table 136: Broadcast Mapping for D18F2x9C_x0D0F_0[F,8:0]02_dct[0] ............................................... 338Table 137: Valid Values for D18F2x9C_x0D0F_0[F,8:0]02_dct[0][TxPreP]........................................... 338Table 138: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]0[B,7,3]_dct[0]............................................. 339Table 139: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]04_dct[0]_mp[1:0] ....................................... 339Table 140: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]06_dct[0] ...................................................... 340Table 141: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]0A_dct[0] ..................................................... 340Table 142: Broadcast Mapping for D18F2x9C_x0D0F_0[F,8:0]0[A,6]_dct[0]......................................... 340Table 143: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]10_dct[0]_mp[1:0] ....................................... 340Table 144: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]13_dct[0]_mp[1:0] ....................................... 341Table 145: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]1C_dct[0]_mp[1:0] ...................................... 342Table 146: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]1E_dct[0]_mp[1:0]....................................... 343Table 147: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]1F_dct[0]_mp[1:0]....................................... 343Table 148: Index Mapping for D18F2x9C_x0D0F_0[F,8:0]2[3:0]_dct[0]_mp[1:0] ................................. 344Table 149: Index Addresses for D18F2x9C_x0D0F_0[F,8:0]30_dct[0] .................................................... 346Table 150: Broadcast Write Index Address for D18F2x9C_x0D0F_0[F,8:0]30_dct[0] ............................ 346Table 151: Index addresses for D18F2x9C_x0D0F_0[F,8:0]31_dct[0] ..................................................... 346Table 152: Broadcast write index address for D18F2x9C_x0D0F_0[F,8:0]31_dct[0] .............................. 347Table 153: Index addresses for D18F2x9C_x0D0F_0[F,8:0]38_dct[0] ..................................................... 347Table 154: Broadcast write index address for D18F2x9C_x0D0F_0[F,8:0]38_dct[0] .............................. 347Table 155: Broadcast write index address for D18F2x9C_x0D0F_1C00_dct[0]....................................... 348Table 156: Index Mapping for D18F2x9C_x0D0F_2[2:0]02_dct[0] ......................................................... 348Table 157: Index address mapping for D18F2x9C_x0D0F_[C,8,2][2:0]1E_dct[0]_mp[1:0] .................... 349Table 158: Index address mapping for D18F2x9C_x0D0F_[C,8,2][2:0]1F_dct[0] ................................... 349Table 159: Index Addresses for D18F2x9C_x0D0F_[C,8,2][2:0]20_dct[0]_mp[1:0] ............................... 350Table 160: Index Addresses for D18F2x9C_x0D0F_2[F,2:0]30_dct[0] .................................................... 350Table 161: Index Mapping for D18F2x9C_x0D0F_[C,8][1:0]02_dct[0]................................................... 352Table 162: Index Mapping for D18F2x9C_x0D0F_[C,8][1:0][12,0E,0A,06]_dct[0]................................ 353

16


Table 163: Index Mapping for D18F2x9C_x0D0F_[C,8][F:0]30_dct[0]................................................... 353Table 164: BIOS Recommendations for D18F2x1B[4:0]........................................................................... 366Table 165: Field Mapping for D18F2x1BC_dct[0] .................................................................................... 370Table 166: BIOS Recommendations for D18F2x1BC_dct[0] .................................................................... 370Table 167: BIOS Recommendations for RdPtrInit ..................................................................................... 374Table 168: Register Mapping for D18F2x25[8,4]_dct[0]........................................................................... 386Table 169: Register Mapping for D18F2x2[B4,B0,AC,A8]_dct[0] ........................................................... 393Table 170: Field Mapping for D18F2x2[B4,B0,AC,A8]_dct[0] ................................................................ 394Table 171: Field Mappings for D18F2x2[C0,BC]_dct[0] .......................................................................... 395Table 172: Buffer Definitions ......................................................................................................................411Table 173: SMAF Action Definition .......................................................................................................... 414Table 174: Register Mapping for D18F3x1[54:48] .................................................................................... 428Table 175: D18F5x80[Enabled, DualCore, TripleCore, QuadCore] Definition......................................... 448Table 176: Register Mapping for D18F5x16[C:0]...................................................................................... 453Table 177: NB P-state Definitions .............................................................................................................. 454Table 178: Register Mapping for APIC[170:100] ...................................................................................... 466Table 179: Register Mapping for APIC[1F0:180] ...................................................................................... 467Table 180: Register Mapping for APIC[270:200] ...................................................................................... 467Table 181: ICR valid combinations ............................................................................................................ 468Table 182: Register Mapping for APIC3[60:50] ........................................................................................ 471Table 183: Div[3,1:0] Value Table .............................................................................................................. 472Table 184: Register Mapping for APIC[4F0:480] ...................................................................................... 473Table 185: Register Mapping for APIC[530:500] ...................................................................................... 474Table 186: Reset Mapping for CPUID Fn8000_0000_E[D,C,B]X ............................................................ 475Table 187: CPUID Fn8000_0000_E[B,C,D]X Value ................................................................................. 483Table 188: Valid Values for CPUID Fn8000_000[4:2]_E[D,C,B,A]X...................................................... 486Table 189: ECX mapping to Cache Type for CPUID Fn8000_001D_E[D,C,B,A]X................................. 496Table 190: Register Mapping for MSR0000_020[E,C,A,8,6,4,2,0] ........................................................... 507Table 191: Valid Values for Memory Type Definition............................................................................... 508Table 192: Register Mapping for MSR0000_020[F,D,B,9,7,5,3,1] ........................................................... 508Table 193: Register Mapping for MSR0000_02[6F:68,59:58,50].............................................................. 509Table 194: Field Mapping for MSR0000_02[6F:68,59:58,50]................................................................... 509Table 195: MC0 Error Descriptions............................................................................................................ 514Table 196: MC0 Error Signatures ............................................................................................................... 515Table 197: MC0 Address Register .............................................................................................................. 515Table 198: MC1 Error Descriptions............................................................................................................ 517Table 199: MC1 Error Signatures ............................................................................................................... 518Table 200: MC1 Address Register .............................................................................................................. 518Table 201: MC2 Error Descriptions............................................................................................................ 521Table 202: MC2 Error Signatures ............................................................................................................... 522Table 203: MC2 Address Register .............................................................................................................. 523Table 204: MC4 Error Descriptions............................................................................................................ 526Table 205: MC4 Error Signatures, Part 1.................................................................................................... 527Table 206: MC4 Error Signatures, Part 2.................................................................................................... 528

17


Table 207: Format of MSR0000_0412[ErrAddr[47:1]] for All Other Errors............................................. 529Table 208: Format of MSR0000_0412[ErrAddr[47:1]] for Protocol Errors .............................................. 529Table 209: Valid Values for ProtocolErrorType ......................................................................................... 529Table 210: Format of MSR0000_0412[ErrAddr[47:1]] for NB Array Errors ............................................ 530Table 211: Valid Values for ArrayErrorType ............................................................................................. 530Table 212: Format of MSR0000_0412[ErrAddr[47:1]] for Watchdog Timer Errors ................................. 531Table 213: MC5 Error Descriptions............................................................................................................ 534Table 214: MC5 Error Signatures ............................................................................................................... 534Table 215: MC5 Address Register .............................................................................................................. 534Table 216: Register Mapping for MSRC001_00[03:00] ............................................................................ 542Table 217: Register Mapping for MSRC001_00[07:04] ............................................................................ 544Table 218: Register Mapping for MSRC001_00[35:30] ............................................................................ 550Table 219: BIOS Recommendations for MSRC001_00[35:30] ................................................................. 550Table 220: Register Mapping for MSRC001_00[53:50] ............................................................................ 554Table 221: Register Mapping for MSRC001_00[6B:64]............................................................................ 558Table 222: P-state Definitions..................................................................................................................... 558Table 223: Register Mapping for MSRC001_023[6,4,2,0] ........................................................................ 568Table 224: Register Mapping for MSRC001_023[7,5,3,1] ........................................................................ 570Table 225: Register Mapping for MSRC001_024[6,4,2,0] ........................................................................ 570Table 226: Register Mapping for MSRC001_024[7,5,3,1] ........................................................................ 571Table 227: Register Mapping for MSRC001_101[B:9].............................................................................. 575Table 228: Field Mapping for MSRC001_101[B:9]................................................................................... 575Table 229: Register Mapping for PMCx0D[F:C] ....................................................................................... 599Table 230: SATA Controller Subclass Code and ProgramIF Settings ........................................................ 635Table 231: IDE Compatibility Mode and Native Mode Address Mapping ................................................ 651Table 232: OHCI[3:1]x48 reset values ....................................................................................................... 693Table 233: Reset mapping for EHCI[3:1]x04 ............................................................................................. 710Table 234: Register Mapping for SDHCx6[C:0:step4]............................................................................... 774Table 235: Field Mapping for SDHCx6[C:0:step4].................................................................................... 774Table 236: Reset Mapping for IOMUXx[E4:00]........................................................................................ 844Table 237: BIOS Recommendations for KbRstEn ..................................................................................... 868Table 238: BIOS Recommendations for UsbPhyS5PwrDwnEnable.......................................................... 875

18


19

Revision HistoryKB BKDG Revision 3.00 initial release.


1 Overview

This document defines AMD Family 16h Models 00h-0Fh Processors, henceforth referred to as the processor.• The processor overview is located at 2.1 [Processor Overview].• The processor is distinguished by the combined ExtFamily and BaseFamily fields of the CPUID instruc-

tion (see CPUID Fn8000_0001_EAX in 3.18 [CPUID Instruction Registers]).

1.1 Intended Audience

This document provides the processor behavioral definition and associated design notes. It is intended for plat-form designers and for programmers involved in the development of low-level BIOS (basic input/output sys-tem) functions, drivers, and operating system kernel modules. It assumes prior experience in personal computer platform design, microprocessor programming, and legacy x86 and AMD64 microprocessor archi-tecture. The reader should also have familiarity with various platform technologies, such as DDR DRAM.

1.2 Reference Documents

• Advanced Configuration and Power Interface (ACPI) Specification. www.acpi.info.• AMD64 Architecture Programmer's Manual Volume 1: Application Programming, #24592.• AMD64 Architecture Programmer's Manual Volume 2: System Programming, #24593.• AMD64 Architecture Programmer's Manual Volume 3: Instruction-Set Reference, #24594.• AMD64 Architecture Programmer's Manual Volume 4: 128-Bit and 256-Bit Media Instructions, #26568.• AMD64 Architecture Programmer's Manual Volume 5: 64-Bit Media and x87 Floating-Point Instructions,

#26569.• Software Optimization Guide for AMD Family 16h Processors, #52128.• Revision Guide for AMD Family 16h Models 00h-0Fh Processors, #51810• JEDEC standards. www.jedec.org.• PCI local bus specification. (www.pcisig.org).• PCI Express® specification. (www.pcisig.org).• Universal Serial Bus Specification (http://www.usb.org)• Serial ATA Specification (http://www.sata-io.org)• AT Attachment with Packet Interface (http://www.t13.org)• SD Host Controller Standard Specification (https://www.sdcard.org)• Alert Standard Format Specification (http://dmtf.org/standards/asf)

1.3 Conventions

1.3.1 Numbering

• Binary numbers. Binary numbers are indicated by appending a “b” at the end, e.g., 0110b. • Decimal numbers. Unless specified otherwise, all numbers are decimal. This rule does not apply to the reg-

ister mnemonics described in 3.1 [Register Descriptions and Mnemonics]; register mnemonics all utilize hexadecimal numbering.

• Hexadecimal numbers. hexadecimal numbers are indicated by appending an “h” to the end, e.g., 45f8h.• Underscores in numbers. Underscores are used to break up numbers to make them more readable. They do

not imply any operation. E.g., 0110_1100b.

20


1.3.2 Arithmetic And Logical Operators

In this document, formulas generally follow Verilog conventions for logic equations.

Table 1: Arithmetic and Logical Operators

Operator Definition{} Concatenation. Curly brackets are used to indicate a group of bits that are concatenated

together. Each set of bits is separated by a comma. E.g., {Addr[3:2], Xlate[3:0]} repre-sents a 6-bit value; the two MSBs are Addr[3:2] and the four LSB’s are Xlate[3:0].

| Bitwise OR. E.g. (01b | 10b == 11b).|| Logical OR. E.g. (01b || 10b == 1b); treats multibit operand as 1 if >=1 and produces a

1-bit result.& Bitwise AND. E.g. (01b & 10b == 00b).&& Logical AND. E.g. (01b && 10b == 1b); logical treats multibit operand as 1 if >=1 and

produces a 1-bit result.^ Bitwise exclusive-OR. E.g. (01b ^ 10b == 11b). Sometimes used as “raised to the

power of” as well, as indicated by the context in which it is used. E.g. (2^2 == 4).~ Bitwise NOT. (also known as one’s complement). E.g. (~10b == 01b).! Logical NOT. E.g. (!10b == 0b); treats multibit operand as 1 if >=1 and produces a 1-

bit result.=,