Predicting Package Level Failure Modes in … Package Level Failure Modes in Multilayered Packages ... o This paper provides a methodology for creating a high- ... o Some BGAs will

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Predicting Package Level Failure Modes in Multilayered Packages

Dr. Gil Sharon, [email protected]

February 18, 2016

© 2004 - 2007© 2004 - 20109000 Virginia Manor Rd Ste 290, Beltsville MD 20705 | 301-474-0607 | www.dfrsolutions.com

Speaker Bio:

o Research focus:

o Mechanical reliability of electronic systems and components

o Multidisciplinary reliability of complex electro mechanical systems

o Characterization and modeling of material behavior

o Physics of failure of electromechanical and MEMS system

o Mechanical performance of flip chip packages

o Doctoral research

o Solder reliability

o MEMS structures characterization

o Embedded components failure analysis

o Particle beam accelerator mechanical fatigue.

o Experience at Amkor technology

o Advanced product development group as senior engineer

o Analysis of chip-package interactions

o Ph.D, Mechanical Engineering (University of Maryland)

o Sales contact: Tom O’Connor [email protected]


“I want you to remember that everything I am saying may be

wrong and I want you to question everything that I’m

saying.”

-Nathan Myhrvold

Formerly Chief Technology Officer at Microsoft

Question Everything


o Package technology is constantly improving in order to

keep up with the advances in silicon technology.

o Multi layered packages exhibit several failure modes that

can be predicted using modern software tools

o This paper provides a methodology for creating a high-

fidelity model of the interposer with all the conductor

geometries.

o The two failure modes that are explored with this model

are package warpage prediction due to actual copper

imbalance and filled microvia delamination.

Introduction


o The substrate model was created from the multi-chip module (MCM) files of a 25 by 25mm coreless substrate. o Examples of multi chip modules:

Generating the Model

Source: Eric Bogatin, “Roadmaps of Packaging Technology”

1997, Integrated Circuit Engineering Corporation, ISBN: 1-

877750-61-1

o A 15 by 15mm piece of the substrate was cut out for this investigation.

o A three dimensional model of the substrate was created using the Sherlock tool.

o Every segment of geometry is modeled for every trace and material properties are assigned automatically by the software.

o The drill holes for every layer are also created and the whole layered model is exported to the Abaqus computer aided engineering tool.

Source: Rick Grigalunas, “Design

Engineers! 1 More Reason To

Use Bare Die.” ES Components

Blog March 19, 2015

Source: ACME Systems, ARM9

Linux Embedded Module, Aria G25

http://www.acmesystems.it/catalog_a

riag25

http://www.acmesystems.it/catalog_ariag25


Model Meshed in Abaqus

o Boundary conditions are applied and the whole model is meshed inside Abaqus.

o The resulting model for the top and bottom layer of the substrate are shown below

o Abaqus FEA is a software suite

for finite element analysis and

computer-aided engineering.


o The model can be modified to perform predictions for

several different phenomena because each trace and

via has a selectable geometrical entity.

Detailed Geometry

o The figure shows a

single trace in the

model after it has

been meshed.

o The laminate and

resin material is

invisible


o The analysis is this project is concentrated on predicting mechanical performance o The model can easily be converted to perform electromagnetic,

thermal and multi-physics simulations.

o The image illustrates the detailed cross section of several vias.

Analysis Objectives

o The level of detail shows

o Flanges

o Buried vias

o Different copper layer thicknesses

o Stacked vias

o This example employs a stacked via structure without staggered vias

Flange

Buried Via

Through Via

Stacked Via


o The model has 2,851,604 nodes and 2,044,465 elements.

o The model includes two materials.

o The copper material is isotropic and linear elastic and applied to the traces and vias.

o The buildup material is orthotropic.

o Some BGAs will have laminate layers

o The one in this analysis is coreless and the entire material is presumed to be buildup

The Model Characteristics

Source: http://www.toppan.co.jp/electronics/english/semicon/package/fc-bga/coreres/

http://www.toppan.co.jp/electronics/english/semicon/package/fc-bga/coreres/


Predicting Package Warpage

[4] Li, Yuan. "Accurate predictions of flip chip BGA warpage." Electronic Components and Technology Conference. IEEE; 1999, 2003

o Excessive warpage can hinder the creation of solder joints when a die is attached to the pads

o Malformed solder joints can lead to a higher probability of cracks forming in the joints.

o Package warpage is caused by copper imbalance between the two sides of the substrate stackup

o Prediction of package warpage can be performed using effective properties and simpler models

o An accurate model was useful for addressing the warpage issue successfully [4].

o The detailed model can provide information about localized effects of each via


Examples of Possible Issues Caused by Warpage

Source: Raiyo Aspandiar (Intel), “FCBGA Package Warpage” HDP User Group meeting


o This figure illustrates the displacement magnitude

o The warpage analysis was performed for a

temperature of -55°C and 260°C, with the reference

temperature 25°C

Warpage Plot


Predicted Diagonal Warpage

o This model is overkill for a simple warpage

calculation!

o At the high temperature, the diagonal

warpage is predicted to be 55µm or 2.1 mils

as shown


o Warpage

modeling along

with substrate

traces is bad for

computational

efficiency.

o Prohibitively

expensive

o Large packages

o Substrates with

many metal

levels.

A Simpler Approach

Source: http://electronicdesign.com/components/mechanical-modeling-advances-improve-semiconductor-packaging

Siva Gurrum, “Mechanical Modeling Advances Improve Semiconductor Packaging”, Electronic Design, Jun 3, 2014

http://electronicdesign.com/components/mechanical-modeling-advances-improve-semiconductor-packaging


o This analysis could be performed using effective properties or layered modelso It is more challenging to obtain the warpage effect on individual

vias.

o The image below shows the out-of-plane direction deformation

Warpage Analysis

o This plot indicates that wherever there are plated vias, the out-of-plane CTE mismatch of the buildup and copper is causing a small difference in localized deformation.

o This finding would be difficult to obtain for a coreless substrate without using the high fidelity trace and via model.


Microvia Delamination and Cracking Stresses

[8] Ning, Yan, Michael H. Azarian, and Michael Pecht. "Influence of

Plating Quality on Reliability of Microvias." IPC APEX Expo, 2015

o Microvias create the electrical connection between copper planes and pads in substrateso They are commonly used in packages with high input/output density and coreless

substrates are no exception

o They can be filled or unfilled

o They can be stacked, staggered or buried

o The image shows a cracked via flange due to CTE mismatch between the copper and the buildup.

o The location of the microvias and the shape of the stack has been shown to have an effect on microvia reliability

o Stress predictions using finite element models have been used to predict these stresses in simplified models [8].


o The stresses predicted by the model will allow the

substrate designer to highlight problematic areas

before going to production.

o This model only provides linear elastic stresses of the copper

structures but it can easily be modified to capture fatigue

effects.

o The results show that the shape of the stack has an

effect on the stresses in the copper.

o It is easier to concentrate on singular vias rather than

using a design rule when a stress map exists for all the

vias and pads.

Microvia Stresses at the Free Surfaces


Microvia Stresses at the Free Surfaces

o Red areas are above the ultimate stress of electroplated copper o Predicted to have a higher probability of cracking.

o The traces have a higher stress than the substrate underneath

o The pads that do not have a via underneath are at a relatively low stress and act as a stress redistribution layer for the solder attach.

Bottom Top


Microvia Pad Design

o The microvia stack and pad

design causes a lower stress

state on one pad compared to

the other

o Dog-bone design is a standard

routing pattern for high density

substrates for this reason

o The results show the added

advantage for copper stress

o This also alleviates stress from the

solder balls after assembly


Stacked Microvia Stresses

[1] Suk-Kyu Ryu, Kuan-Hsun Lu, Jay Im, Rui Huang and Paul S. Ho , “Stress-Induced Delamination Of

Through Silicon Via Structures” in AIP Conf. Proc. 1378, 153 (2011); doi: 10.1063/1.3615702

[3] Ming-Han Wang, Mei-Ling Wu “Thermo-mechanical Stress of underfilled 3D IC packaging” IEEE

EuroSimE, 7-9April, 2014

o The copper stress at the free surfaces are only one part of the stacked via.

o The vias have structures that go through the entire substrate and the stresses can be higher in the middle of the stack than the flanges.

o The stress field induced by differential thermal expansion in the via is three-dimensional in nature [1].

o We need to compare the Von-Mises stress with the first principal stress in order to lookat the interfaces of the stacked vias.

o The Von-Mises stress is appropriate whenlooking at the ductile failure of copper at theflanges and barrel but the interfaces betweenvias are more susceptible to brittle fracture [3].

o The Von-Mises stress plot shows the stress distribution in a stacked via. The high stress regions are at the bottom interface, an inner interface and the flange.


o Myers, Alan M., et al

o “As a result of different thermal expansion coefficients of the

metal interconnects, vias, and insulating layers, the via connections

are subjected to large amounts of stress as the device is

temperature cycled.

o Various residues consisting of fluorides and oxides, formed during

the via etch process, are generally left at the interface prior to

via metallization.

o These fluorides and oxides are generally brittle materials and

when subjected to large amounts of thermal stress, crack and

cause via delamination.”

o The Via interface is more susceptible to brittle fracture

Explanation of Stresses

Source: Myers, Alan M., et al. "Via hole profile and method of fabrication." U.S. Patent No. 5,470,790. 28 Nov. 1995


First Principle Stress Plot for Stacked Via

[11] Yeoh, Hwai Peng, et al. "Flip chip pin grid array (fc-

pga) packaging technology." Electronics Packaging

Technology Conference, 2000.(EPTC 2000). Proceedings

of 3rd. IEEE, 2000.

o The figure below shows the first principle stress in the same stacked via as previously shown.o The two plots can be compared to show that the high stress in the via to pad

interface is of greater concern for causing brittle fracture.

o Failure analysis performed at Intel corp. (ADT) claims that “via delamination occurred at the interface between the first electrolytic Cu and electrolessCu” [11].

o The first principal stress plot indicates that the interface is loaded in the tensile direction and predicts this failure mode.

o The Von-Mises plot indicates that while the flange is more susceptible to ductile modes of failure it is not at risk for brittle fracture.


o The stress plots for the substrate enable the board

designers to predict many reliability issues.

o Not just warpage and Via delamination

o The high-fidelity model provides the predictive capability

o Allows designers to adjust the layout before any manufacturing

has taken place.

How Does this Help Designers


o Making a full three dimensional finite element model

used to be a difficult and lengthy process.

o Detailed trace approach used to be prohibitively

expensive for large packages and substrates with many

metal levels [2].

o Expert modelers spent many hours to create the models

from layout files.

o It is more efficient to allow software to create the high

fidelity substrate model automatically.

o Automation allows the reliability experts, who need not

be modeling experts, to directly interact with the

substrate model.

Conclusions

Source: Gurrum, Siva, “Mechanical Modeling Advances Improve Semiconductor Packaging” in

Electronic Design, Jun 3 2014


o The stresses in the filled microvias are shown to be affected by the stack properties.

o Both ductile and brittle failures can be predicted using this modeling method.

o The Von-Mises stresses at the flange of the vias are indicative of the ductile cracks.

o The first principal stress at the via and pad interfaces are predicting a high probability of delamination due to brittle fracture.

o The stresses in the traces are also helpful in designing substrates that can decrease localized stresses using different copper trace geometries.

o All three copper stress predictions were made possible by the high fidelity model of DfR’s Sherlock Software

Conclusions (continued)


o This project highlights the advantages of using automation

of model creation to improve modeling techniques.

o The constant demand for improved component packaging

is driving the demand for improved modeling techniques.

o The advanced Sherlock software trace modeling

capabilities improve the modeling capabilities while

shortening the model creation time.

Highlights (If you remember nothing else…)


Thanks

Greg Caswell and Gil Sharon

DfR Solutions

301-640-5825 301-640-5804

[email protected] [email protected]

mailto:[email protected]

mailto:[email protected]

Documents

Predicting Package Level Failure Modes in … Package Level Failure Modes in Multilayered Packages ... o This paper provides a methodology for creating a high- ... o Some BGAs will