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Pre-Processing Filter for Pre-Processing Filter for Audio ApplicationsAudio Applications
By Nathan Shaw, Lerzan By Nathan Shaw, Lerzan Celikkanat, and Xiangfeng WangCelikkanat, and Xiangfeng Wang
ELEC 422 VLSI Design 1 Fall 2005
OverviewOverview Implementing a low pass FIR filterImplementing a low pass FIR filter
4 taps4 taps 8-bit I/O, Two’s Complement8-bit I/O, Two’s Complement Major Components:Major Components:
FIFOFIFO 8-bit multiplier8-bit multiplier 16-bit adder16-bit adder PLA: control unit/ROMPLA: control unit/ROM
Filter Block DiagramFilter Block Diagram
ROMROM
6 words x 8-bits6 words x 8-bits Coefficient determined by Coefficient determined by
Control Unit by way ofControl Unit by way ofdecoder decoder
Control UnitControl Unit
INPUTS: Restart FailSafe NewInput;INPUTS: Restart FailSafe NewInput; OUTPUTS: S1 S2 S3 C0 C1 C2 Shift OUTPUTS: S1 S2 S3 C0 C1 C2 Shift
LoadI LoadC LoadMul LoadX LoadSum LoadI LoadC LoadMul LoadX LoadSum LoadFinal Clr1 Clr2LoadFinal Clr1 Clr2
WAITSelect coeff α3
GOTSIGNALLoad signal
S2=0
IDLEClear registers
Load RAM with zeros
SHIFT3 times
MULLoadI=1LoadC=1
ADDLoadMul=1LoadX=1SUM
LoadSum=1
STORELoadX=1Clr1=1
State MachineState Machine
Shift Select next coeff
X 4FINAL
LoadFinal=1
BYPASSS3=1
LoadI=1
(0,d)
(1,d)
(d,1)
16-bit Carry Ripple Adder16-bit Carry Ripple Adder
Composed of four 4-bit carry ripple addersComposed of four 4-bit carry ripple adders Two 16-bit inputs and one 16-bit outputTwo 16-bit inputs and one 16-bit output
MultiplierMultiplier
8 bit x 8 bit8 bit x 8 bit 16 bit output16 bit output
MultiplierMultiplier
FIFOFIFO
8 elements deep8 elements deep 8 bits wide8 bits wide
Output => αOutput => α33*x*x00 + α + α22*x*x11 + α + α11*x*x22 + α + α00*x*x33 + x + x44
xx44
xx33
xx22
xx11
xx00
xx00
XX44
XX33
XX22
xx11
xx44
xx33
xx22
xx11
xx00
xx11
xx00
xx44
xx33
xx22
xx44
xx33
xx22
xx11
xx00
xx33
xx22
xx11
xx00
xx44
xx44
xx33
xx22
xx11
xx00
xx22
xx11
xx00
xx44
xx33
shift1 shift2 shift6shift4 shift5
* α3
shift7shift3
* α2 * α1 * α0 * 1
OutputsOutputs
T0 => T0 => xx00 T1 => T1 => αα00*x*x00 + x+ x11 T2 => T2 => αα11*x*x00 + α+ α00*x*x11 + x+ x22
T3 => T3 => αα22*x*x00 + α+ α11*x*x11 + α+ α00*x*x2 2 + x+ x3 3
T3 => T3 => αα33*x*x00 + α+ α22*x*x11 + α+ α11*x*x2 2 + α+ α00*x*x3 3 + x+ x44
Tn => Tn => αα33*x*xn-3n-3 + α+ α22*x*xn-2n-2 + α+ α11*x*xn-1 n-1 + x+ xn n