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Practical debugging

and testing BGA

by David KimParamit Co.

Oct. 11th, 2007

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PCB1

$4.5k with BGAs ( $50~$800 each)

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PCB2

$3.5k with BGAs ( $50~$800 each)

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PCB3

$5k with BGAs ( $100~$700 each)

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MOREs with BGA

PCB: More PCBs with BGAs More expensive PCBs with expensive BGAs More tests on BGAs More complicated tests (BSCAN and Silicon nail test)

ICT: More false BGA failures

More rework on false BGA failures More rework and replacement cost on false BGA failures More troubleshooting time on false BGA failures

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More false BGA failure More Rework and materials

More Time and $= $ Loss

Less false BGA failures Less rework and materials

Less Time and $ cost= $ Profit

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Testing BGA

pins < connectcheck < testjet (

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Test coverage on BGA

testjet/VTEP has less test coverage on Shielded BGA and micro BGA.

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BGA Rework

Bake - takes long hours. 8 ~ 24Hs

Reflow Reball - not as good as a new one

Replace - expensive BGA

Retest - may still show false failure

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False BGA failures with BSCAN test

Caused by

Contact problem (dirty nail bed, dirty probe, contaminated test vias, etc) Signal delay caused by contact resistance

Missing and improper disables

Random initial condition after power-on Unpredictable bus contention during the output test

Other defected devices

etc.

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Verifying BGA failures

Check Test target(s) - probe, test via(pad) Continuity from Test point to BGA pin

R and Diode test comparing with the KGB

Testing only failed pin in input mode forinput/bidirectional pin or in output mode foroutput pin.

Test with longer vector cycle/receive delay Set TCLK at dh3.3/dl-0.2 and slew rate 250

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R and Diode test

on failed pin to Pwr/GND R test

Internal pull-up R, pull-downR, or internal circuitimpedance to Power orGround

Diode testCMOS SCR Latch-upresistant circuit as ESDprotection on bidirectionalbus has diodes to power andground.

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Separating output-only pins

Separate output-only pins from each connect test.

Use test inputs only option for bidirectional pins andinput-only pins

Create a script to split digital/unn_connect_xinto digital/unn_connect_x_out and digital/unn_connect_x_in

ex.

$ dksplite_bscan u14$ dkrdtest_bga_pin u14.ac5

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!"tundra310.bsd", "HPBGA_304_23x23", no-- STD_1149_1_1994 VHDL Package and Package Body

--------------------------------------------------------------------------

entity tsi310 is

generic (PHYSICAL_PIN_MAP : string := "HPBGA_304_23x23");-- Port List

port (

S_DEVSEL : inout bit;

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!itl digital/u3d1_connect_c

connect "u3d1"ground bounce suppression on

family "TTL_3V3"

!IPG: Connect test generated with CONNECTMAX value of 25

test inputs only !* tests bidirectional pins as input and ignores Output pins.chain "u3d1_u3d1"

tdi "PCIX1_TDO"

tdo "CE_TDO"

tms "CE_TMS" family "CMOS_3V3"

tck "CE_TCK5"

devices

"u3d1", "_bsdl_lib/tundra310_ok.bsd", "HPBGA_304_23x23", no

end devices

end chain

vector cycle 900nreceive delay 800n

set ref on nodes "CE_TCK5" to dh 3.3, dl -0.2set slew rate on nodes "CE_TCK5" to 250

nodesfixed low "NETIFPCIXPD_OPAQUE_EN" test "u3d1.AA18"

node "NETIFS_AD0" hybrid test "u3d1.AA9" !*binode "NETIFS_GNT1_L" hybrid test "u3d1.AA19" !*outnode "NETIFS_GNT2_L" hybrid test "u3d1.AB1" !*outnode "NETIFS_GNT5_L" hybrid test "u3d1.AB4" !*out

end nodes

end connect

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itl without "test inputs only"

------------------------------------------------------------------------------

AGILENT 3070 VCL Wed Sep 26, 2007 09:40:12 AMdigital/u3d1_connect_bx.vcl

------------------------------------------------------------------------------

C O M P I L A T I O N S U M M A R Y

-------------------------------------

4050 vectors executed.

27 Vector RAM slots used, 0 % full.

1026 Sequence RAM slots used, 0 % full.

110 Directory RAM slots used, 0 % full.

P I N S T A T E R E P O R T

-------------------------------

DEVICE PIN STATESPIN NODE TYPE EXECUTED

--- ---- ---- ----------CE_TCK5 DRIVE D0 D1

CE_TDO RECEIVE R0 R1

CE_TMS DRIVE D0 D1

CE_TRST_L DRIVE D1

CENTRALPU_OE_B DRIVE D0

HARDRESET_L DRIVE D1

NETIF_STITCH DRIVE D1

NETIFS_AD0 **bi** BIDIRECTIONAL D0 D1 R0 R1NETIFS_GNT1_L **out* RECEIVE R0 R1NETIFS_GNT2_L **out* RECEIVE R0 R1NETIFS_GNT5_L **out* RECEIVE R0 R1PCIX1_TDO DRIVE D0 D1

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* itl with "test inputs only"

------------------------------------------------------------------------------

AGILENT 3070 VCL Wed Sep 26, 2007 09:42:45 AM

digital/u3d1_connect_bx.vcl

------------------------------------------------------------------------------

C O M P I L A T I O N S U M M A R Y

-------------------------------------

2504 vectors executed.

24 Vector RAM slots used, 0 % full.764 Sequence RAM slots used, 0 % full.

72 Directory RAM slots used, 0 % full.

P I N S T A T E R E P O R T-------------------------------

DEVICE PIN STATESPIN NODE TYPE EXECUTED

--- ---- ---- ----------CE_TCK5 DRIVE D0 D1

CE_TDO RECEIVE R0 R1

CE_TMS DRIVE D0 D1

CE_TRST_L DRIVE D1

CENTRALPU_OE_B DRIVE D0

HARDRESET_L DRIVE D1NETIF_STITCH DRIVE D1

NETIFS_AD0 **bi** BIDIRECTIONAL D0 D1NETIFS_GNT1_L **out* RECEIVENETIFS_GNT2_L **out* RECEIVENETIFS_GNT5_L **out* RECEIVEPCIX1_TDO DRIVE D0 D1

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Improving BGA test for less false failures

put pins test at the beginning of the test

apply connectcheck to each BGA as well as testjet (VTEP is

better). apply vector cycle and receive delay ( 500n~1000n/400n~900n)

with the regular fixture maintenance.

Separate output-only pins from inputs-only or bidirectional pins

Test bidirectional pins as only input with test inputs only option.(Use dktools to split in/out/bi/single pin automatically.)

Separate the unstable pin(s) from other pins. ( good for pins with!IPG: Disable problems, ..)

Use debugging tool for BGA failures to verify the result as falsefailure or true failure, such like testing R and diode junction of thefailed pin to power and ground.

Option: X-ray test with 5Dx or others, if needed.

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Conclusion

By improving the existing ICT test for BGAs, the numberof false failures is reduced.

(more than 50%, depending on the program quality and the complexity of the circuit). False BGA failures can be efficiently verified with

improved BSCAN test and R/Diode test. BSCAN test can be efficiently developed and debugged

more stable with the automated scripts.

Shorter development time and less sustaining time

Less false failures Less rework and replacement Time and $ saving

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Need dktools and my help ?

David KimTest Development Manager

Paramit Co.

Ph) 408-782-2445

dkim@paramit.com