Power Semiconductorsuploads.cq-dx.ru/pdf/TDA/tda1688p.pdfThe Power Combi Control-lC TDA 16888 includes the PWM control for an SMPS and the control for the preconverter to improve the

Product Information 01.98

Power SemiconductorsTDA 16888High Performance Power Combi Controller

http://w

ww.siemens.d

e/

Semiconductor/

Edition 01.98

Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation, Balanstraße 73, 81541 München.

© Siemens AG 1997. All Rights Reserved.

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuitsimplemented within components orassemblies.The information describes the type ofcomponent and shall not be consideredas assured characteristics.Terms of delivery and rights to changedesign reserved.For questions on technology, deliveryand prices please contact theSemiconductor Group Offices inGermany or the Siemens Companiesand Representatives worldwide (seeaddress list).Due to technical requirementscomponents may contain dangeroussubstances. For information on thetypes in question please contact yournearest Siemens Office, SemiconductorGroup.Siemens AG is an approved CECCmanufacturer.Packing

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Components used in life-support devices or systems must be expresslyauthorized for such purpose!

Critical components1 of the Semi-conductor Group of Siemens AG, mayonly be used in life-support devices or systems2 with the express writtenapproval of the Semiconductor Group of Siemens AG.

1 A critical component is a componentused in a life-support device or systemwhose failure can reasonably beexpected to cause the failure of thatlife-support device or system, or toaffect its safety or effectiveness of thatdevice or system.

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Introduction

Functionality and Benefits

PFC Preconverter

PWM Converter

PFC and PWM Gate Drive

Oscillator and Synchronisation

Siemens Aktiengesellschaft3

TDA 16888 – High Performance Power Combi Controller

IntroductionTDA 16888 is designed for newgenerations of off-line SwitchedMode Power Supplies (SMPS) with optional universal input andPower Factor Correction (PFC) e.g.for PCs, Monitors, CTVs and industrial applications.

Functionality and BenefitsThis high performance SMPS Power Combi Controller is optimi-zed to reduce system costs, supports solutions for global requi-rements, generates less EMI andis designed by FMEA rules.

The TDA 16888 allows load variations down to zero watts andcontrols low power standby opera-tion by switching off its PulseWidth Modulation (PWM) stage.

AC/DCInput90 V - 270V

Output 1

Output N

AUX/Standby

380 V DC

TDA 16888TDA 16888

Figure 1 Basic Application Circuitry

Siemens Aktiengesellschaft 4

The Power Combi Control-lC TDA 16888 includes the PWMcontrol for an SMPS and the control for the preconverter to improve the power factor and toreduce the harmonics of the ACinput current. Both sections are internally synchronized on the same operating frequency.

The preferred topology of the PFC preconverter is boost, but fly-back is possible, too. The PWMsection can be designed as a for-ward or as a flyback converter. Maximum duty cycle of the PFC is about 94%, in order to achieveminimal line current gaps. Maxi-mum duty cycle of the PWM is limited to 50% to prevent transformer saturation.

There are monitoring and protec-tion functions such as broken wiredetection, undervoltage and dualstep overvoltage monitoring of thebus voltage, peak current limitationfor PFC and PWM section and undervoltage lockout of the IC supply voltage. The Combi-lC TDA 16888 is designed with respect to a Failure Mode EffectAnalysis (FMEA).

The limitation of the PWM duty cycle, i.e. the leading edge PFC-and the trailing edge PWM operation, are done in a digital wayby flip-flops. Handling the signalsthis way meets the requirementsfor an external synchronisation. On the other hand an oscillator isnecessary that operates at twiceof the operating frequency. For alower current consumption andhigher EMI resistance the capaci-tor of the oscillator is integrated.The operating frequency is set byonly one resistor. The operatingfrequency can be increased by asink current in parallel to this resistor. There is an additional synchronisation input that can beused for frequency adjustment orin connection with a phase lockedoperation.


100 V

0%

10%

90%

100%

2 ms

Rectified AC Input Voltage

(100 V/Div)

AC Input Current

(0.5 A/Div)

10 mV


Figure 2 Input Signals

PFC PreconverterIn normal operation the PFC sec-tion of TDA 16888 operates withdual loop control. A first controlloop controls the shape of the linecurrent by average current controlenabling either continuous or dis-continuous operation mode. The second loop controls the DC bus voltage. There is a thirdcontrol loop available that enablesthe PFC section as an auxiliary power supply even when thePWM section is disabled. Duringstandby operation mode (disabledPWM) the PFC section is opera-ting with half of its nominal opera-ting frequency in order to save operating power.

Rectification of an AC voltage andsmoothing with an electrolytic capacitor effects a peak currentduring the peak input voltage and a break in current flow during therest of the half period of the linefrequency. The RMS value of sucha pulsed input current is about twice of a sinusoidal current andthe harmonics of that pulsed current effect EMI to other devi-ces. The power factor is the relati-on between real input power to apparent input power. With a typical main voltage rectification inelectronic devices the power fac-tor is about 0.5. Standards to improve the power factor will become effective in the near future.

But system cost must not increaseby introduction of power factorcorrection. It depends on the output power and features like theoption to supply a device from different line voltages.


6

V IN

IIN Fuse L1 L4

RFI

R36A

R29

R28

R30

R27

+

90 V –270 V AC

D10

Q3

AUX1

D12...D15D11

Means two resistors in series

C24

C18

C25

C26

C1

PIN1 PFC IAC Input ACPIN2 Reference VoltageVREFPIN3 Current CompensationPFC CC

Current SensePIN4 PFC CSGround SensePIN5 GND SCurrent LimitationPFC CLPIN6GroundGNDPIN7Driver OutputPFC OUTPIN8Supply VoltagePIN9 VCC

PIN10 Driver OutputPWM OUTPIN11 PWM CS Current Sense

SynchronisationSYNCPIN12PWM SSPIN13 Softstart

InputPWM INPIN14PIN15 PWM RMP RAMP Voltage

OscillatorROSCPIN16PFC FBPIN17 Feedback

Voltage CompensationPFC VCPIN18Voltage SensePFC VSPIN19

PIN20

150 W Feed-Forward Multioutput SMPS for PC

AUX VS Auxiliary Voltage Sense

100 V

100 V

0%

10%

90%

100%

2 µs

PFC Drain-Source Voltage

(100 V/Div; On-Time 7.5 µs,L)

PWM Drain-Source Voltage

(100 V/Div; On-Time 3.5 µs,L)

Figure 3 Output Signals

Figure 4 Application Circuitry

Siemens Aktiengesellschaft

The most efficient way to correctthe power factor with an active circuitry is to use a boost converter.Most of the energy flowing fromthe input via rectifiers to the buscapacitor bypasses the switching transistor of the boostconverter. Connecting the boostpreconverter to the line, an inrushcurrent occurs due to charging thebus capacitor. As the capacitanceof the bus capacitor is between

three to ten times lower than withconventional rectification, the inrush current is much smallereven without additional measureslike NTCs.

There is a peak current limitation(Pin 6) to prevent an overload ofthe boost transistor during inrushcurrents and during maximum load, which occurs for example after turn on to charge the bus capacitor. The turn off threshold

is designed at +1 V to meet FMEArequirements. A broken wire to Pin 6 activates the current limitation. Another comparator (C2)at Pin 19 is detecting a broken wireto the bus voltage sense. At least20% of nominal bus voltage is necessary to make the Combi-lCactive. This feature has to be takeninto account when testing the IC atlow input voltages.

7 Siemens Aktiengesellschaft

L2

R31

C19 C20

C29

R26

R35

R25

R34

Over-voltage

4 5 3 8 17 187

STANDBY EA

9

Current EA

12 2 20 15 13 14 1116 10

Voltage EA

5 V

5 V

AUX1

VBUS = 380 V DC

+ +

+ +

C15 C28

C34

C31

C3A

L3 L5R41

+

19

R8

R13

R16

R19

R32R9

R37

R47

30C

R42

R40

R11

R6

R10

R15

R39

R24 R23

R33

R4A

R43

R5R4BR3R2R1 R7

R12

R14

R17

R18

R 20R22

+

R21

R38

Off=Standby

SoftStart

D1...D4

D5

D6

D7

Tr.1

Q1

Q2

SIPMOS600 V

SIPMOS1000 V

D16...D19

IC5

IC3

IC4

D9

D8

IC1

IC2

5 V20 A

C33

+ +C36 C37

C35 L3 L6R45

R46

32C

R44

D21

D2012 V4.2 A

+C38

L3

R48D23D24

-12 V1 A

5 V100 mA

IC6

Q4C11A C12 C22C13 C14

C23C11

C9

C4

C2

C3

C8C10 C7 C6 C5 C16

C27

C39 C42

C17C21C41

5

6

PWM

Currentlimitation

StartupUVLO +

+

OSC

PFC

VREF

16

The typical startup of the Combi-lCis supported by the undervoltagelockout (UVLO) feature of the IC.Via a highly resistive resistor (R2) a capacitor (C11) is charged up to a threshold of 14 V at Pin 9. Duringthis operation the current consumption of the IC is less than100 µA. Reaching this thresholdthe IC becomes active sending drive pulses to the boost transistorQ1. During this operation thePWM section is not active yet inorder to save supply current. Thesame reason is for driving theboost transistor with only half ofthe nominal operating frequency.Capacitor C11 has to be designedlarge enough that the circuitry isable to supply the IC before thevoltage at Pin 9 reaches the turnoff threshold of 11 V.

The power supply of the Combi-lCcan be realized by a separate win-ding on the boost converter choke.Our proposal is to use a bridge rectifier on the auxiliary windingAUX 1. In this way a current canflow at low input voltages in flyback mode and at high input voltages in forward mode. The minimum supply voltage at capacitor C18 will occur at an inputvoltage level half of the bus voltage.

There is another operating condition when the supply voltageat C18 becomes low, i.e. at disabled PWM section and highinput voltages. This condition maybe the worst for the auxiliary power supply. In this applicationwe got the power to supply theCombi-lC during all operating conditions and in addition the circuit offers an isolated auxiliaryvoltage of 5 V / 100 mA.

An increase of output power of theauxiliary power supply will be anoption of future applications. In order to continue the descriptionof the auxiliary power supply thereis a separate control loop and a separate output of the boostconverter via diode D6. This additional circuitry is necessary toget a fast response at load changes. There are operating conditions resulting in an overshoot at the bus voltage thatwould stop the boost transistor formore than 100 ms. With the second output of the boost con-verter via D6 a not working transi-stor can be detected within 100 µsand the transistor can be turned onin a way, that the auxiliary outputgets power but not the main output to the bus capacitor. Duringthe standby operation the bus voltage remains at nominal level.The separate control loop can beactivated by itself, when the second output of the boost con-verter via D6 is designed for an output voltage slightly below thenominal bus voltage (e.g. 5%). Theload (R2) which is necessary at thesecond output can be used for thestartup of the Combi-lC.

The PFC section is working initiallyat half of the nominal operatingfrequency until a level of 20% below the nominal bus voltage isreached. Then the PWM section is able to run with a soft start (Pin 13) with nominal operating frequency on both sections or if it is disabled by transistor Q4, thenthe system is running in the standby mode with half of its nominal operating frequency.

Usually there is an overshoot during the charging of the bus capacitor. The reason is the longresponse time of the bus voltagecontrol loop. There is a first over-voltage threshold at 10% abovenominal bus voltage. The operationof the boost transistor is turneddown via OTA2 and the Multiplierto avoid increasing bus voltage. A second threshold at 20% abovenominal bus voltage will stop PFCand PWM section immediately until the bus voltage reaches a level of 10% above nominal busvoltage. This feature protects thepower supply during hazardousmains overvoltages in combinationwith varistor R30.


Figure 5 Dynamic Characteristicsof the Multiplier

0

100

200

300

400

500

0 1 2 3 4 5 6 7V

µA

270 V AC for10% NominalOutput Power

180 V AC90 V AC

8004002001005025

AµAµAµAµAA

µµ

Input Current (Pin 1)

Out

put C

urre

nt (P

in 4

)

Input Voltage (Pin 18)

270 V AC forNominalOutput Power

180 V AC90 V AC

At typical operating mode of thePFC section a DC output signalwith a small superimposed AC ripple can be found at the outputof the voltage error amplifier OP1at Pin 18. This signal is multipliedby the current at Pin 1, derivedfrom the rectified AC input voltage.Consequently a multiplier outputcurrent shaped like the input voltage is achived, that can be varied in amplitude by the voltageerror amplifier OP1.

A second error amplifier OP2 controls the input current like theset value of the multiplier output.In order to enlarge the effect ofthe voltage error amplifier OP1there is an exponential function atthe voltage input (Pin 18) of themultiplier included (cf. Figure 5).

Furthermore there is an OTA3 thatcares for the stability of the busvoltage during light load and no load conditions.This is achieved bycompensating the multiplier outputcurrent as long as the output voltage of OP1 is well below 1.2 V.

The ramp voltage of the PFC pulse width modulation starts from a higher voltage level of 6 Vdecreasing to the minimum of 1 V.The reason for this shape which is invers to commonly used ramp voltages is that the feedback ofOP2 can be connected to the current sense input (Pin 4). In thisway the sensed signal is smoothedand the levels at Pin 4 can be keptwell above 0 V.



9

Figure 6 Block Diagram of TDA 16888

(output disable)

4 V

Power Management

–+

+–

–

–

–+

–

–

FB

5 V

1.2 V

D2D1

D4

M3

QM

M2M1

5 V

D3

1 V

1 V

5.5 V

6 V5.5 V

0.4 V

1 V

C10

FF2

FF1

C9

C8

C7

C5

OP3

Z2

x5

V1=1.5 V

10 kΩ10 kΩ

100 kΩ

OSC

6 V 0.45 V0.4 V

7.4 V

Undervoltage Lockout11 V - 14 V

Z1

Z317.5 V

T1

I1=30 µAQR

S Q

17

PFC PFCVC

VCC

VCC

VCC

18CS

4

PFC

20

AUXS5

GNDCC

3

PFC

19

PFCCL

6

PFC

9 8

PFCOUTVCCVSVS

1PFC IAC

2SYNC

12 16PWM SS

13PWM IN

14PWM RMP

15

+–

+–

+–

C6

OP1

+–

C1

+

OTA1

+–

OTA2

+

C4

+–

–

C3+

OTA3

–+

C2+

OP2+

PWM CS11

GNDROSCVREF7 10

PWM OUT

QSR Q

R1

R3

R2

PWMBias

Control

Voltage Reference 7.5 V

PWM ConverterThe PWM section operates withimproved current mode control,with effective slope compensation,spike suppression and especiallywith amplified signal levels at thepulse width comparator. The PWMsection can be disabled by a short(controlled by transistor Q4) acrossthe soft start capacitor.


OutputCurrent EA

0t

t

t

1.0 V

0

V PIN 14

t

6.5 V max

0.4 V

H

t

0

6 V

1 V

L

L

L

L

H

t

H

t

Internal Clock

H

t1 V

0

5 V

VCOSC

2

16

7

VREF = 7.5 V

ROSC

Simplified Equivalent Circuitof the Oscillator Frequency Setting Circuitry

GND COSCROSC

PWM Current Sense Voltage (Pin 11)

PWM RAMP Voltage (Pin 15)

PFC OUT

Internal PFC RAMP Voltage

MAX Duty Cycle PFC

MAX Duty Cycle PWM

Figure 7 Typical Shape of Signals

The PWM converter starts with a soft start at a bus voltage higherthan 80% of its nominal value.Operating frequency is the nomi-nal and the same like that of thePFC preconverter. The transistor ofthe boost converter turns on withleading edge and that of the PWMturns on with trailing edge, delay-ed in minimum 50% of the operati-on period.

The way of control is an improvedcurrent mode. There is a capacitorat Pin 15, by means of which a basic ramp voltage is generatedfor slope compensation. This voltage is superimposed by the times 5 amplified voltage dropacross the shunt resistor (R15) fedover an internal 10 kΩ resistor inorder to suppress spikes. The resultis a ramp voltage with a maximum level up to 6.5 V. Correspondinglythe active input range of the PWMinput (Pin 14) is from 0.4 V to 7 V.The higher level on the PWM com-parator cares for better resistanceagainst EMI and better stability ofoperation (cf. Figure 3). In additionthe current sense input (Pin 11)feeds a fast comparator (threshold = 1 V) for current limitation.

PFC and PWM Gate DriveThere is a new design for the gatedrive of both sections. The employed totem pole configurationavoids cross conduction currentsand has a voltage modulated turnon slope. The turn on slope increases moderately between 0 Vand 3 V, increases slowly between3 V and 5 V and increases mode-rately above 5 V up to the maxi-mum of 12 V. The reason for thisimproved rising edge is a possiblefast turn off as soon as the currentlimitation is activated, a con-tinuously reduciable duty cycle down to zero and a soft currentcommutation from the boost oroutput diode to the transistor. Thevoltage modulation meets thesedemands independent of the loadcapacitance. The turn off is fastwith a current capability of about1.5 A peak.

When operating the Combi-lC below the undervoltage threshold,the drive outputs are active low.

Oscillator and SynchronisationThe oscillator operates with an integrated low tolerance capacitorand a special voltage and tempera-ture compensated current mirrorset by only one external resistor atPin 16. The integration of this capacitor operating with a rampvoltage of 5 V increases the resis-tance against EMI and saves supplycurrent due to its small value. Theinternal oscillator operates withtwice of the external operating frequency for exact limitation ofthe PWM duty cycle below 50%by flip-flops. In the same way theleading edge turn on of the PFCand the trailing edge turn on of thePWM is generated. Therefore the operating frequencycan be changed during operationonly by bypassing a current to theset resistor R24.

Changing the frequency by the setcurrent at Pin 16 does not influencethe amplitude of the internal rampvoltage of the PFC pulse widthmodulation but will influence theexternal ramp voltage of the PWMat the external capacitor C13.


11 Siemens Aktiengesellschaft

90%

100%

200 ms

Gate Drive Voltage

(5 V/Div)

Drive Current to BUZ 91

(0.5 A/Div)

10 mV

5 V

10%

0%

Figure 8 Gate Drive Signals

There is a synchronisation inputPin 12. A high level signal (3.5 V - 7.5 V) discharges the inter-nal oscillator capacitor. Corre-spondingly a low level signal (below 0.4 V) enables the chargingwith the set current (R24). The internal oscillator can be completely superimposed by anexternal synchronisation signal.However the influence on the internal ramp voltages has to betaken into account.

For a synchronisation over a widefrequency range the variation ofthe set current at Pin 16 is to bepreferred. For a synchronisation,which will alter the set frequencyup to 20% the synchronisationinput may be the better choice.

Example for External Synchronisation:

Synchronisation of the Combi-lCTDA 16888 to a Reference Frequency by a Phase-LockedLoop (PLL)

The switching frequency of the Power Factor- and PWM controllerTDA 16888 may be synchronizedto a reference frequency e.g. of aCRT monitor by using the standardPLL-CMOS-IC 4046.

12

PWM

=

Over-

Startup OSCVREF SoftStart

R31

=SIPMOS1000 V

IC1

V IN

IINFuse

AUX1

AUX1

L1

L2

L4

RFI

R36A

C19

C73

R29

R26

R35

R25

R34

R1 R2

R28

R30

5 17 18

VBUS = 380 V DC

+

C20

C71

C40

C3A

+

R72

R8

R13

R16

R32

R9

R49

R11

R6

R10

R15

R27 R24 R23

R3 R4B

R4A R43

R5 R7

R12

R14

R17

R18

R22

90 V –270 V AC

D1...D4

D5

D22

Tr.1

Q1

Q2

SIPMOS600 V

D16...D19

IC3

IC4

D71

C76 +C74

R74

D72

C79 +C77

R76

D73

C82 +C80

C83

R78

D74

C85 +R80

D75

Q4

D10

Q3

D12...D15

D11

Means two resistors in series

C24

C18

+

C11AC11

C12 C22C13 C14

C23

C10

C9

C4

C3

C8 C7 C6 C5

C39

C21

C41

C25

C26

C1

SYNCInput

=

R60

+

+

=

=

+

D6

5

43

1

UVLO

Currentlimitation PFC Voltage

SynchronisationCircuit

L

IC5

Current EA

36 1 4 8 7 19

STANDBY EA

Voltage EA

9 12 2 20 15 13 1416 1110

5 V

5 V

C2



This device is supplied by the 7.5 V reference output VREF (Pin 2)of the TDA 16888. Generally the4046 controls the output current ofPin 16, which allows to set-up theswitching frequency by the internal oscillator.

The PWM output signal at Pin 10is fed back via a voltage divider(R50, R51) to Pin 3 of the 4046. Pin 14 of the 4046 is the input ofthe given reference frequency sig-nal, fed from a separate windingon the deflection transformer, andcompared internally by using phasecomparator II.

The level of the phase comparator IIoutput signal (Pin 13) representsthe phase difference between thePWM output and the referencesignal. Pin 13 feeds a low pass filter to provide VCO IN (Pin 9) ofthe 4046 with the average of thephase difference value. The VCOis not used, but the signal is ampli-fied by the internal source follower.

The DEM OUT (Pin 10) controls thebase current of Q6 and in this waythe oscillator of the TDA 16888.R24 and R52 set the minimum andmaximum limits of the frequency(adjusted to approximately 30 kHzand 120 kHz respectively).

The phase comparator II output signal at Pin 13 is filtered by R55and C44 and fed into the VCO inputat Pin 9. In addition a dynamicfeedback from collector of Q6 is fedinto Pin 9 via Q5 and its network.The capacitors C43 and C47 bypasshigh frequent currents. The res-ponse time of the phase lockedloop is less than 10 ms. If thereare some PWM output pulses mis-sing, the oscillator frequency runstowards its maximum. If triggerpulses of the reference frequencyare missing, the oscillator frequencydecreases to the minimum set value.

The design works independent ofthe duty cycle of the PWM outputsignal, as long as its level is highenough to be realized as 'high' bythe CMOS-IC. The PLL frequency lock range andcapture range are determined byR24 and R52.


+1 C72

R37

R71

R39

R21

R33

R20

R20A

R38

Off=Standby

IC2

+4 C75

L72

R73

+7 C78

L73

R75

+0

3

C81

L74

R77

+-12 V0.2 A

5 V0.1 A

5 V2 A

15 V1 A

85 V0.28 A

195 V0.3 A

C84

L75

R79

IC6

C16

C27

C42

C17

R19

L71

D25

10

13

94046

D26

2

R24

R55 R58

R54

R57

R59

R50 R51 R56

C44

C43

C48

C45

C46

C47

R 52R53

PWMDriverOutput

10

7

VREF = 7.5 V

Q6

Q5

5 2

3

164

1

14

3

5 8

16 TDA16888TDA

16888

Figure 9 Application Circuitry

Figure 10 Synchronisation Circuitry of TDA 16888 with PLL

Documents

Power Semiconductorsuploads.cq-dx.ru/pdf/TDA/tda1688p.pdfThe Power Combi Control-lC TDA 16888 includes the PWM control for an SMPS and the control for the preconverter to improve the