ACIN

DRAIN

SOURCE

CONTROL

TOPSwitch

TOPSwitch

TOPSwitch SELECTION GUIDEOUTPUT POWER RANGE

FLYBACKORDERPART

NUMBER

PFC/BOOST

Three-terminal Off-line PWM Switch

TOP100-4

48 VDC

100/110 VVAC

N*

N*

N*

N*

N*

100/110VAC

July 2009

F7 /092

TOP100-4

PI-1746-011796

SHUTDOWN/ AUTO-RESTART

PWM COMPARATOR

CLOCK

SAW

OSCILLATOR

CONTROLLED TURN-ON

GATE DRIVER

INTERNAL SUPPLY

5.7 V 4.7 V

SOURCE

S

R

Q

Q

DMAX

-

+

CONTROL

-

+ 5.7 V

IFB

RE

ZC

VC

MINIMUM ON-TIME DELAY

+

- VILIMIT

LEADING EDGE

BLANKING

POWER-UP RESET

R

S

Q

Q

÷ 8

0

1

THERMAL SHUTDOWN

EXTERNALLY TRIGGERED SHUTDOWN

SHUNT REGULATOR/ ERROR AMPLIFIER

+

-

DRAIN

Figure 2. Functional Block Diagram.

Pin Functional Description

DRAIN Pin:Output MOSFET drain connection. Provides internal biascurrent during start-up operation via an internal switched high-voltage current source. Internal current sense point.

CONTROL Pin:Error amplifier and feedback current input pin for duty cyclecontrol. Internal shunt regulator connection to provide internalbias current during normal operation. Trigger input for latchingshutdown. It is also used as the supply bypass and auto-restart/compensation capacitor connection point.

SOURCE Pin:Output MOSFET source connection. Primary-side circuitcommon, power return, and reference point.

PI-1065A-110194

CONTROL

DRAIN

SOURCE (TAB)

TO-220/3 (YO3A)

Figure 3. Pin Configuration.

F7/ 09

TOP100-4

3

TOPSwitch Family Functional DescriptionTOPSwitch is a self biased and protectedlinear control current-to-duty cycleconverter with an open drain output.High efficiency is achieved through theuse of CMOS and integration of themaximum number of functions possible.CMOS significantly reduces biascurrents as compared to bipolar ordiscrete solutions. Integration eliminatesexternal power resistors used for currentsensing and/or supplying initial start-upbias current.

During normal operation, the internaloutput MOSFET duty cycle linearlydecreases with increasing CONTROLpin current as shown in Figure 4. Toimplement all the required control, bias,and protection functions, the DRAINand CONTROL pins each performseveral functions as described below.Refer to Figure 2 for a block diagramand Figure 6 for timing and voltagewaveforms of the TOPSwitch integratedcircuit.

Control Voltage SupplyCONTROL pin voltage V

C is the supply

or bias voltage for the controller anddriver circuitry. An external bypasscapacitor closely connected between theCONTROL and SOURCE pins isrequired to supply the gate drive current.The total amount of capacitanceconnected to this pin (C

T) also sets the

auto-restart timing as well as controlloop compensation. V

C is regulated in

either of two modes of operation.Hysteretic regulation is used for initialstart-up and overload operation. Shuntregulation is used to separate the dutycycle error signal from the control circuitsupply current. During start-up, V

C

current is supplied from a high-voltageswitched current source connectedinternally between the DRAIN andCONTROL pins. The current sourceprovides sufficient current to supply thecontrol circuitry as well as charge thetotal external capacitance (C

T).

PI-1691-112895

DMAX

DMIN

ICD1D

uty

Cyc

le (

%)

IC (mA)2.5 6.5 45

Slope = PWM Gain -16%/mA

IB

Auto-restart

Figure 4. Relationship of Duty Cycle to CONTROL Pin Current.

Figure 5. Start-up Waveforms for (a) Normal Operation and (b) Auto-restart.

DRAIN

0

VIN

VC

0

4.7 V5.7 V

8 Cycles

95%5%

Off

Switching Switching

Off

IC Charging CT

ICD1 Discharging CT

ICD2 Discharging CT

IC Charging CT

Off

PI-1124A-060694

DRAIN

0

VIN

VC0

4.7 V5.7 V

Off

Switching

(b)

(a)

CT is the total external capacitance connected to the CONTROL pin

F7/ 094

TOP100-4

The first time VC reaches the upper

threshold, the high-voltage currentsource is turned off and the PWMmodulator and output transistor areactivated, as shown in Figure 5(a).During normal operation (when theoutput voltage is regulated) feedbackcontrol current supplies the V

C supply

current. The shunt regulator keeps VC at

typically 5.7 V by shunting CONTROLpin feedback current exceeding therequired DC supply current through thePWM error signal sense resistor R

E. The

low dynamic impedance of this pin (ZC)

sets the gain of the error amplifier whenused in a primary feedbackconfiguration. The dynamic impedanceof the CONTROL pin together with theexternal resistance and capacitancedetermines the control loopcompensation of the power system.

If the CONTROL pin externalcapacitance (C

T) should discharge to the

lower threshold, then the outputMOSFET is turned off and the controlcircuit is placed in a low-current standbymode. The high-voltage current sourceis turned on and charges the externalcapacitance again. Charging current isshown with a negative polarity anddischarging current is shown with apositive polarity in Figure 6. Thehysteretic auto-restart comparator keepsV

C within a window of typically 4.7 to

5.7 V by turning the high-voltage currentsource on and off as shown in Figure5(b). The auto-restart circuit has a divide-by-8 counter which prevents the outputMOSFET from turning on again untileight discharge-charge cycles haveelapsed. The counter effectively limitsTOPSwitch power dissipation byreducing the auto-restart duty cycle totypically 5%. Auto-restart continues tocycle until output voltage regulation isagain achieved.

Bandgap ReferenceAll critical TOPSwitch internal voltagesare derived from a temperature-compensated bandgap reference. Thisreference is also used to generate atemperature-compensated current sourcewhich is trimmed to accurately set theoscillator frequency and MOSFET gatedrive current.

OscillatorThe internal oscillator linearly chargesand discharges the internal capacitancebetween two voltage levels to create asawtooth waveform for the pulse widthmodulator. The oscillator sets the pulsewidth modulator/current limit latch atthe beginning of each cycle. The nominalfrequency of 100 kHz was chosen tominimize EMI and maximize efficiencyin power supply applications. Trimmingof the current reference improvesoscillator frequency accuracy.

Pulse Width ModulatorThe pulse width modulator implementsa voltage-mode control loop by drivingthe output MOSFET with a duty cycleinversely proportional to the currentflowing into the CONTROL pin. Theerror signal across R

E is filtered by an

RC network with a typical cornerfrequency of 7 kHz to reduce the effectof switching noise. The filtered errorsignal is compared with the internaloscillator sawtooth waveform to generatethe duty cycle waveform. As the controlcurrent increases, the duty cycledecreases. A clock signal from theoscillator sets a latch which turns on theoutput MOSFET. The pulse widthmodulator resets the latch, turning offthe output MOSFET. The maximumduty cycle is set by the symmetry of theinternal oscillator. The modulator has aminimum ON-time to keep the currentconsumption of the TOPSwitchindependent of the error signal. Notethat a minimum current must be driveninto the CONTROL pin before the dutycycle begins to change.

Gate DriverThe gate driver is designed to turn theoutput MOSFET on at a controlled rateto minimize common-mode EMI. Thegate drive current is trimmed forimproved accuracy.

Error AmplifierThe shunt regulator can also perform thefunction of an error amplifier in primaryfeedback applications. The shuntregulator voltage is accurately derivedfrom the temperature compensatedbandgap reference. The gain of the erroramplifier is set by the CONTROL pindynamic impedance. The CONTROLpin clamps external circuit signals to theV

C voltage level. The CONTROL pin

current in excess of the supply current isseparated by the shunt regulator andflows through R

E as the error signal.

Cycle-By-Cycle Current LimitThe cycle by cycle peak drain currentlimit circuit uses the output MOSFETON-resistance as a sense resistor. Acurrent limit comparator compares theoutput MOSFET ON-state drain-sourcevoltage, V

DS(ON), with a threshold voltage.

High drain current causes VDS(ON)

toexceed the threshold voltage and turnsthe output MOSFET off until the start ofthe next clock cycle. The current limitcomparator threshold voltage istemperature compensated to minimizevariation of the effective peak currentlimit due to temperature related changesin output MOSFET R

DS(ON).

The leading edge blanking circuit inhibitsthe current limit comparator for a shorttime after the output MOSFET is turnedon. The leading edge blanking time hasbeen set so that current spikes caused byprimary-side capacitances andsecondary-side rectifier reverse recoverytime will not cause prematuretermination of the switching pulse.

TOPSwitch Family Functional Description (cont.)

F7/ 09

TOP100-4

5

PI-1119-110194

VIN

VOUT0

IOUT0

1 2 143

DRAIN

0

VIN

VC0

••• •••1 2 1 2 8 1

0IC ••• •••

1 2

8

8 1 2 8 1

VC(reset)

45 mA

Shutdown/Auto-restartTo minimize TOPSwitch powerdissipation, the shutdown/auto-restartcircuit turns the power supply on and offat a duty cycle of typically 5% if an outof regulation condition persists. Loss ofregulation interrupts the external currentinto the CONTROL pin. V

C regulation

changes from shunt mode to thehysteretic auto-restart mode describedabove. When the fault condition isremoved, the power supply outputbecomes regulated, V

C regulation returns

to shunt mode, and normal operation ofthe power supply resumes.

Latching ShutdownThe output overvoltage protection latchis activated by a high-current pulse intothe CONTROL pin. When set, the latchturns off the TOPSwitch output.Activating the power-up reset circuit by

removing and restoring input power, ormomentarily pulling the CONTROL pinbelow the power-up reset threshold resetsthe latch and allows TOPSwitch toresume normal power supply operation.V

C is regulated in hysteretic mode when

the power supply is latched off.

Overtemperature ProtectionTemperature protection is provided by aprecision analog circuit that turns theoutput MOSFET off when the junctiontemperature exceeds the thermalshutdown temperature (typically 145°C).Activating the power-up reset circuit byremoving and restoring input power ormomentarily pulling the CONTROL pinbelow the power-up reset threshold resetsthe latch and allows TOPSwitch toresume normal power supply operation.V

C is regulated in hysteretic mode when

the power supply is latched off.

High-voltage Bias Current SourceThis current source biases TOPSwitchfrom the DRAIN pin and charges theCONTROL pin external capacitance(C

T) during start-up or hysteretic

operation. Hysteretic operation occursduring auto-restart and latchedshutdown. The current source is switchedon and off with an effective duty cycle ofapproximately 35%. This duty cycle isdetermined by the ratio of CONTROLpin charge (I

C) and discharge currents

(ICD1

and ICD2

). This current source isturned off during normal operation whenthe output MOSFET is switching.

Figure 6. Typical Waveforms for (1) Normal Operation, (2) Auto-restart, (3) Latching Shutdown, and (4) Power Down Reset.

F7 /096

TOP100-4

current will flow into the control pin.Increasing control pin current decreasesthe duty cycle until a stable operatingpoint is reached. The output voltage isproportional to the bias voltage by theturns ratio of the output to bias windings.C5 is used to bypass the CONTROL pin.C5 also provides loop compensation forthe power supply by shunting ACcurrents around the CONTROL pindynamic impedance, and also determinesthe auto-restart frequency during start-up and auto-restart conditions. See DN-8 for more information regarding biassupplies.

General Circuit OperationPrimary Feedback RegulationThe circuit shown in Figure 7 is a simple5 V, 5 W bias supply using the TOP100.This flyback power supply employsprimary-side regulation from atransformer bias winding. This approachis best for low-cost applications requiringisolation and operation within a narrowrange of load variation. Line and loadregulation of ±5% or better can beachieved from 10% to 100% of ratedload.

Voltage feedback is obtained from thetransformer (T1) bias winding, whicheliminates the need for optocoupler andsecondary-referenced error amplifier.High-voltage DC is applied to theprimary winding of T1. The other sideof the transformer primary is driven by

Figure 7. Schematic Diagram of a Minimum Parts Count 5 V, 5 W Bias Supply Utilizing the TOP100.

the integrated high-voltage MOSFETtransistor within the TOP100 (U1). Thecircuit operates at a switching frequencyof 100 kHz, set by the internal oscillatorof the TOP100. The clamp circuitimplemented by VR1 and D1 limits theleading-edge voltage spike caused bytransformer leakage inductance to a safevalue. The 5 V power secondary windingis rectified and filtered by D2, C2, C3,and L1 to create the 5 V output voltage.

The output of the T1 bias winding isrectified and filtered by D3, R1, and C5.The voltage across C5 is regulated byU1, and is determined by the 5.7 Vinternal shunt regulator at theCONTROL pin of U1. When therectified bias voltage on C5 begins toexceed the shunt regulator voltage,

PI-1767-020296

5 V

RTN

C547 µF

U1TOP100YAI

D21N5822

D31N4148

L1(Bead)

C2330 µF25 V

C3150 µF25 V

T1

D1UF4004

DCINPUT

VR1P6KE91

R122 Ω

CIRCUIT PERFORMANCE:Load Regulation - ±4%

(10% to 100%)Line Regulation - ±1.5%

95 to 185 V DCRipple Voltage ±25 mVDRAIN

SOURCE

CONTROL

F7/ 09

TOP100-4

7

Simple Optocoupler FeedbackThe circuit shown in Figure 8 is a 7.5 V,15 W secondary regulated flyback powersupply using the TOP101 that willoperate from 85 to 132 VAC inputvoltage. Improved output voltageaccuracy and regulation over the circuitof Figure 7 is achieved by using anoptocoupler and secondary referencedZener diode. The general operation ofthe power stage of this circuit is the sameas that described for Figure 7.

The input voltage is rectified and filteredby BR1 and C1. L2, C6 and C7 reduceconducted emission currents. The biaswinding is rectified and filtered by D3and C4 to create a typical 11 V biasvoltage. Zener diode (VR2) voltagetogether with the forward voltage of theLED in the optocoupler U2 determinethe output voltage. R1, the optocoupler

current transfer ratio, and the TOPSwitchcontrol current to duty cycle transferfunction set the DC control loop gain.C5 together with the control pin dynamicimpedance and capacitor ESR establisha control loop pole-zero pair. C5 alsodetermines the auto-restart frequencyand filters internal gate drive switchingcurrents. R2 and VR2 provide minimumcurrent loading when output current islow. See DN-11 for more informationregarding low-cost, 15 W powersupplies.

Accurate Optocoupler FeedbackThe circuit shown in Figure 9 is a highlyaccurate, 15 V, 30 W secondary-regulated flyback power supply that willoperate from 85 to 132 VAC inputvoltage. A TL431 shunt regulatordirectly senses and accurately regulatesthe output voltage. The effective output

voltage can be fine tuned by adjustingthe resistor divider formed by R4 andR5. Other output voltages are possibleby adjusting the transformer turns ratiosas well as the divider ratio.

The general operation of the input andpower stages of this circuit are the sameas that described for Figures 7 and 8. R3and C5 tailor frequency response. TheTL431 (U3) regulates the output voltageby controlling optocoupler LED current(and TOPSwitch duty cycle) to maintainan average voltage of 2.5 V at the TL431input pin. Divider R4 and R5 determinethe actual output voltage. C9 rolls offthe high frequency gain of the TL431 forstable operation. R1 limits optocouplerLED current and determines highfrequency loop gain. For moreinformation, refer to application noteAN-14.

Figure 8. Schematic Diagram of a 15 W 100/110 VAC Input Power Supply Utilizing the TOP101 and Simple Optocoupler Feedback.

PI-1692-112895

7.5 V

RTN

C547µF10 V

D2UG8BT

D31N4148

R268 Ω

VR21N5234B

6.2 V

C3120 µF25 V

T1

D1UF4004

C2680 µF25 V

VR1P6KE91

CIRCUIT PERFORMANCE:Line Regulation - ±0.5%

(85-132 VAC)Load Regulation - ±1%

(10-100%)Ripple Voltage ±50 mV

Meets CISPR-22 Class B

BR1200 V

C127 µF200 V

R139 Ω

U2NEC2501

U1TOP101YAI

DRAIN

SOURCE

CONTROL

C40.1 µF

C71 nFY1

L13.3 µH

F13.15 A

J1

C60.1 µF

L220 mH

L

N

F7/ 098

TOP100-4

Figure 10. Schematic Diagram of a 60 W 110 VAC Input Boost Power Factor Correction Circuit Utilizing the TOP103.

Figure 9. Schematic Diagram of a 30 W 100/110 VAC Input Power Supply Utilizing the TOP102 and Accurate Optocoupler Feedback.

PI-1693-112895

15 V

RTN

BR1 200 V

C1 47 µF 200 V

C5 47 µF

C4 0.1 µF

U1 TOP102YAI

R3 6.2 Ω

R2 200 Ω 1/2 W

D2 MUR610CT

D3 1N4148

C2 1000 µF

35 V

T1

D1 BYV26B

C7 1 nF Y1

DRAIN

SOURCE

CONTROL

C3 120 µF 25 V

U2 NEC2501

U3 TL431

R4 49.9 kΩ

R5 10 kΩ

C9 0.1 µF

R1 510 Ω

VR1 P6KE91

L1 3.3 µH

F1 3.15 A

J1

C6 0.1 µF

L2 33 mH

L

N

CIRCUIT PERFORMANCE: Line Regulation - ±0.2%

(85-132 VAC) Load Regulation - ±0.2%

(10-100%) Ripple Voltage ±150 mV Meets CISPR-22 Class B

PI-1437-042595

PFC OUT

RTN

D1MUR440

BR1200 V

R1130 kΩ

R2200 Ω

R106.8 kΩ

R33 kΩ

VR1120 V

VR2120 V

D21N4936

C1220 nF200 V

C4100 µF

C24.7 µF

C3220 µF

L1380 µH

EMIFILTER

ACIN

U1TOP103YAI

DRAIN

SOURCE

CONTROLTYPICAL PERFORMANCE:Power Factor = 0.99

THD =5%

F7/ 09

TOP100-4

9

by the boost inductance and parasiticcapacitance. R1 generates a pre-compensation current proportional tothe instantaneous rectified AC inputvoltage which directly varies the dutycycle. C2 filters high frequencyswitching currents while having nofiltering effect on the line frequency pre-compensation current. R2 decouplesthe pre-compensation current from thelarge filter capacitor C3 to prevent anaveraging effect which would increasetotal harmonic distortion. C1 filtershigh frequency noise currents whichcould cause errors in the pre-compensation current.

General Circuit Operation (cont.)When power is first applied, C3 chargesto typically 5.7 volts before TOPSwitchstarts. C3 then provides TOPSwitchbias current until the output voltagebecomes regulated. When the outputvoltage becomes regulated, seriesconnected Zener diodes VR1 and VR2begin to conduct, drive current into theTOPSwitch control pin, and directlycontrol the duty cycle. C3 together withR3 perform low pass filtering on thefeedback signal to prevent output linefrequency ripple voltage from varyingthe duty cycle. For more information,refer to Design Note DN-7.

Keep the SOURCE pin length very short.Use a Kelvin connection to the SOURCEpin for the CONTROL pin bypasscapacitor. Use single point groundingtechniques at the SOURCE pin as shownin Figure 11.

Minimize peak voltage and ringing onthe DRAIN voltage at turn-off. Use aZener or TVS Zener diode to clamp theDRAIN voltage.

Do not plug the TOPSwitch device intoa “hot” IC socket during test. ExternalCONTROL pin capacitance may delivera surge current sufficient to trigger theshutdown latch which turns theTOPSwitch off.

Under some conditions, externallyprovided bias or supply current driveninto the CONTROL pin can hold theTOPSwitch in one of the 8 auto-restartcycles indefinitely and prevent starting.Shorting the CONTROL pin to theSOURCE pin will reset the TOPSwitch.To avoid this problem when doing benchevaluations, it is recommended that theV

C power supply be turned on before the

DRAIN voltage is applied.

CONTROL pin currents during auto-restart operation are much lower at lowinput voltages (< 20 V) which increasesthe auto-restart cycle period (see the I

C

vs. Drain Voltage Characteristic curve).

Short interruptions of AC power maycause TOPSwitch to enter the 8-countauto-restart cycle before starting again.This is because the input energy storagecapacitors are not completely dischargedand the CONTROL pin capacitance hasnot discharged below the pin internalpower-up reset voltage.

In some cases, minimum loading maybe necessary to keep a lightly loaded orunloaded output voltage within thedesired range due to the minimum ON-time.

For additional applications informationregarding the TOPSwitch family, referto AN-14.

Key Application Issues

Figure 11. Recommended TOPSwitch Layout.

PI-1240-110194

PC Board

Kelvin-connected bypass capacitor

and/or compensation network

Bias/Feedback Input

Bias/Feedback Return

High-voltage Return

Bend DRAIN pin forward if needed for creepage

DR

AIN

SO

UR

CE

CO

NT

RO

L

Do not bend SOURCE pin Keep it short

High Voltage Return

Bias/Feedback Return

Bypass Capacitor

DSC

TOP VIEW

Bias/Feedback Input

Boost PFC Pre-regulatorTOPSwitch can also be used as a fixedfrequency, discontinuous mode boostpre-regulator to improve Power Factorand reduce Total Harmonic Distortion(THD) for applications such as powersupplies and electronic ballasts. Thecircuit shown in Figure 10 operates from110 VAC and delivers 60 W at 265 VDCwith typical Power Factor over 0.99 andTHD of 5%. Bridge Rectifier BR1 fullwave rectifies the AC input voltage. L1,D1, C4, and TOPSwitch make up theboost power stage. D2 prevents reversecurrent through the TOPSwitch bodydiode due to ringing voltages generated

F7/ 0910

TOP100-4

IC = 4 mA, T

j = 25˚C

IC = I

CD1+ 0.5 mA, See Figure 12

IC = 10 mA, See Figure 12

IC = 4 mA, T

j = 25˚C

See Figure 4

See Note 1

See Figure 4

IC = 4 mA, Tj = 25˚C

See Figure 13

Tj = 25˚C

See Note 1

S1 open

Conditions(Unless Otherwise Specified)

Specification Symbol See Figure 14 Min Typ Max UnitsSOURCE = 0 V

Tj = -40 to 125°C

ABSOLUTE MAXIMUM RATINGS(1)

DRAIN Voltage ............................................ -0.3 to 350 VCONTROL Voltage ..................................... - 0.3 V to 9 VStorage Temperature ...................................... -65 to 125°COperating Junction Temperature(2) ................. -40 to 150°CLead Temperature(3) ................................................. 260°C

Thermal Impedance (θJA

) ...................................... 70°C/WThermal Impedance (θ

JC)(4) .................................... 2 °C/W

1. Unless noted, all voltages referenced to SOURCE,T

A = 25°C.

2. Normally limited by internal circuitry.3. 1/16" from case for 5 seconds.4. Measured at tab closest to plastic interface.

90 100 110

64 67 70

1.0 1.8 3.0

-11 -16 -21

-0.05

1.5 2.5 4

10 15 22

0.18

-2.4 -1.9 -1.2

-2 -1.5 -0.8

0.4

5.7

fOSC

DCMAX

DCMIN

IB

ZC

IC

CONTROL FUNCTIONS

OutputFrequency

MaximumDuty Cycle

MinimumDuty Cycle

PWMGain

PWM GainTemperature Drift

ExternalBias Current

DynamicImpedance

Dynamic ImpedanceTemperature Drift

CONTROL PinCharging Current

Charging CurrentTemperature Drift

Auto-restartThreshold Voltage

kHz

%

%

%/mA

%/mA/˚C

mA

Ω

%/˚C

mA

%/˚C

V

SHUTDOWN/AUTO-RESTART

VC

= 0 V

VC

= 5 V

VC(AR)

F7/ 09

TOP100-4

11

4.7

0.6 1.0

5 8

1.2

0.88 1.25

1.50 2.15

2.20 3.10

2.85 4.00

3.30 4.60

150

100

125 145

25 45 75

2.0 3.3 4.2

S1 open

S1 open

S1 open

S1 open

TOP100

di/dt = 160 mA/µs, Tj = 25˚C

TOP101

di/dt = 280 mA/µs, Tj = 25˚C

TOP102

di/dt = 400 mA/µs, Tj = 25˚C

TOP103

di/dt = 520 mA/µs, Tj = 25˚C

TOP104

di/dt = 600 mA/µs, Tj = 25˚C

IC = 4 mA

IC = 4 mA

IC = 4 mA

See Figure 13

S2 open

ILIMIT

tLEB

tILD

ISD

VC(RESET)

V

V

%

Hz

A

ns

ns

°C

mA

V

SHUTDOWN/AUTO-RESTART (cont.)

UV LockoutThreshold Voltage

Auto-restartHysteresis Voltage

Auto-restartDuty Cycle

Auto-restartFrequency

Self-protectionCurrent Limit

Leading EdgeBlanking Time

Current LimitDelay

Thermal ShutdownTemperature

Latched ShutdownTrigger Current

Power-up ResetThreshold Voltage

CIRCUIT PROTECTION

Conditions(Unless Otherwise Specified)

Specification Symbol See Figure 14 Min Typ Max UnitsSOURCE = 0 VT

j = -40 to 125°C

F7/ 0912

TOP100-4

RDS(ON)

IDSS

BVDSS

tr

tf

VC(SHUNT)

ICD1

ICD2

TOP100 Tj = 25°C

ID = 110 mA T

j = 100°C

TOP101 Tj = 25°C

ID = 190 mA T

j = 100°C

TOP102 Tj = 25°C

ID = 270 mA T

j = 100°C

TOP103 Tj = 25°C

ID = 350 mA T

j = 100°C

TOP104 Tj = 25°C

ID = 400 mA T

j = 100°C

Device in Latched Shutdown

IC = 4 mA, V

DS = 280 V, T

A = 125°C

Device in Latched Shutdown

IC = 4 mA, I

D = 500 µA, T

A = 25°C

Measured With

Figure 8 Schematic

Measured With

Figure 8 Schematic

See Note 2

IC = 4 mA

Output MOSFET Enabled

Output MOSFET Disabled

ON-StateResistance

OFF-StateCurrent

BreakdownVoltage

RiseTime

FallTime

DRAIN SupplyVoltage

Shunt RegulatorVoltage

Shunt RegulatorTemperature Drift

CONTROL Supply/Discharge Current

Ω

µA

V

ns

ns

V

V

ppm/˚C

mA

OUTPUT

SUPPLY

Conditions(Unless Otherwise Specified)

Specification Symbol See Figure 14 Min Typ Max UnitsSOURCE = 0 V

Tj = -40 to 125°C

6.4 7.5

10.5 12.4

3.6 4.3

6.0 7.1

2.6 3.0

4.2 5.0

2.0 2.4

3.3 3.9

1.7 2.0

2.8 3.3

500

350

100

50

36

5.5 5.8 6.1

±50

0.6 1.2 1.6

0.5 0.8 1.1

F7/ 09

TOP100-4

13

Conditions(Unless Otherwise Specified)

Specification Symbol See Figure 14 Min Typ Max UnitsVS2 = 16 V R1 = 0 Ω

SOURCE = 0 VT

j = -40 to 125°C

LOW INPUT VOLTAGE OPERATION (See Note 3)

16

-2.3 -1.65 -1

-1.2 -0.64 -0.28

4 8

0.85

Volts

mA

mA

%

Hz

DRAIN SupplyVoltage

CONTROL PinCharging Current

Auto-restartDuty Cycle

Auto-restartFrequency

NOTES:1. For specifications with negative values, a negative temperature coefficient corresponds to an increase in

magnitude with increasing temperature, and a positive temperature coefficient corresponds to a decrease inmagnitude with increasing temperature.

2. It is possible to start up and operate TOPSwitch at DRAIN voltages well below 36 V. Refer to the "Low InputVoltage" Specification section for details.

3. This section specifies only parameters affected by low input voltage operation (Drain Voltages less than 36 V). Allother parameters remain unchanged.

4. For low input voltage applications, the primary peak current could be set to a lower value than the current limit toincrease efficiency. Refer to the Output Characteristics graph (Drain Current vs. Drain Voltage). The voltageacross the transformer primary during the ON time is the difference between the input voltage and the drainvoltage (V

DS(ON)).

For example, if the input voltage is 16 VDC and a TOP104 (3.3A minimum current limit) is used at a primary peakcurrent of 1A. Then the (V

DS(ON)) is 3 V at 100°C and the energizing voltage across the transformer primary is

13 V.

VC= 0 V

VC= 5 V

See Note 4

Tj = 25°C

S1/Open

S1/Open

F7/ 0914

TOP100-4

PI-1215-091794

DRAIN VOLTAGE

HV

0 V

90%

10%

90%

t2

t1

DC = t1

t2

Figure 12. TOPSwitch Duty Cycle Measurement.

PI-1905-061396

C10.1 µF

C247 µF

VS10-50 V

VS240 VTOPSwitch

R1470 Ω5 W S2

S1

R2

470 Ω

DRAIN

SOURCE

CONTROL

NOTE: This test circuit is not applicable for current limit or output characteristic measurements.

Figure 14. TOPSwitch General Test Circuit.

120

100

80

40

20

60

00 2 4 6 8 10

CONTROL Pin Voltage (V)

CO

NT

RO

L P

in C

urr

ent

(mA

)

TYPICAL CONTROL PIN I-V CHARACTERISTIC

PI-

1216

-091

794

Latched Shutdown Trigger Current (45 mA)

1 Slope

Dynamic Impedance

=

Figure 13. TOPSwitch CONTROL Pin I-V Characteristic.

F7/ 09

TOP100-4

15

1.1

1.0

0.9-50 -25 0 25 50 75 100 125 150

Junction Temperature (°C)

Bre

akd

ow

n V

olt

age

(V)

(No

rmal

ized

to

25°

C)

BREAKDOWN vs. TEMPERATURE

PI-

176B

-051

391 1.2

1.0

0.8

0.6

0.4

0.2

0-50 -25 0 25 50 75 100 125 150

Junction Temperature (°C)

FREQUENCY vs. TEMPERATURE

PI-

1123

A-0

6079

4

Ou

tpu

t F

req

uen

cy

(No

rmal

ized

to

25°

C)

1.2

1.0

0.8

0.6

0.4

0.2

0-50 -25 0 25 50 75 100 125 150

Junction Temperature (°C)

CURRENT LIMIT vs. TEMPERATURE

PI-

1125

-041

494

Cu

rren

t L

imit

(N

orm

aliz

ed t

o 2

5°C

)

2

1.2

1.6

00 20 40 60 80 100

Drain Voltage (V)

CO

NT

RO

L P

in

Ch

arg

ing

Cu

rren

t (m

A)

IC vs. DRAIN VOLTAGEP

I-11

45-1

0319

4

0.4

0.8

VC = 5 V

The control pin voltage will be oscillatingat a low frequency from 4.7 to 5.7 V andthe DRAIN is turned on every eighthcycle of the CONTROL pin oscillation.If the CONTROL pin power supply isturned on while in this auto-restart mode,there is only a 12.5% chance that thecontrol pin oscillation will be in thecorrect state (DRAIN active state) so

The following precautions should befollowed when testing TOPSwitch byitself outside of a power supply. Theschematic shown in Figure 14 issuggested for laboratory testing ofTOPSwitch.

When the DRAIN supply is turned on,the part will be in the auto-restart mode.

BENCH TEST PRECAUTIONS FOR EVALUATION OF ELECTRICAL CHARACTERISTICS

that the continuous DRAIN voltagewaveform may be observed. It isrecommended that the V

C power supply

be turned on first and the DRAIN powersupply second if continuous drain voltagewaveforms are to be observed. The12.5% chance of being in the correctstate is due to the 8:1 counter.

Typical Performance Characteristics

F7/ 0916

TOP100-4

Typical Performance Characteristics (cont.)

5

3

4

00 4 6 82 10

Dra

in C

urr

ent

(A)

OUTPUT CHARACTERISTICS

PI-

1747

-011

796

1

2

Drain Voltage (V)

TCASE = 25°CTCASE = 100°C

Scaling Factors:

TOP104 1.00TOP103 0.87TOP102 0.67TOP101 0.47TOP100 0.27

1000

100 24016080 320

DRAIN Voltage (V)

DR

AIN

Cap

acit

ance

(p

F)

COSS vs. DRAIN VOLTAGE

100

PI-

1439

-042

595

Scaling Factors: TOP104 1.00 TOP103 0.87 TOP102 0.67 TOP101 0.47 TOP100 0.27

100

50

00 16080 240 320

DRAIN Voltage (V)

Po

wer

(m

W)

DRAIN CAPACITANCE POWER

PI-

1694

-112

895

Scaling Factors:TOP104 1.00TOP103 0.87TOP102 0.67TOP101 0.47TOP100 0.27

F7/ 09

TOP100-4

17

B K

F

G

C

J

L

M

E

A

D

DIM

A

B

C

D

E

F

G

H

J

K

L

M

N

O

P

PI-1848-050696

inches

.460-.480

.400-.415

.236-.260

.240 - REF.

.520-.560

.028-.038

.045-.055

.090-.110

.165-.185

.045-.055

.095-.115

.015-.020

.705-.715

.146-.156

.103-.113

mm

11.68-12.19

10.16-10.54

5.99-6.60

6.10 - REF.

13.21-14.22

.71-.97

1.14-1.40

2.29-2.79

4.19-4.70

1.14-1.40

2.41-2.92

.38-.51

17.91-18.16

3.71-3.96

2.62-2.87

H

* LEADS AND TAB ARE SOLDER PLATED

N

O

PNotes: 1. Package dimensions conform to JEDEC specification TO-220 AB for standard flange mounted, peripheral lead package; .100 inch lead spacing (Plastic) 3 leads (issue J, March 1987) 2. Controlling dimensions are inches. 3. Pin numbers start with Pin 1, and continue from left to right when viewed from the top. 4. Dimensions shown do not include mold flash or other protrusions. Mold flash or protrusions shall not exceed .006 (.15 mm) on any side. 5. Position of terminals to be measured at a position .25 (6.35 mm) from the body. 6. All terminals are solder plated.

Y03A Plastic TO-220/3

F7/ 0918

TOP100-4

JAPANPower Integrations, K.K.Keihin-Tatemono 1st Bldg.12-20 Shin-Yokohoma 2-Chome, Kohoku-kuYokohama-shi, Kanagawa 222 JapanPhone: 81•(0)•45•471•1021Fax: 81•(0)•45•471•3717

ASIA & OCEANIAFor Your Nearest Sales/Rep OfficePlease Contact Customer ServicePhone: 408•523•9265Fax: 408•523•9365

WORLD HEADQUARTERSPower Integrations, Inc.477 N. Mathilda AvenueSunnyvale, CA 94086USAMain: 408•523•9200Customer Service:Phone: 408•523•9265Fax: 408•523•9365

AMERICASFor Your Nearest Sales/Rep OfficePlease Contact Customer ServicePhone: 408•523•9265Fax: 408•523•9365

Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability.Power Integrations does not assume any liability arising from the use of any device or circuit described herein, nor does itconvey any license under its patent rights or the rights of others.

PI Logo and TOPSwitch are registered trademarks of Power Integrations, Inc.©Copyright 1994, Power Integrations, Inc. 477 N. Mathilda Avenue, Sunnyvale, CA 94086

APPLICATIONS HOTLINEWorld Wide 408•523•9260

APPLICATIONS FAXAmericas 408•523•9361Europe/Africa44•(0)•1753•622•209Japan 81•(0)•45•471•3717Asia/Oceania 408•523•9364

EUROPE & AFRICAPower Integrations (Europe) Ltd.Mountbatten HouseFairacresWindsor SL4 4LEUnited KingdomPhone: 44•(0)•1753•622•208Fax: 44•(0)•1753•622•209