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ISTANBUL TECHNICAL UNIVERSITYDEPARTMENT OF ELECTRICAL ENGINEERING
POWER ELECTRONIC CIRCUITSFALL 2008, CRN: 11473
ASST. PROF. DENİZ YILDIRIM
PROJECT REPORT
MINIPROJECT IV
DC/AC INVERTER
GROUP MEMBERS
040060450040050442040050437
BİROL ÇAPAELİF KÖKSALBURAK BEŞER
SUBMISSION DATE: JANUARY 21, 2009
2
1. PURPOSE
The purpose of the project is to design and construct an inverter that produces
220V, 50Hz sinusoidal AC voltage from a DC power supply.
The project contains three main steps, design an inverter, simulating the
circuit, and construct the circuit. After construction, the circuit will be tested to
see if it obeys simulation results.
In conclusion, 220V 50Hz sinusoidal output should be obtain.
2. DESIGN
Figure 2.1 - AC inverter circuit
A typical circuit to receive a sinusoidal signal at the output is shown in Figure
2.1. To achieve this purpose the most important part is to design a PWM inverter.
This PWM signal will be applied to the MOSFET H bridge through the gate drive
IC. MOSFETs will be triggered according to the following equation:
3
For obtaining necessary PWM signal, sinusoidal and triangular signal must be
produced and compared. Triangular wave in the carrier wave and the sinusoidal
wave is the main wave. There are many different methods for obtaining those
signals, but XR2206 IC is chosen.
Figure 2.2 - XR2206 waveform generator
Figure 2.3 - Timing resistor vs. frequency
4
It is possible getting desired signals at desired frequencies by choosing
resistors and capacitors. R resistor and C capacitor, in Figure 2.2, are chosen for
frequency range. Figure 2.3 shows the resistor values for particular frequency
range. Equation 1 is the formula of frequency.
f= 1/ R*C (1)
To obtain the PWM signal, frequencies of the sinus and triangle waves are
chosen carefully. The frequency of triangular wave must be larger than the
sinusoidal. Therefore frequency of sinusoidal wave is 50 Hz, triangular one is
20KHz. With help of the Figure 2.3, resistors for 50Hz as 100K and for 20KHz as
10 K are suitable. From the equation (1) capacitors are calculated 200nF for sinus,
5nF for triangular.
For sinusoidal wave, S1 switch must be off.
For obtaining a modulated wave as PWM, a comparator in used. In Figure 2.4
LM311 can be seen basically. When the input 3 larger than the input 2 the output
is +Vcc, on the other condition the output is –Vcc. the modulated signal is as
Figure 2.5.
Figure 2.4 - LM311
HC7804 “NOT gate” is placed at the output of the LM311, in order to obtain
necessary signals for HIP4082. LM805 regulator is used to get the supply voltage
for HC7804 IC.
5
Figure 2.5 - Modulated signal
Modulated signal which is the output of the comparator and the inverse of it is
applied the HIP4082 IC. The purpose of this IC is to trigger MOSFETs properly.
Typical application schema for HIP4082 is shown in Figure 2.6.
Figure 2.6 - HIP4082 application
6
Diodes between 12 and 9 pins and 12 and 1 pins and capacitors are for
bootstrap, which are needed for full bridge drive.
For trigger MOSFETs correctly 10Ω resistors are placed.
3. SIMULATION
The simulations are done with PSIM. As the sine and triangle waves are
generated from function generator XR2206 IC, these signals are simulated as sine
and triangle wave sources. In Figure 3.1 the simulation circuit is seen with voltage
and current probes attached to it.
Figure 3.1 – The simulation circuit
LM311 comparator is simulated as an ideal op-amp with ±5V supply voltage.
The transformer has a ratio 24:220. Rload is identified as a 484Ω resistance as it is
a 100W 220V incandescent lamp in real construction. Simulation results are given
below due to full load and no load respectively.
7
Figure 3.2 – Waveforms of Vsine, Vtri and Vcontrol at full load
8
Figure 3.3 – Waveforms of Vac, Iac and Vpwm at full load
When no load is attached to circuit the simulation results are acquired as
below. However simulations cannot be run with zero load, Rload is selected
0,00001Ω which can be considered as zero.
Figure 3.4 – Waveforms of Vsine, Vtri and Vcontrol at no load
9
Figure 3.5 – Waveforms of Vac, Iac and Vpwm at no load
As it can be seen from Figure 3.2 through Figure 3.5, only the value of Iac is
related with the value of Rload. Besides that the PWM signal’s waveform is
consistent with theoretical expectations.
4. CONSTRUCTION AND TESTING
Tests of the circuit are executed in parts. Firstly, the sine and triangular waves
are tested which can be seen in Figure 4.1 and Figure 4.2.
10
Figure 4.1 – The sinusoidal waveform
Figure 4.2 – The triangular waveform
After that the comparator’s output signal waveform is observed in
oscilloscope. This waveform can be seen in Figure 4.3 and it is also well-matched
with theoretical calculations.
11
Figure 4.3 – The waveform at the output of LM311
The PWM signal that is produced from voltage comparator LM311 and the
inverted PWM signal that is produced from hex inverter 74HC04 are applied to
the inputs of HIP4082. These waveforms can be seen in Figure 4.4
simultaneously.
Figure 4.4 – Inverted and non-inverted PWM waveform
12
In Figure 4.5 the waveforms of the outputs of HIP4082, PWM signal and
inverted PWM signal that change between 0-12V are given. However, as no load
is attached to the circuit, a 12V DC voltage is seen at the other 2 outputs as it is
given in Figure 4.6.
Figure 4.5 – Waveform at the low-side MOSFET
Figure 4.5 – Waveform at the high-side MOSFET
13
At the testing part a 100W 220V incandescent lamp is connected as a load to
the secondary side of a 22:220 transformer. In figure 4.6 the waveform of the
Vload that is not filtered can be seen.
Figure 4.6 – Waveform of Vload with no capacitor
After connecting a 3.33nF filter capacitor, the waveform of Vload is changed
and approximated to a sinusoidal wave that can be seen in Figure 4.7.
Figure 4.6 – Waveform of Vload with 3.33nF capacitor
14
In Figure 4.7 the waveform of Vload is seen when higher capacitor is used for
filtering. A 150nF capacitor is used for this purpose.
Figure 4.7 – Waveform of Vload with 150nF capacitor
At the secondary side of the transformer the rms value of the voltage is
127.8V and the current that flows through the load is 0.12A as it can be seen in
Figure 4.8.
Figure 4.8 – RMS value of Vlaod and value of Iload
15
Figure 4.9 shows all the testing setup.
Figure 4.9 – The complete testing setup
5. CONCLUSION
In conclusion, the sinusoidal wave is produced from a DC voltage by using a
DC/AC inverter circuit. Adding a capacitance filter the output voltage of the load
approximate to a sinusoidal waveform. In addition designing a L-C low pass filter
aid to obtain a smooth sinusoidal waveform.
6. EQUIPMENT
2*XR2206 Function Generator
LM311 Voltage Comparator
74HC04 Hex Inverter
HIP4082 MOSFET Driver
LM7805 Voltage Regulator
4*IRF540 N-Type MOSFET
2*UF4002 Ultrafast Diode
4*1N5245 Ultrafast Zener Diode
16
2*0.01uF, 2*2.2uF, 3*1uF, 1.5uF, 200nF, 5nF, 0.33uF 2*10uF (electrolyte
type), 2*1uF (electrolyte type) Capacitors
6*1KΩ, 4*5.1KΩ, 4*15Ω, 2*10KΩ, 2*100KΩ, 220Ω Resistors
100KΩ Potentiometer, 10KΩ Potentiometer
7. REFERENCES
1. Exar Corp. (1997). XR-2206 Monolithic Function Generator. Retrieved
January 20, 2009, from http://www.datasheetcatalog.com/
2. Fairchild Semiconductor Corporation (2001). MC78XX/LM78XX/MC78XXA
3-Terminal 1A positive voltage regulator. Retrieved January 20, 2009,
from http://www.datasheetcatalog.com/
3. General Semiconductor (1998). UF4001 THRU UF4007 Ultrafast effıcıent
plastıc rectifier. Retrieved January 20, 2009, from
http://www.datasheetcatalog.com/
4. Intersil (2004). HIP4082. Retrieved January 20, 2009, from
http://www.datasheetcatalog.com/
5. Philips Semiconductors (1999). IRF540, IRF540S. Retrieved January 20,
2009, from http://www.datasheetcatalog.com/
6. Semelab Plc. (1999). 1N5221B-LCC3 TO 1N5281B-LCC3. Retrieved
January 20, 2009, from http://www.datasheetcatalog.com/
7. ST Microelectronics (2002). LM111 - LM211 - LM311 Voltage comparators.
Retrieved January 20, 2009, from http://www.datasheetcatalog.com/
17
8. Texas Instruments Incorporated (2004). CD54HC04, CD74HC04,
CD54HCT04, CD74HCT04 High-speed CMOS logic hex inverter.
Retrieved January 20, 2009, from http://www.datasheetcatalog.com/
8. APPENDIX
Appendix 1 – XR-2206 datasheet
Appendix 2 – UF4007 datasheet
Appendix 3 – HIP4082 datasheet
Appendix 4 – IRF540 datasheet
Appendix 5 – 1N5245 datasheet
Appendix 6 – LM311 datasheet
Appendix 7 – CD74HC05 datasheet
Appendix 8 – LM7805 datasheet
XR-2206...the analog plus companyTM
MonolithicFunction Generator
Rev. 1.031972
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 (510) 668-7000 (510) 668-7017
1
June 1997-3
FEATURES
Low-Sine Wave Distortion, 0.5%, Typical
Excellent Temperature Stability, 20ppm/°C, Typ.
Wide Sweep Range, 2000:1, Typical
Low-Supply Sensitivity, 0.01%V, Typ.
Linear Amplitude Modulation
TTL Compatible FSK Controls
Wide Supply Range, 10V to 26V
Adjustable Duty Cycle, 1% TO 99%
APPLICATIONS
Waveform Generation
Sweep Generation
AM/FM Generation
V/F Conversion
FSK Generation
Phase-Locked Loops (VCO)
GENERAL DESCRIPTION
The XR-2206 is a monolithic function generatorintegrated circuit capable of producing high quality sine,square, triangle, ramp, and pulse waveforms ofhigh-stability and accuracy. The output waveforms can beboth amplitude and frequency modulated by an externalvoltage. Frequency of operation can be selectedexternally over a range of 0.01Hz to more than 1MHz.
The circuit is ideally suited for communications,instrumentation, and function generator applicationsrequiring sinusoidal tone, AM, FM, or FSK generation. Ithas a typical drift specification of 20ppm/°C. The oscillatorfrequency can be linearly swept over a 2000:1 frequencyrange with an external control voltage, while maintaininglow distortion.
ORDERING INFORMATION
Part No. PackageOperating
Temperature Range
XR-2206M 16 Lead 300 Mil CDIP -55°C to +125°C
XR-2206P 16 Lead 300 Mil PDIP –40°C to +85°C
XR-2206CP 16 Lead 300 Mil PDIP 0°C to +70°C
XR-2206D 16 Lead 300 Mil JEDEC SOIC 0°C to +70°C
XR-2206
2
Rev. 1.03
11 SYNCO
VCO
4
VCC
12
GND
10
BIAS
TimingCapacitor
5TC1
6TC2
TimingResistors
7TR1
8TR2
9FSKI
1AMSI
CurrentSwitches
MultiplierAnd SineShaper
2 STO
3 MO
13WAVEA1
14WAVEA2
15SYMA1
16SYMA2
Figure 1. XR-2206 Block Diagram
+1
XR-2206
3
Rev. 1.03
16 Lead PDIP, CDIP (0.300”)
SYMA2SYMA1WAVEA2WAVEA1GNDSYNCOBIASFSKI
AMSISTOMOVCCTC1TC2TR1TR2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
AMSISTOMOVCCTC1TC2TR1TR2
SYMA2SYMA1WAVEA2WAVEA1GNDSYNCOBIASFSKI
16 Lead SOIC (Jedec, 0.300”)
161
98
2
3
4
5
6
7
15
14
13
12
11
10
PIN DESCRIPTION
Pin # Symbol Type Description
1 AMSI I Amplitude Modulating Signal Input.
2 STO O Sine or Triangle Wave Output.
3 MO O Multiplier Output.
4 VCC Positive Power Supply.
5 TC1 I Timing Capacitor Input.
6 TC2 I Timing Capacitor Input.
7 TR1 O Timing Resistor 1 Output.
8 TR2 O Timing Resistor 2 Output.
9 FSKI I Frequency Shift Keying Input.
10 BIAS O Internal Voltage Reference.
11 SYNCO O Sync Output. This output is a open collector and needs a pull up resistor to VCC.
12 GND Ground pin.
13 WAVEA1 I Wave Form Adjust Input 1.
14 WAVEA2 I Wave Form Adjust Input 2.
15 SYMA1 I Wave Symetry Adjust 1.
16 SYMA2 I Wave Symetry Adjust 2.
XR-2206
4
Rev. 1.03
DC ELECTRICAL CHARACTERISTICSTest Conditions: Test Circuit of Figure 2 Vcc = 12V, TA = 25°C, C = 0.01F, R1 = 100k, R2 = 10k, R3 = 25kUnless Otherwise Specified. S1 open for triangle, closed for sine wave.
XR-2206M/P XR-2206CP/D
Parameters Min. Typ. Max. Min. Typ. Max. Units Conditions
General Characteristics
Single Supply Voltage 10 26 10 26 V
Split-Supply Voltage +5 +13 +5 +13 V
Supply Current 12 17 14 20 mA R1 10k
Oscillator Section
Max. Operating Frequency 0.5 1 0.5 1 MHz C = 1000pF, R1 = 1k
Lowest Practical Frequency 0.01 0.01 Hz C = 50F, R1 = 2M
Frequency Accuracy +1 +4 +2 % of fo fo = 1/R1C
Temperature StabilityFrequency
+10 +50 +20 ppm/°C 0°C TA 70°CR1 = R2 = 20k
Sine Wave Amplitude Stability2 4800 4800 ppm/°C
Supply Sensitivity 0.01 0.1 0.01 %/V VLOW = 10V, VHIGH = 20V,R1 = R2 = 20k
Sweep Range 1000:1 2000:1 2000:1 fH = fL fH @ R1 = 1kfL @ R1 = 2M
Sweep Linearity
10:1 Sweep 2 2 % fL = 1kHz, fH = 10kHz
1000:1 Sweep 8 8 % fL = 100Hz, fH = 100kHz
FM Distortion 0.1 0.1 % +10% Deviation
Recommended Timing Components
Timing Capacitor: C 0.001 100 0.001 100 F Figure 5
Timing Resistors: R1 & R2 1 2000 1 2000 k
Triangle Sine Wave Output 1 Figure 3
Triangle Amplitude 160 160 mV/k Figure 2, S1 Open
Sine Wave Amplitude 40 60 80 60 mV/k Figure 2, S1 Closed
Max. Output Swing 6 6 Vp-p
Output Impedance 600 600
Triangle Linearity 1 1 %
Amplitude Stability 0.5 0.5 dB For 1000:1 Sweep
Sine Wave Distortion
Without Adjustment 2.5 2.5 % R1 = 30k
With Adjustment 0.4 1.0 0.5 1.5 % See Figure 7 and Figure 8
Notes1 Output amplitude is directly proportional to the resistance, R3, on Pin 3. See Figure 3.2 For maximum amplitude stability, R3 should be a positive temperature coefficient resistor.Bold face parameters are covered by production test and guaranteed over operating temperature range.
XR-2206
5
Rev. 1.03
DC ELECTRICAL CHARACTERISTICS (CONT’D)
XR-2206M/P XR-2206CP/D
Parameters Min. Typ. Max. Min. Typ. Max. Units Conditions
Amplitude Modulation
Input Impedance 50 100 50 100 k
Modulation Range 100 100 %
Carrier Suppression 55 55 dB
Linearity 2 2 % For 95% modulation
Square-Wave Output
Amplitude 12 12 Vp-p Measured at Pin 11.
Rise Time 250 250 ns CL = 10pF
Fall Time 50 50 ns CL = 10pF
Saturation Voltage 0.2 0.4 0.2 0.6 V IL = 2mA
Leakage Current 0.1 20 0.1 100 A VCC = 26V
FSK Keying Level (Pin 9) 0.8 1.4 2.4 0.8 1.4 2.4 V See section on circuit controls
Reference Bypass Voltage 2.9 3.1 3.3 2.5 3 3.5 V Measured at Pin 10.
Notes1 Output amplitude is directly proportional to the resistance, R3, on Pin 3. See Figure 3.2 For maximum amplitude stability, R3 should be a positive temperature coefficient resistor.Bold face parameters are covered by production test and guaranteed over operating temperature range.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS
Power Supply 26V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Dissipation 750mW. . . . . . . . . . . . . . . . . . . . . . . Derate Above 25°C 5mW/°C. . . . . . . . . . . . . . . . . . . . . .
Total Timing Current 6mA. . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature -65°C to +150°C. . . . . . . . . . . .
SYSTEM DESCRIPTION
The XR-2206 is comprised of four functional blocks; avoltage-controlled oscillator (VCO), an analog multiplierand sine-shaper; a unity gain buffer amplifier; and a set ofcurrent switches.
The VCO produces an output frequency proportional toan input current, which is set by a resistor from the timing
terminals to ground. With two timing pins, two discreteoutput frequencies can be independently produced forFSK generation applications by using the FSK inputcontrol pin. This input controls the current switches whichselect one of the timing resistor currents, and routes it tothe VCO.
XR-2206
6
Rev. 1.03
5
Figure 2. Basic Test Circuit
Symmetry Adjust
25K
1
6
7
8
9
11
3
2
13
1415
16
4
10 12 XR-2206
1F
VCC
C
R1
R2
FSK Input
S1 THD Adjust
500Triangle OrSine WaveOutputSquare WaveOutput
VCC
10K
1F
R325K
5.1K 5.1KVCC
1F
CurrentSwitches
Mult.AndSine
Shaper
+1
VCO
+
S1 = Open For Triangle
= Closed For Sinewave
Figure 3. Output Amplitudeas a Function of the Resistor,
R3, at Pin 3
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Triangle
Sinewave
26
22
18
14
108 12 16 20 24 28
70°C Max.PackageDissipation
1K
2K
10K
30K
Figure 4. Supply Current vsSupply Voltage, Timing, R
0 20 40 60 80 100
1
2
3
4
5
6
Pea
k O
utpu
t Vol
tage
(V
olts
)
R3 in (K
I CC
(mA
)
VCC (V)
XR-2206
7
Rev. 1.03
ÁÁÁÁÁÁÁÁÁÁ
MINIMUM TIMING R
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Figure 5. R versus Oscillation Frequency.
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
4V 4V
10M
1M
100K
10K
1K
10-2 10 102
ÁÁÁÁÁÁÁÁÁÁÁÁ
MAXIMUM TIMING R
VCC / 2
DC Voltage At Pin 1Frequency (Hz)
Tim
ing
Res
isto
r
0
0.5
1.0
Nor
mal
Out
put A
mpl
itude
Figure 6. Normalized Output Amplitude versus DC Bias at AM Input (Pin 1)
Figure 7. Trimmed Distortion versusTiming Resistor.
Dis
tort
ion
(%)
Timing R K(
0
1
2
3
4
5
1.0 10 100 103
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
C = 0.01FTrimmed For MinimumDistortion At 30 K
Figure 8. Sine Wave Distortion versus Operating Frequency with Timing Capacitors Varied.
10 100 1K 10K 100K 1M
0
1
2
3
4
5
Dis
tort
ion
(%)
Frequency (Hz)
ÁÁÁR=3K
ÁÁÁÁÁÁÁÁ
RL=10K
ÁÁÁÁÁÁÁÁÁÁ
NORMAL RANGE
ÁÁÁÁÁÁÁÁÁÁ
TYPICAL VALUE
=0.5VRMS Pin 2VOUT
()
104 106
XR-2206
8
Rev. 1.03
Figure 9. Frequency Drift versusTemperature.
3
2
1
0
-1
-2
-3-50 -25 0 25 50 75 125
C=0.01F
R=1M
R=2K
R=10KR=200K
R=1M
R=1K
R=10KR=2K
R=1K
Ambient Temperature (C °)
Figure 10. Circuit Connection for Frequency Sweep.
SweepInput +
- VC
R
IB
ICRc
IT Pin 7or 8
12
ÁÁ100
Figure 11. Circuit tor Sine Wave Generation without External Adjustment.(See Figure 3 for Choice of R 3)
R=200K
Fre
quen
cy D
rift (
%)
+
-
1 5
6
7 8
9
11
3
2
13
14
15
164
10 1 2 XR-2206
1F
C
R12M 1K
S1
Triangle OrSine Wave Output
Square WaveOutput
200
10KR350K
5.1K 5.1KVCC
10F
1F
R
VCC
VCC
CurrentSwitches
Mult.AndSine
Shaper
+1
+
+
VCO
S1 Closed For Sinewave
3V
XR-2206
9
Rev. 1.03
0
Figure 12. Circuit for Sine Wave Generation with Minimum Harmonic Distortion. (R3 Determines Output Swing - See Figure 3 )
Figure 13. Sinusoidal FSK Generator
Symmetry Adjust
25K RB
1 5
6
7 8
9
11
3
2
13
1415
164
1 12 XR-2206
1F
C
1KR12M
F =S1
Triangle OrSine Wave OutputSquare WaveOutput
RA
500
10K
5.1K 5.1K
10F
R350K
1F
R
Mult.AndSine
Shaper
CurrentSwitches
VCC
VCC
VCO
+
+
+1
VCC
1 5
6
7 8
9
11
3
2
13
14
15
164
10 12 XR-2206
1F
VCC
C
FSK InputR1
R2
<1V
>2V F1
F2
F1=1/R1C
200
5.1K 5.1K
10F
1F
R350K
F2=1/R2C
VCC
Mult.AndSine
Shaper
VCO
+
+
+1Current
Switches
S1 Closed For Sinewave1RC
FSK Output
XR-2206
10
Rev. 1.03
Figure 14. Circuit for Pulse and Ramp Generation.
1 5
6
7 8
9
11
3
2
13
1415
16
4
10 12 XR-2206
1F
VCC
C
R1R2
5.1K
5.1K 5.1K
10F
1F
R324K
VCC
VCC
Mult.AndSine
Shaper
VCO
+1
+
+
CurrentSwitches
f 2C 1
R1 R2
R1
R1 R2Duty Cycle =
Sawtooth Output
Pulse Output
Frequency-Shift Keying
The XR-2206 can be operated with two separate timingresistors, R1 and R2, connected to the timing Pin 7 and 8,respectively, as shown in Figure 13. Depending on thepolarity of the logic signal at Pin 9, either one or the otherof these timing resistors is activated. If Pin 9 isopen-circuited or connected to a bias voltage 2V, onlyR1 is activated. Similarly, if the voltage level at Pin 9 is1V, only R2 is activated. Thus, the output frequency canbe keyed between two levels. f1 and f2, as:
f1 = 1/R1C and f2 = 1/R2C
For split-supply operation, the keying voltage at Pin 9 isreferenced to V-.
Output DC Level Control
The dc level at the output (Pin 2) is approximately thesame as the dc bias at Pin 3. In Figure 11, Figure 12 andFigure 13, Pin 3 is biased midway between V+ andground, to give an output dc level of V+/2.
APPLICATIONS INFORMATION
Sine Wave Generation
Without External Adjustment
Figure 11 shows the circuit connection for generating asinusoidal output from the XR-2206. The potentiometer,R1 at Pin 7, provides the desired frequency tuning. Themaximum output swing is greater than V+/2, and thetypical distortion (THD) is < 2.5%. If lower sine wavedistortion is desired, additional adjustments can beprovided as described in the following section.
The circuit of Figure 11 can be converted to split-supplyoperation, simply by replacing all ground connectionswith V-. For split-supply operation, R3 can be directlyconnected to ground.
XR-2206
11
Rev. 1.03
With External Adjustment:
The harmonic content of sinusoidal output can bereduced to -0.5% by additional adjustments as shown inFigure 12. The potentiometer, RA, adjusts thesine-shaping resistor, and RB provides the fineadjustment for the waveform symmetry. The adjustmentprocedure is as follows:
1. Set RB at midpoint and adjust RA for minimum distortion.
2. With RA set as above, adjust RB to further reduce distortion.
Triangle Wave Generation
The circuits of Figure 11 and Figure 12 can be convertedto triangle wave generation, by simply open-circuiting Pin13 and 14 (i.e., S1 open). Amplitude of the triangle isapproximately twice the sine wave output.
FSK Generation
Figure 13 shows the circuit connection for sinusoidal FSKsignal operation. Mark and space frequencies can beindependently adjusted by the choice of timing resistors,R1 and R2; the output is phase-continuous duringtransitions. The keying signal is applied to Pin 9. Thecircuit can be converted to split-supply operation bysimply replacing ground with V-.
Pulse and Ramp Generation
Figure 14 shows the circuit for pulse and ramp waveformgeneration. In this mode of operation, the FSK keyingterminal (Pin 9) is shorted to the square-wave output (Pin11), and the circuit automatically frequency-shift keysitself between two separate frequencies during thepositive-going and negative-going output waveforms.The pulse width and duty cycle can be adjusted from 1%to 99% by the choice of R1 and R2. The values of R1 andR2 should be in the range of 1k to 2M.
PRINCIPLES OF OPERATION
Description of Controls
Frequency of Operation:
The frequency of oscillation, fo, is determined by theexternal timing capacitor, C, across Pin 5 and 6, and bythe timing resistor, R, connected to either Pin 7 or 8. Thefrequency is given as:
f0 1
RC Hz
and can be adjusted by varying either R or C. Therecommended values of R, for a given frequency range,as shown in Figure 5. Temperature stability is optimumfor 4k < R < 200k. Recommended values of C are from1000pF to 100F.
Frequency Sweep and Modulation:
Frequency of oscillation is proportional to the total timingcurrent, IT, drawn from Pin 7 or 8:
f 320IT (mA)
C(F)Hz
Timing terminals (Pin 7 or 8) are low-impedance points,and are internally biased at +3V, with respect to Pin 12.Frequency varies linearly with IT, over a wide range ofcurrent values, from 1A to 3mA. The frequency can becontrolled by applying a control voltage, VC, to theactivated timing pin as shown in Figure 10. The frequencyof oscillation is related to VC as:
f 1RC1 R
RC
1 –VC
3Hz
where VC is in volts. The voltage-to-frequency conversiongain, K, is given as:
K fVC – 0.32RCC
HzV
CAUTION: For safety operation of the circuit, IT should belimited to 3mA.
XR-2206
12
Rev. 1.03
Output Amplitude:
Maximum output amplitude is inversely proportional tothe external resistor, R3, connected to Pin 3 (seeFigure 3). For sine wave output, amplitude isapproximately 60mV peak per k of R3; for triangle, thepeak amplitude is approximately 160mV peak per k ofR3. Thus, for example, R3 = 50k would produceapproximately 13V sinusoidal output amplitude.
Amplitude Modulation:
Output amplitude can be modulated by applying a dc biasand a modulating signal to Pin 1. The internal impedance
at Pin 1 is approximately 100k. Output amplitude varieslinearly with the applied voltage at Pin 1, for values of dcbias at this pin, within 14 volts of VCC/2 as shown inFigure 6. As this bias level approaches VCC/2, the phaseof the output signal is reversed, and the amplitude goesthrough zero. This property is suitable for phase-shiftkeying and suppressed-carrier AM generation. Totaldynamic range of amplitude modulation is approximately55dB.
CAUTION: AM control must be used in conjunction with awell-regulated supply, since the output amplitude now becomesa function of VCC.
Figure 15. Equivalent Schematic Diagram
21616145 1311VR V215VCC
5
6
7VCC
VR
V1
V2Reg.Int’nI.
12
4
VCC10
VR
V1
VR
8
9
3
XR-2206
13
Rev. 1.03
A 0.100 0.200 2.54 5.08
A1 0.015 0.060 0.38 1.52
B 0.014 0.026 0.36 0.66
B1 0.045 0.065 1.14 1.65
c 0.008 0.018 0.20 0.46
D 0.740 0.840 18.80 21.34
E1 0.250 0.310 6.35 7.87
E 0.300 BSC 7.62 BSC
e 0.100 BSC 2.54 BSC
L 0.125 0.200 3.18 5.08
α 0° 15° 0° 15°
D
B
e
B1
16 LEAD CERAMIC DUAL-IN-LINE(300 MIL CDIP)
Rev. 1.00
SYMBOL MIN MAX MIN MAX
INCHES MILLIMETERS
1 8
9
αc
E1
A
L
A1
SeatingPlane
BasePlane
16
E
Note: The control dimension is the inch column
XR-2206
14
Rev. 1.03
16 LEAD PLASTIC DUAL-IN-LINE(300 MIL PDIP)
Rev. 1.00
16
1
9
8
D
e B1
A1
E1
E
AL
B
SeatingPlane
SYMBOL MIN MAX MIN MAX
INCHES
A 0.145 0.210 3.68 5.33
A1 0.015 0.070 0.38 1.78
A2 0.115 0.195 2.92 4.95
B 0.014 0.024 0.36 0.56
B1 0.030 0.070 0.76 1.78
C 0.008 0.014 0.20 0.38
D 0.745 0.840 18.92 21.34
E 0.300 0.325 7.62 8.26
E1 0.240 0.280 6.10 7.11
e 0.100 BSC 2.54 BSC
eA 0.300 BSC 7.62 BSC
eB 0.310 0.430 7.87 10.92
L 0.115 0.160 2.92 4.06
α 0° 15° 0° 15°
MILLIMETERS
α
A2
C
Note: The control dimension is the inch column
eB
eA
XR-2206
15
Rev. 1.03
SYMBOL MIN MAX MIN MAX
A 0.093 0.104 2.35 2.65
A1 0.004 0.012 0.10 0.30
B 0.013 0.020 0.33 0.51
C 0.009 0.013 0.23 0.32
D 0.398 0.413 10.10 10.50
E 0.291 0.299 7.40 7.60
e 0.050 BSC 1.27 BSC
H 0.394 0.419 10.00 10.65
L 0.016 0.050 0.40 1.27
α 0° 8° 0° 8°
INCHES MILLIMETERS
16 LEAD SMALL OUTLINE(300 MIL JEDEC SOIC)
Rev. 1.00
e
16 9
8
D
E H
B
A
L
C
A1
SeatingPlane α
Note: The control dimension is the millimeter column
1
XR-2206
16
Rev. 1.03
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits arefree of patent infringement. Charts and schedules contained here in are only for illustration purposes and may varydepending upon a user’s specific application. While the information in this publication has been carefully checked;no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure ormalfunction of the product can reasonably be expected to cause failure of the life support system or to significantlyaffect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporationreceives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) theuser assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-stances.
Copyright 1972 EXAR CorporationDatasheet June 1997Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
UF4001 THRU UF4007ULTRAFAST EFFICIENT PLASTIC RECTIFIER
Reverse Voltage - 50 to 1000 Volts Forward Current - 1.0 Ampere
FEATURES ♦ Plastic package has Underwriters Laboratory
Flammability Classification 94V-0♦ 1.0 ampere operation at TA=55°C with no thermal
runaway♦ Glass passivated chip junction♦ Low cost♦ Ultrafast recovery
time for high efficiency♦ Low forward voltage ♦ Low leakage current♦ High surge current capability♦ High temperature soldering guaranteed:
250°C/10 seconds, 0.375" (9.5mm) lead length,5 lbs. (2.3kg) tension
MECHANICAL DATA Case: JEDEC DO-204AL molded plastic body overpassivated chipTerminals: Plated axial leads, solderable per MIL-STD-750,Method 2026Polarity: Color band denotes cathode end Mounting Position: AnyWeight: 0.012 ounce, 0.3 gram
MAXIMUM RATINGS AND ELECTRICAL CHARACTERISTICS
Ratings at 25°C ambient temperature unless otherwise specified..
UF UF UF UF UF UF UFSYMBOLS 4001 4002 4003 4004 4005 4006 4007 UNITS
Maximum repetitive peak reverse voltage VRRM 50 100 200 400 600 800 1000 Volts
Maximum RMS voltage VRMS 35 70 140 280 420 560 700 Volts
Maximum DC blocking voltage VDC 50 100 200 400 600 800 1000 Volts
Maximum average forward rectified current 0.375" (9.5mm) lead length at TA=55°C I(AV) 1.0 Amp
Peak forward surge current8.3ms single half sine-wave superimposed on IFSM 30.0 Ampsrated load (JEDEC Method)
Maximum instantaneous forward voltage at 1.0A VF 1.0 1.7 Volts
Maximum DC reverse current TA=25°C 10.0at rated DC blocking voltage TA=100°C IR 50.0 µA
Maximum reverse recovery time (NOTE 1) trr 50.0 75.0 ns
Typical junction capacitance (NOTE 2) CJ 17.0 pF
Typical thermal resistance (NOTE 3) RΘJA 60.0RΘJL 15.0 °C/W
Operating junction and storage temperature range TJ, TSTG -55 to +150 °C
NOTES:(1) Reverse recovery test conditions: IF=0.5A, IR=1.0A, Irr=0.25A(2) Measured at 1.0 MHZ and applied reverse voltage of 4.0 Volts(3) Thermal resistance from junction to ambient and from junction to lead length 0.375" ( 9.5mm), P.C.B. mounted
4/98
0.107 (2.7)0.080 (2.0)
0.034 (0.86)0.028 (0.71)
DIA.
1.0 (25.4) MIN.
1.0 (25.4) MIN.
0.205 (5.2)0.160 (4.1)
DIA.
NOTE: Lead diameter is for suffix "E" part numbers0.026 (0.66)0.023 (0.58)
DO-204AL
Dimensions in inches and (millimeters)
1.0
20 40 60 80 100 120 140 1600
0.5
1 10 1000
5.0
10
15
20
25
30
0.1 1 10 1001
10
100
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.80.001
0.01
0.1
1
10
0 20 40 60 80 1000.01
0.1
1
10
100
RATINGS AND CHARACTERISTIC CURVES UF4001 THRU UF4007
FIG. 1 - MAXIMUM FORWARD CURRENT DERATING CURVE
AMBIENT TEMPERATURE, °C
AV
ER
AG
E F
OR
WA
RD
RE
CT
IFIE
DC
UR
RE
NT,
AM
PE
RE
S
FIG. 2 - MAXIMUM NON-REPETITIVE PEAK FORWARD SURGE CURRENT
NUMBER OF CYCLES AT 60 HZ
PE
AK
FO
RW
AR
D S
UR
GE
CU
RR
EN
T,A
MP
ER
ES
FIG. 3 - TYPICAL INSTANTANEOUSFORWARD CHARACTERISTICS
FIG. 4 - TYPICAL REVERSE LEAKAGECHARACTERISTICS
INS
TAN
TAN
EO
US
FO
RW
AR
D C
UR
RE
NT,
AM
PE
RE
S
INS
TAN
TAN
EO
US
RE
VE
RS
E L
EA
KA
GE
CU
RR
EN
T,
MIC
RO
AM
PE
RE
S
INSTANTANEOUS FORWARD VOLTAGE,VOLTS
PERCENT OF RATED PEAK REVERSE VOLTAGE, %
FIG. 5 - TYPICAL JUNCTION CAPACITANCE
JUN
CT
ION
CA
PAC
ITA
NC
E,
pF
REVERSE VOLTAGE, VOLTS
TA=55°C8.3ms SINGLE HALF SINE-WAVE(JEDEC Method)
TJ=125°C
TJ=125°C
TJ=25°C
TJ=25°CPULSE WIDTH=300µs1% DUTY CYCLE
RESISTIVE ORINDUCTIVE LOAD0.375" (9.5mm)LEAD LENGTH
TJ=100°C
UF4001-UF4004UF4005-UF4007
TJ=100°C
UF4001 - UF4004
UF4005 - UF4007
TJ=25°Cf=1.0 MHzVsig=50mVp-p
1
®
HIP4082July 2004Data Sheet FN3676.3
80V, 1.25A Peak Current H-Bridge FET DriverThe HIP4082 is a medium frequency, medium voltage H-Bridge N-Channel MOSFET driver IC, available in 16 lead plastic SOIC (N) and DIP packages.
Specifically targeted for PWM motor control and UPS applications, bridge based designs are made simple and flexible with the HIP4082 H-bridge driver. With operation up to 80V, the device is best suited to applications of moderate power levels.
Similar to the HIP4081, it has a flexible input protocol for driving every possible switch combination except those which would cause a shoot-through condition. The HIP4082’s reduced drive current allows smaller packaging and it has a much wider range of programmable dead times (0.1 to 4.5µs) making it ideal for switching frequencies up to 200kHz. The HIP4082 does not contain an internal charge pump, but does incorporate non-latching level-shift translation control of the upper drive circuits.
This set of features and specifications is optimized for applications where size and cost are important. For applications needing higher drive capability the HIP4080A and HIP4081A are recommended.
Features• Independently Drives 4 N-Channel FET in Half Bridge or
Full Bridge Configurations
• Bootstrap Supply Max Voltage to 95VDC
• Drives 1000pF Load in Free Air at 50°C with Rise and Fall Times of Typically 15ns
• User-Programmable Dead Time (0.1 to 4.5µs)
• DIS (Disable) Overrides Input Control and Refreshes Bootstrap Capacitor when Pulled Low
• Input Logic Thresholds Compatible with 5V to 15V Logic Levels
• Shoot-Through Protection
• Undervoltage Protection
• Pb-free Available
Applications• UPS Systems
• DC Motor Controls
• Full Bridge Power Supplies
• Switching Power Amplifiers
• Noise Cancellation Systems
• Battery Powered Vehicles
• Peripherals
• Medium/Large Voice Coil Motors
• Related Literature- TB363, Guidelines for Handling and Processing
Moisture Sensitive Surface Mount Devices (SMDs)
PinoutHIP4082
(PDIP, SOIC)TOP VIEW
Ordering InformationPART
NUMBERTEMP.
RANGE (°C) PACKAGEPKG.
DWG. #
HIP4082IB -55 to +125 16 Ld SOIC (N) M16.15
HIP4082IBZ (Note)
-55 to +125 16 Ld SOIC (N) (Pb-free) M16.15
HIP4082IP -55 to +125 16 Ld PDIP E16.3
HIP4082IPZ (Note)
-55 to +125 16 Ld PDIP (Pb-free) E16.3
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
BHB
BHI
BLI
ALI
DEL
VSS
DIS
AHI
BHO
BLO
ALO
VDD
AHS
AHO
AHB
BHS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Harris Corporation 1995. Copyright Intersil Americas Inc. 2003, 2004. All Rights ReservedAll other trademarks mentioned are the property of their respective owners.
HIP4082
Application Block Diagram
Functional Block Diagram
80V
GND
LOAD
HIP4082
GND
12V
AHI
ALI
BLI
BHI BLO
BHS
BHO
ALO
AHS
AHO
3
8
2
7
4
12
5
6
TURN-ONDELAY
DRIVER
13
LEVELSHIFT
DRIVER
AHB
AHS
9
10
11
14
15
16
1DRIVER
TURN-ONDELAY
DRIVERTURN-ON
DELAY
LEVELSHIFT
AHO
BHB
BHS
BHO
ALO BLO
TURN-ONDELAY
UNDERVOLTAGEDETECTOR
VDD
BHI
AHI
DIS
ALI
VDD
DEL
BLI
VSS
U/V U/V
2
HIP4082
Typical Application (PWM Mode Switching)
80V
12V
12V
DIS
GND
GND
TO OPTIONALCURRENT CONTROLLER OR
PWM
LOAD
INPUT
+-
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
BHB
BHI
BLI
ALI
DEL
VSS
DIS
AHI
BHO
BLO
ALO
VDD
AHS
AHO
AHB
BHS
OVERCURRENT LATCH
RDIS
DELAY RESISTOR
FROMOPTIONAL
OVERCURRENT LATCH
RSH
3
HIP4082
Absolute Maximum Ratings Thermal InformationSupply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16VLogic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3VVoltage on AHS, BHS . . . . . -6V (Transient) to 80V (25°C to 150°C)Voltage on AHS, BHS . . . . . -6V (Transient) to 70V (-55°C to150°C)Voltage on AHB, BHB . . . . . . . . VAHS, BHS -0.3V to VAHS, BHS +VDDVoltage on ALO, BLO . . . . . . . . . . . . . . . . . VSS -0.3V to VDD +0.3VVoltage on AHO, BHO . . . VAHS, BHS -0.3V to VAHB, BHB +0.3V InputCurrent, DEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA to 0mAPhase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/nsNOTE: All voltages are relative VSS unless otherwise specified.
Thermal Resistance, Junction-Ambient θJA (°C/W)SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Maximum Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . See CurveStorage Temperature Range . . . . . . . . . . . . . . . . . . -65°C to +150°COperating Max. Junction Temperature . . . . . . . . . . . . . . . . . +150°CLead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300°C
(For SOIC - Lead Tips Only))
Operating ConditionsSupply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . +8.5V to +15VVoltage on VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to +1.0VVoltage on AHB, BHB . . . . . . . VAHS, BHS +7.5V to VAHS, BHS +VDDInput Current, DEL . . . . . . . . . . . . . . . . . . . . . . . . . -4mA to -100µA
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of thedevice at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications VDD = VAHB = VBHB = 12V, VSS = VAHS = VBHS = 0V, RDEL = 100K
PARAMETER SYMBOL TEST CONDITIONS
TJ = +25°CTJ = -55°C TO +150°C
UNITSMIN TYP MAX MIN MAX
SUPPLY CURRENTS & UNDER VOLTAGE PROTECTION
VDD Quiescent Current IDD All inputs = 0V, RDEL = 100K 1.2 2.3 3.5 0.85 4 mA
All inputs = 0V, RDEL = 10K 2.2 4.0 5.5 1.9 6.0 mA
VDD Operating Current IDDO f = 50kHz, no load 1.5 2.6 4.0 1.1 4.2 mA
50kHz, no load, RDEL = 10kΩ 2.5 4.0 6.4 2.1 6.6 mA
AHB, BHB Off Quiescent Current IAHBL, IBHBL AHI = BHI = 0V 0.5 1.0 1.5 0.4 1.6 mA
AHB, BHB On Quiescent Current IAHBH, IBHBH AHI = BHI = VDD 65 145 240 40 250 µA
AHB, BHB Operating Current IAHBO, IBHBO f = 50kHz, CL = 1000pF .65 1.1 1.8 .45 2.0 mA
AHS, BHS Leakage Current IHLK VAHS = VBHS = 80VVAHB = VBHB = 96
- - 1.0 - - µA
VDD Rising Undervoltage Threshold VDDUV+ 6.8 7.6 8.25 6.5 8.5 V
VDD Falling Undervoltage Threshold VDDUV- 6.5 7.1 7.8 6.25 8.1 V
Undervoltage Hysteresis UVHYS 0.17 0.4 0.75 0.15 0.90 V
AHB, BHB Undervoltage Threshold VHBUV Referenced to AHS & BHS 5 6.0 7 4.5 7.5 V
INPUT PINS: ALI, BLI, AHI, BHI, & DIS
Low Level Input Voltage VIL Full Operating Conditions - - 1.0 - 0.8 V
High Level Input Voltage VIH Full Operating Conditions 2.5 - - 2.7 V
Input Voltage Hysteresis - 35 - - - mV
Low Level Input Current IIL VIN = 0V, Full Operating Conditions -145 -100 -60 -150 -50 µA
High Level Input Current IIH VIN = 5V, Full Operating Conditions -1 - +1 -10 +10 µA
TURN-ON DELAY PIN DEL
Dead Time TDEAD RDEL = 100K 2.5 4.5 8.0 2.0 8.5 µS
RDEL = 10K 0.27 0.5 0.75 0.2 0.85 µS
GATE DRIVER OUTPUT PINS: ALO, BLO, AHO, & BHO
Low Level Output Voltage VOL IOUT = 50mA 0.65 1.1 0.5 1.2 V
High Level Output Voltage VDD-VOH IOUT = -50mA 0.7 1.2 0.5 1.3 V
4
HIP4082
Peak Pullup Current IO+ VOUT = 0V 1.1 1.4 2.5 0.85 2.75 A
Peak Pulldown Current IO- VOUT = 12V 1.0 1.3 2.3 0.75 2.5 A
Switching Specifications VDD = VAHB = VBHB = 12V, VSS = VAHS = VBHS = 0V, RDEL= 100K, CL = 1000pF.
PARAMETER SYMBOL TEST CONDITIONS
TJ = +25°CTJ = -55°C TO
+150°C
UNITSMIN TYP MAX MIN MAX
Lower Turn-off Propagation Delay(ALI-ALO, BLI-BLO)
TLPHL - 25 50 - 70 ns
Upper Turn-off Propagation Delay(AHI-AHO, BHI-BHO)
THPHL - 55 80 - 100 ns
Lower Turn-on Propagation Delay(ALI-ALO, BLI-BLO)
TLPLH - 40 85 - 100 ns
Upper Turn-on Propagation Delay(AHI-AHO, BHI-BHO)
THPLH - 75 110 - 150 ns
Rise Time TR - 9 20 - 25 ns
Fall Time TF - 9 20 - 25 ns
Minimum Input Pulse Width TPWIN-ON/OFF 50 - - 50 - ns
Output Pulse Response to 50 ns Input Pulse TPWOUT 63 80 ns
Disable Turn-off Propagation Delay(DIS - Lower Outputs)
TDISLOW - 50 80 - 90 ns
Disable Turn-off Propagation Delay(DIS - Upper Outputs)
TDISHIGH - 75 100 - 125 ns
Disable Turn-on Propagation Delay(DIS - ALO & BLO)
TDLPLH - 40 70 - 100 ns
Disable Turn-on Propagation Delay (DIS- AHO & BHO)
TDHPLH RDEL = 10K - 1.2 2 - 3 µs
Refresh Pulse Width (ALO & BLO) TREF-PW 375 580 900 350 950 ns
TRUTH TABLE
INPUT OUTPUT
ALI, BLI AHI, BHI VDDUV VHBUV DIS ALO, BLO AHO, BHO
X X X X 1 0 0
X X 1 X X 0 0
0 X 0 1 0 0 0
1 X 0 X 0 1 0
0 1 0 0 0 0 1
0 0 0 0 0 0 0
NOTE: X signifies that input can be either a “1” or “0”.
Electrical Specifications VDD = VAHB = VBHB = 12V, VSS = VAHS = VBHS = 0V, RDEL = 100K (Continued)
PARAMETER SYMBOL TEST CONDITIONS
TJ = +25°CTJ = -55°C TO +150°C
UNITSMIN TYP MAX MIN MAX
5
6
HIP4082
Pin Descriptions PIN
NUMBER SYMBOL DESCRIPTION
1 BHB B High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrapdiode and positive side of bootstrap capacitor to this pin.
2 BHI B High-side Input. Logic level input that controls BHO driver (Pin 16). BLI (Pin 3) high level input overrides BHI highlevel input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 8) high level input overrides BHI high levelinput. The pin can be driven by signal levels of 0V to 15V (no greater than VDD).
3 BLI B Low-side Input. Logic level input that controls BLO driver (Pin 14). If BHI (Pin 2) is driven high or not connectedexternally then BLI controls both BLO and BHO drivers, with dead time set by delay currents at DEL (Pin 5). DIS (Pin8) high level input overrides BLI high level input. The pin can be driven by signal levels of 0V to 15V (no greater thanVDD).
4 ALI A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not connectedexternally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at DEL (Pin 5). DIS (Pin8) high level input overrides ALI high level input. The pin can be driven by signal levels of 0V to 15V (no greater thanVDD).
5 DEL Turn-on DELay. Connect resistor from this pin to VSS to set timing current that defines the dead time between drivers.All drivers turn-off with no adjustable delay, so the DEL resistor guarantees no shoot-through by delaying the turn-onof all drivers. The voltage across the DEL resistor is approximately Vdd -2V.
6 VSS Chip negative supply, generally will be ground.
7 AHI A High-side Input. Logic level input that controls AHO driver (Pin 10). ALI (Pin 4) high level input overrides AHI highlevel input to prevent half-bridge shoot-through, see Truth Table. DIS (Pin 8) high level input overrides AHI high levelinput. The pin can be driven by signal levels of 0V to 15V (no greater than VDD).
8 DIS DISable input. Logic level input that when taken high sets all four outputs low. DIS high overrides all other inputs.When DIS is taken low the outputs are controlled by the other inputs. The pin can be driven by signal levels of 0V to15V (no greater than VDD).
9 AHB A High-side Bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrapdiode and positive side of bootstrap capacitor to this pin.
10 AHO A High-side Output. Connect to gate of A High-side power MOSFET.
11 AHS A High-side Source connection. Connect to source of A High-side power MOSFET. Connect negative side ofbootstrap capacitor to this pin.
12 VDD Positive supply to control logic and lower gate drivers. De-couple this pin to VSS (Pin 6).
13 ALO A Low-side Output. Connect to gate of A Low-side power MOSFET.
14 BLO B Low-side Output. Connect to gate of B Low-side power MOSFET.
15 BHS B High-side Source connection. Connect to source of B High-side power MOSFET. Connect negative side ofbootstrap capacitor to this pin.
16 BHO B High-side Output. Connect to gate of B High-side power MOSFET.
HIP4082
7
HIP4082
Timing Diagrams
FIGURE 1. INDEPENDENT MODE
FIGURE 2. BISTATE MODE
FIGURE 3. DISABLE FUNCTION
DIS=0
XLI
XHI
XLO
XHO
TLPHL THPHL
THPLH TLPLH TR(10% - 90%)
TF(10% - 90%)
X = A OR B, A AND B HALVES OF BRIDGE CONTROLLER ARE INDEPENDENT
and UV
DIS=0
XLI
XHI = HI OR NOT CONNECTED
XLO
XHO
and UV
DIS or UV
XLI
XHI
XLO
XHO
TDLPLH TDIS
TDHPLH
TREF-PW
HIP4082
HIP4082
Performance Curves
FIGURE 4. IDD SUPPLY CURRENT vs TEMPERATURE AND VDD SUPPLY VOLTAGE
FIGURE 5. VDD SUPPLY CURRENT vs TEMPERATURE AND SWITCHING FREQUENCY (1000pF LOAD)
FIGURE 6. FLOATING (IXHB) BIAS CURRENT vs FREQUENCY AND LOAD
FIGURE 7. GATE SOURCE/SINK PEAK CURRENT vs BIAS SUPPLY VOLTAGE AT 25°C
FIGURE 8. GATE CURRENT vs TEMPERATURE, NORMALIZED TO 25°C
FIGURE 9. VDD-VOH vs BIAS VOLTAGE TEMPERATURE
-60 -40 -20 0 20 40 60 80 100 120 1401.5
1.75
2
2.25
2.5
2.75
3
3.25
3.5
JUNCTION TEMPERATURE (°C)
I DD
SU
PP
LY C
UR
RE
NT
(mA
) VDD = 16VVDD = 15V
VDD = 12V
VDD = 10V
VDD = 8V
-60 -40 -20 0 20 40 60 80 100 120 140456789
10111213141516
JUNCTION TEMPERATURE (°C)
I DD
SU
PP
LY C
UR
RE
NT
(mA
)
200kHz
100kHz
50kHz
10kHz
0 50 100 150 2000
1
2
3
4
5
6
7
8
FREQUENCY (kHz)
LOA
DE
D, N
L B
IAS
CU
RR
EN
TS (m
A)
1000pF LOAD
NO LOAD
8 9 10 11 12 13 14 150.5
0.75
1
1.25
1.5
1.75
BIAS SUPPLY VOLTAGE (V) AT 25°C
PE
AK
GA
TE C
UR
RE
NT
(A)
1.925
0.815
ISRC(BIAS)
ISNK(BIAS)
BIAS
2
8 15
SOURCE
SINK
-75 -50 -25 0 25 50 75 100 125 1500.8
0.9
1
1.1
1.2
JUNCTION TEMPERATURE (°C)
NO
RM
ALI
ZED
GA
TES
INK
/SO
UR
CE
CU
RR
EN
T (A
)
8 9 10 11 12 13 14 15
0.6
1
1.4
VDD SUPPLY VOLTAGE (V)
VD
D-V
OH
(V)
1.2
0.8
-55°C-40°C
0°C25°C
125°C 150°C
8
HIP4082
FIGURE 10. VOL vs BIAS VOLTAGE AND TEMPERATURE FIGURE 11. UNDERVOLTAGE TRIP VOLTAGES vs TEMPERA-TURE
FIGURE 12. UPPER LOWER TURN-ON/TURN-OFF PROPAGA-TION DELAY vs TEMPERATURE
FIGURE 13. UPPER/LOWER DIS(ABLE) TO TURN-ON/OFF vs TEMPERATURE (°C)
FIGURE 14. FULL BRIDGE LEVEL-SHIFT CURRENT vs FREQUENCY (kHz)
FIGURE 15. MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE
Performance Curves (Continued)
8 9 10 11 12 13 14
1.4
VDD SUPPLY VOLTAGE (V)
VO
L (V
)
15
1.2
0.8
0.6
-55°C-40°C 0°C 25°C
125°C
150°C
1
-60 -40 -20 0 20 40 60 80 100 120 140 1605
5.5
6
6.5
7
7.5
8
JUNCTION TEMPERATURE (°C)
VD
D, B
IAS
SU
PP
LY V
OLT
AG
E (V
) LOWER U/V RESET
LOWER U/V SET
UPPER U/V SET/RESET
-60 -40 -20 0 20 40 60 80 100 120 140 16020
30
40
50
60
70
80
90
100
JUNCTION TEMPERATURE (°C)
PR
OP
AG
ATI
ON
DE
LAY
S (n
s)
UPPER tON
UPPER tOFF
LOWER tON
LOWER tOFF
-60 -40 -20 0 20 40 60 80 100 120 140 16010
100
104
JUNCTION TEMPERATURE (°C)
DIS
TO
TU
RN
-ON
/OFF
TIM
E (n
s)
1000
DISHTON
DISHTOFF
DISLTONDISLOFF
0 20 40 60 80 1000.5
1
1.5
2
SWITCHING FREQUENCY (kHz)
LEV
EL-
SH
IFT
CU
RR
EN
T (m
A)
-60 -30 0 30 60 90 120 1500
0.5
1
1.5
2
2.5
AMBIENT TEMPERATURE (°C)
TOTA
L P
OW
ER
DIS
SIP
ATI
ON
(W)
SOIC
16 PIN DIP
QUIESCENT BIAS COMPONENT
9
HIP4082
FIGURE 16. DEAD-TIME vs DEL RESISTANCE AND BIAS SUPPLY (VDD) VOLTAGE
FIGURE 17. MAXIMUM OPERATING PEAK AHS/BHS VOLTAGE vs TEMPERATURE
Performance Curves (Continued)
0 10 20 30 40 50 60 70 80 90 100100
1000
104
DEAD TIME RESISTANCE (kΩ)
DE
AD
TIM
E (n
s)
VDD = 12V
VDD = 9V
VDD = 15V
100 50 0 50 100 15070
75
80
85
90
TEMPERATURE (°C)
VX
HS-V
SS
10
11
HIP4082
Dual-In-Line Plastic Packages (PDIP)
NOTES:1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.2. Dimensioning and tolerancing per ANSI Y14.5M-1982.3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.4. Dimensions A, A1 and L are measured with the package seated in JE-
DEC seating plane gauge GS-3.5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).6. E and are measured with the leads constrained to be perpendic-
ular to datum .7. eB and eC are measured at the lead tips with the leads unconstrained.
eC must be zero or greater.8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA-C-
CL
E
eA
C
eB
eC
-B-
E1INDEX 1 2 3 N/2
N
AREA
SEATING
BASEPLANE
PLANE
-C-
D1
B1B
e
D
D1
AA2
L
A1
-A-
0.010 (0.25) C AM B S
E16.3 (JEDEC MS-001-BB ISSUE D)16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA 0.300 BSC 7.62 BSC 6
eB - 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N 16 16 9
Rev. 0 12/93
12
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time withoutnotice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate andreliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may resultfrom its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
HIP4082HIP4082
Small Outline Plastic Packages (SOIC)
NOTES:1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.2. Dimensioning and tolerancing per ANSI Y14.5M-1982.3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-terlead flash and protrusions shall not exceed 0.25mm (0.010inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.7. “N” is the number of terminal positions.8. Terminal numbers are shown for reference only.9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-sions are not necessarily exact.
INDEXAREA
E
D
N
1 2 3
-B-
0.25(0.010) C AM B S
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
µ
0.25(0.010) BM M
α
M16.15 (JEDEC MS-012-AC ISSUE C)16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.053 0.069 1.35 1.75 -
A1 0.004 0.010 0.10 0.25 -
B 0.014 0.019 0.35 0.49 9
C 0.007 0.010 0.19 0.25 -
D 0.386 0.394 9.80 10.00 3
E 0.150 0.157 3.80 4.00 4
e 0.050 BSC 1.27 BSC -
H 0.228 0.244 5.80 6.20 -
h 0.010 0.020 0.25 0.50 5
L 0.016 0.050 0.40 1.27 6
N 16 16 7
α 0o 8o 0o 8o -
Rev. 1 02/02
Philips Semiconductors Product specification
N-channel TrenchMOS transistor IRF540, IRF540S
FEATURES SYMBOL QUICK REFERENCE DATA
• ’Trench’ technology• Low on-state resistance VDSS = 100 V• Fast switching• Low thermal resistance ID = 23 A
RDS(ON) ≤ 77 mΩ
GENERAL DESCRIPTIONN-channel enhancement mode field-effect power transistor in a plastic envelope using ’trench ’ technology.
Applications:-• d.c. to d.c. converters• switched mode power supplies• T.V. and computer monitor power supplies
The IRF540 is supplied in the SOT78 (TO220AB) conventional leaded package.The IRF540S is supplied in the SOT404 (D2PAK) surface mounting package.
PINNING SOT78 (TO220AB) SOT404 (D2PAK)
PIN DESCRIPTION
1 gate
2 drain1
3 source
tab drain
LIMITING VALUESLimiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDSS Drain-source voltage Tj = 25 ˚C to 175˚C - 100 VVDGR Drain-gate voltage Tj = 25 ˚C to 175˚C; RGS = 20 kΩ - 100 VVGS Gate-source voltage - ± 20 VID Continuous drain current Tmb = 25 ˚C; VGS = 10 V - 23 A
Tmb = 100 ˚C; VGS = 10 V - 16 AIDM Pulsed drain current Tmb = 25 ˚C - 92 APD Total power dissipation Tmb = 25 ˚C - 100 WTj, Tstg Operating junction and - 55 175 ˚C
storage temperature
d
g
s
1 3
tab
2
1 2 3
tab
1 It is not possible to make connection to pin:2 of the SOT404 package
August 1999 1 Rev 1.100
Philips Semiconductors Product specification
N-channel TrenchMOS transistor IRF540, IRF540S
AVALANCHE ENERGY LIMITING VALUESLimiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
EAS Non-repetitive avalanche Unclamped inductive load, IAS = 10 A; - 230 mJenergy tp = 350 µs; Tj prior to avalanche = 25˚C;
VDD ≤ 25 V; RGS = 50 Ω; VGS = 10 V; referto fig:14
IAS Peak non-repetitive - 23 Aavalanche current
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Rth j-mb Thermal resistance junction - - 1.5 K/Wto mounting base
Rth j-a Thermal resistance junction SOT78 package, in free air - 60 - K/Wto ambient SOT404 package, pcb mounted, minimum - 50 - K/W
footprint
ELECTRICAL CHARACTERISTICSTj= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V(BR)DSS Drain-source breakdown VGS = 0 V; ID = 0.25 mA; 100 - - Vvoltage Tj = -55˚C 89 - - V
VGS(TO) Gate threshold voltage VDS = VGS; ID = 1 mA 2 3 4 V Tj = 175˚C 1 - - VTj = -55˚C - - 6 V
RDS(ON) Drain-source on-state VGS = 10 V; ID = 17 A - 49 77 mΩresistance Tj = 175˚C - 132 193 mΩ
gfs Forward transconductance VDS = 25 V; ID = 17 A 8.7 15.5 - SIGSS Gate source leakage current VGS = ± 20 V; VDS = 0 V - 10 100 nAIDSS Zero gate voltage drain VDS = 100 V; VGS = 0 V - 0.05 10 µA
current VDS = 80 V; VGS = 0 V; Tj = 175˚C - - 250 µA
Qg(tot) Total gate charge ID = 17 A; VDD = 80 V; VGS = 10 V - - 65 nCQgs Gate-source charge - - 10 nCQgd Gate-drain (Miller) charge - - 29 nC
td on Turn-on delay time VDD = 50 V; RD = 2.2 Ω; - 8 - nstr Turn-on rise time VGS = 10 V; RG = 5.6 Ω - 39 - nstd off Turn-off delay time Resistive load - 26 - nstf Turn-off fall time - 24 - ns
Ld Internal drain inductance Measured tab to centre of die - 3.5 - nHLd Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH
(SOT78 package only)Ls Internal source inductance Measured from source lead to source - 7.5 - nH
bond pad
Ciss Input capacitance VGS = 0 V; VDS = 25 V; f = 1 MHz - 890 1187 pFCoss Output capacitance - 139 167 pFCrss Feedback capacitance - 83 109 pF
August 1999 2 Rev 1.100
Philips Semiconductors Product specification
N-channel TrenchMOS transistor IRF540, IRF540S
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICSTj = 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
IS Continuous source current - - 23 A(body diode)
ISM Pulsed source current (body - - 92 Adiode)
VSD Diode forward voltage IF = 28 A; VGS = 0 V - 0.94 1.5 V
trr Reverse recovery time IF = 17 A; -dIF/dt = 100 A/µs; - 61 - nsQrr Reverse recovery charge VGS = 0 V; VR = 25 V - 200 - nC
August 1999 3 Rev 1.100
Philips Semiconductors Product specification
N-channel TrenchMOS transistor IRF540, IRF540S
Fig.1. Normalised power dissipation.PD% = 100⋅PD/PD 25 ˚C = f(Tmb)
Fig.2. Normalised continuous drain current.ID% = 100⋅ID/ID 25 ˚C = f(Tmb); conditions: VGS ≥ 10 V
Fig.3. Safe operating area. Tmb = 25 ˚CID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.4. Transient thermal impedance.Zth j-mb = f(t); parameter D = tp/T
Fig.5. Typical output characteristics, Tj = 25 ˚C.ID = f(VDS)
Fig.6. Typical on-state resistance, Tj = 25 ˚C.RDS(ON) = f(ID)
Normalised Power Derating, PD (%)
0
10
20
30
40
50
60
70
80
90
100
0 25 50 75 100 125 150 175Mounting Base temperature, Tmb (C)
0.01
0.1
1
10
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00
Pulse width, tp (s)
Transient thermal impedance, Zth j-mb (K/W)
single pulse
D = 0.5
0.2
0.10.05
0.02tp D = tp/TDP
T
Normalised Current Derating, ID (%)
0
10
20
30
40
50
60
70
80
90
100
0 25 50 75 100 125 150 175Mounting Base temperature, Tmb (C)
0
5
10
15
20
25
30
35
40
45
50
55
0 1 2 3 4 5 6 7 8 9 10
Drain-Source Voltage, VDS (V)
Drain Current, ID (A)
4V
5 V
6 V
7 V
9 V 8 V
0.1
1
10
100
1000
1 10 100 1000Drain-Source Voltage, VDS (V)
Peak Pulsed Drain Current, IDM (A)
D.C.
100 ms10 ms
RDS(on) = VDS/ ID
1 ms
tp = 10 us
100 us
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0 10 20 30 40 50Drain Current, ID (A)
Drain-Source On Resistance, RDS(on) (Ohms)
VGS =9 V
8V
6V
7 V5 V
4V
5.5V
6.5V
August 1999 4 Rev 1.100
Philips Semiconductors Product specification
N-channel TrenchMOS transistor IRF540, IRF540S
Fig.7. Typical transfer characteristics.ID = f(VGS)
Fig.8. Typical transconductance, Tj = 25 ˚C.gfs = f(ID)
Fig.9. Normalised drain-source on-state resistance.RDS(ON)/RDS(ON)25 ˚C = f(Tj)
Fig.10. Gate threshold voltage.VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Fig.11. Sub-threshold drain current.ID = f(VGS); conditions: Tj = 25 ˚C; VDS = VGS
Fig.12. Typical capacitances, Ciss, Coss, Crss.C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
02468
1012141618202224262830
0 1 2 3 4 5 6 7 8 9 10
Gate-source voltage, VGS (V)
Drain current, ID (A)
VDS > ID X RDS(ON)
Tj = 25 C175 C
Threshold Voltage, VGS(TO) (V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)
typical
maximum
minimum
0
2
4
6
8
10
12
14
16
18
20
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30Drain current, ID (A)
Transconductance, gfs (S)
Tj = 25 C
175 C
VDS > ID X RDS(ON)
Drain current, ID (A)
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5Gate-source voltage, VGS (V)
minimum
typical
maximum
Normalised On-state Resistance
0.50.70.91.11.31.51.71.92.12.32.52.72.9
-60 -40 -20 0 20 40 60 80 100 120 140 160 180Junction temperature, Tj (C)
10
100
1000
10000
0.1 1 10 100Drain-Source Voltage, VDS (V)
Capacitances, Ciss, Coss, Crss (pF)
Ciss
Coss
Crss
August 1999 5 Rev 1.100
Philips Semiconductors Product specification
N-channel TrenchMOS transistor IRF540, IRF540S
Fig.13. Typical reverse diode current.IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
Fig.14. Maximum permissible non-repetitiveavalanche current (IAS) versus avalanche time (tAV);
unclamped inductive load
02468
1012141618202224262830
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
Source-Drain Voltage, VSDS (V)
Source-Drain Diode Current, IF (A)
Tj = 25 C
175 C
VGS = 0 V
0.1
1
10
100
0.001 0.01 0.1 1 10
Avalanche time, t AV (ms)
Maximum Avalanche Current, I AS (A)
Tj prior to avalanche = 150 C
25 C
August 1999 6 Rev 1.100
Philips Semiconductors Product specification
N-channel TrenchMOS transistor IRF540, IRF540S
MECHANICAL DATA
Fig.15. SOT78 (TO220AB); pin 2 connected to mounting base (Net mass:2g)
Notes1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.2. Refer to mounting instructions for SOT78 (TO220AB) package.3. Epoxy meets UL94 V0 at 1/8".
REFERENCESOUTLINEVERSION
EUROPEANPROJECTION ISSUE DATE
IEC JEDEC EIAJ
SOT78 TO-220
D
D1
q
P
L
1 2 3
L2(1)
b1
e e
b
0 5 10 mm
scale
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead TO-220 SOT78
DIMENSIONS (mm are the original dimensions)
AE
A1
c
Note
1. Terminals in this zone are not tinned.
Q
L1
UNIT A1 b1 D1 e P
mm 2.54
q QA b Dc L2(1)
max.
3.0 3.83.6
15.013.5
3.302.79
3.02.7
2.62.2
0.70.4
15.815.2
0.90.7
1.31.0
4.54.1
1.391.27
6.45.9
10.39.7
L1E L
97-06-11
August 1999 7 Rev 1.100
Philips Semiconductors Product specification
N-channel TrenchMOS transistor IRF540, IRF540S
MECHANICAL DATA
Fig.16. SOT404 surface mounting package. Centre pin connected to mounting base.
Notes1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.3. Epoxy meets UL94 V0 at 1/8".
UNIT A
REFERENCESOUTLINEVERSION
EUROPEANPROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm
A1 D1D
max.E e Lp HD Qc
2.54 2.602.20
15.4014.80
2.902.10
11 1.601.20
10.309.70
4.504.10
1.401.27
0.850.60
0.640.46
b
DIMENSIONS (mm are the original dimensions)
SOT404
0 2.5 5 mm
scale
Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads(one lead cropped) SOT404
e e
E
b
D1
HD
D
Q
Lp
c
A1
A
1 3
2
mountingbase
98-12-1499-06-25
August 1999 8 Rev 1.100
Max Zener Impedance Max Reverse Leakage Current
Max Zener Voltage
Temp. Coeff
– 0.085– 0.085– 0.080– 0.080– 0.075– 0.070– 0.065– 0.060± 0.055± 0.030± 0.030+ 0.038+ 0.038+ 0.045+ 0.050
Prelim. 1/99
1N5221B-LCC3 TOB-LCC
1N5281B-LCC3
Semelab plc. Telephone +44(0)1455 556565. Fax +44(0)1455 552612.E-mail: [email protected] Website: http://www.semelab.co.uk
ZENER VOLTAGE REGULATORDIODE IN HERMETIC CERAMIC
SURFACE MOUNT PACKAGEFOR HIGH RELIABILITY
APPLICATIONS
Tcase Operating temperature Range
Tstg Storage Temperature Range
PTOT Power Dissipation TA = 25°C
RTHJ-A Thermal resistance (Junction to Ambient)
-55 to +175°C
-65 to +175°C
500mW
300°C/W
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS @ 25°C
FEATURES
• Military Screening Options available
MECHANICAL DATADimensions in mm (inches)
1
23
4
5.59 ± 0.13(0.22 ± 0.005)
0.23(0.009) rad.
1.02 ± 0.20(0.04 ± 0.008)
2.03 ± 0.20(0.08 ± 0.008)
1.40 ± 0.15(0.055 ± 0.006)
0.25 ± 0.03(0.01 ± 0.001)
0.23(0.009) min.1.
27 ±
0.0
5(0
.05
± 0.
002)
3.81
± 0
.13
(0.1
5 ±
0.00
5)
0.64
± 0
.08
(0.0
25 ±
0.0
03)
1 = CATHODE 2 = N/C 3 = N/C 4 = ANODE
Nominal
Zener Voltage
Vz @ IZT
Volts
2.42.52.72.83.03.33.63.94.34.75.15.66.06.26.8
ZZT @ IZT
Ohms
3030303029282423221917117.07.05.0
ZZK @ IZK = 0.25mA
Ohms
12001250130014001600160017001900200019001600160016001000750
IR
mmmmA
1001007575502515105.05.05.05.05.05.03.0
VR Volts
B, C & D
1.01.01.01.01.01.01.01.01.02.02.03.03.54.05.0
@
A
0.950.950.950.950.950.950.950.950.951.91.92.93.33.84.8
Test
Current
IZT
mA
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
Part No.
1N52211N52221N52231N52241N52251N52261N52271N52281N52291N52301N52311N52321N52331N52341N5235
Prelim. 1/99
1N5221B-LCC3 TOB-LCC
1N5281B-LCC3
Semelab plc. Telephone +44(0)1455 556565. Fax +44(0)1455 552612.E-mail: [email protected] Website: http://www.semelab.co.uk
Max Zener Impedance Max Reverse Leakage Current
Max Zener Voltage
Temp. Coeff
+ 0.058+ 0.062+ 0.065+ 0.068+ 0.075+ 0.076+ 0.077+ 0.079+ 0.082+ 0.082+ 0.083+ 0.084+ 0.085+ 0.086+ 0.086+ 0.087+ 0.088+ 0.089+ 0.090+ 0.091+ 0.091+ 0.092+ 0.093+ 0.094+ 0.095+ 0.095+ 0.096+ 0.096+ 0.097+ 0.097+ 0.097+ 0.098+ 0.098+ 0.099+ 0.099+ 0.110+ 0.110+ 0.110+ 0.110+ 0.110+ 0.110+ 0.110+ 0.110+ 0.110+ 0.110+ 0.110
Nominal
Zener Voltage
Vz @ IZT
Volts
7.58.28.79.110111213141516171819202224252728303336394347515660626875828791100110120130140150160170180190200
ZZT @ IZT
Ohms
6.08.08.01017223013151617192123252933354144495870809310512515017018523027033037040050075090011001300150017001900220024002500
ZZK @ IZK = 0.25mA
Ohms
500500600600600600600600600600600600600600600600600600600600600700700800900
100011001300140014001600170020002200230026003000400045004500500055005500600065007000
IR
mmmmA
3.03.03.03.03.02.01.00.50.10.10.10.10.10.10.10.10.10.10.10.10.10.10.10.10.10.10.10.10.10.10.10.10.10.10.10.10.10.10.10.10.10.10.10.10.10.1
VR Volts
B, C & D6.06.56.57.08.08.49.19.910111213141415171819212123252730333639434647525662686976849199
106114122129137144152
@
A
5.76.26.26.77.68.08.79.49.5
10.511.412.413.313.314.316.217.118.1202022242629313437414445495359656672808694101108116123130137144
Test
Current
IZT
mA
20
20
20
20
20
20
20
9.5
9.0
8.5
7.8
7.4
7.0
6.6
6.2
5.6
5.2
5.0
4.6
4.5
4.2
3.8
3.4
3.2
3.0
2.7
2.5
2.2
2.1
2.0
1.8
1.7
1.5
1.4
1.4
1.3
1.1
1.0
0.95
0.90
0.85
0.80
0.74
0.68
0.66
0.65
Part No.
1N52361N52371N52381N52391N52401N52411N52421N52431N52441N52451N52461N52471N52481N52491N52501N52511N52521N52531N52541N52551N52561N52571N52581N52591N52601N52611N52621N52631N52641N52651N52661N52671N52681N52691N52701N52711N52721N52731N52741N52751N52761N52771N52781N52791N52801N5281
ELECTRICAL CHARACTERISTICS @ 25°C continued
1/9
MAXIMUM INPUT CURRENT : 150nA
MAXIMUM OFFSET CURRENT : 20nA
DIFFERENTIAL INPUT VOLTAGE RANGE : ±30V
POWER CONSUMPTION :135mW AT ±15V
SUPPLY VOLTAGE : +5V TO ±15V
OUTPUT CURRENT : 50mA
DESCRIPTION
The LM111, LM211, LM311 are voltage compara-tors that have low input currents.
They are also designed to operate over a widerange of supply voltages : from standard ±15V op-erational amplifier supplies down to the single +5Vsupply used for IC logic.
Their output is compatible with RTL-DTL and TTLas well as MOS circuits and can switch voltagesup to +50V at outputs currents as high as 50mA.
ORDER CODE
N = Dual in Line Package (DIP)D = Small Outline Package (SO) - also available in Tape & Reel (DT)
PIN CONNECTIONS (top view)
Part Number Temperature Range
Package
N D
LM111 -55°C, +125°C • •LM211 -40°C, +105°C • •LM311 0°C, +70°C • •Example : LM311D
DSO8
NDIP8
1
2
3
4
8
7
6
5
1 - Ground2 - Non-inverting input3 - Inverting input4 - VCC
-
5 - Balance6 - Strobe/Balance7 - Output
8 - VCC+
LM111 LM211 - LM311
VOLTAGE COMPARATORS
June 2002
LM111-LM211-LM311
2/9
SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
OPERATING CONDITIONS
Symbol Parameter Value Unit
VCC Supply Voltage 36 V
Vid Differential Input Voltage ±30 V
Vi Input Voltage 1)
1. This rating applies for ±15V supplies. The positive input voltage limit is 30V above the negative. The negative input voltage is equal to thenegative supply voltage or 30V below the positive supply, whichever is less.
±15 V
V(1-4) Ground to Negative Supply Voltage 30 V
V(7-4)Output to Negative Supply Voltage LM111-LM211
LM3115040
V
Output Short-Circuit Duration 10 s
Voltage at strobe pin VCC+ -5 V
pdPower Dissipation 2) DIP8
SO8
2. Pd is calculated with Tamb = +25°C, Tj = +150°C and Rthja = 100°C/W for DIP8 package= 175°C/W for SO8 package
1250710
mW
Tj Junction Temperature +150 °C
Tstg Storage Temperature Range -65 to +150 °C
Symbol Parameter Value Unit
VCC Supply Voltage 5 to ±15 V
Toper
Operating Free-Air Temperature range LM111 LM211 LM311
-55 to +125-40 to +105
0 to +70°C
LM111-LM211-LM311
3/9
ELECTRICAL CHARACTERISTICSVCC
+ = ±15V, Tamb = +25°C (unless otherwise specified)
Symbol ParameterLM111 - LM211 LM311
UnitMin. Typ. Max. Min. Typ. Max.
Vio
Input Offset Voltage (RS ≤ 50kΩ)- note 1) Tamb = +25°CTmin ≤ Tamb ≤ Tmax
1. The offset voltage, offset current and bias current specifications apply for any supply voltage from a single +5V suplly up to ±15VsuppliesThe offset voltages and offset currents given are the maximum values required to drive the output down to +1V or up to +14V with a1mA load current. Thus, these parameters define an error band and take into account the worst-case of voltage gain and input impedance.
0.7 34
2 7.510
mV
Iio
Input Offset Current -(see note 1) Tamb = +25°CTmin ≤ Tamb ≤ Tmax
4 1020
6 5070
nA
Iib
Input Bias Current - (see note 1 )Tamb = +25°CTmin ≤ Tamb ≤ Tmax
60 100150
100 250300
nA
Avd Large Signal Voltage Gain 40 200 40 200 V/mV
ICC+
ICC-
Supply Currents Positive Negative
5.14.1
65
5.14.1
7.55
mA
VicmInput Common Mode Voltage Range
Tmin ≤ Tamb ≤ Tmax
-14.5 +13.8-14.7
+13 -14.5 +13.8-14.7
+13 V
VOL
Low Level Output VoltageTamb = +25°C, IO = 50mA Vi ≤ -5mV
Vi ≤ -10mVTmin ≤ Tamb ≤ Tmax
VCC+ ≥ +4.5V, VCC
- = 0IO = 8mA Vi ≤ -6m
Vi ≤ -10mV
0.75
0.23
1.5
0.4
0.75
0.23
1.5
0.4
V
IOH
High Level Output Current Tamb = +25°C Vi ≥ +5mV,Vo = +35V Vi ≥ +10mV,Vo = +5VTmin ≤ Tamb ≤ Tmax Vi ≥ +5mV,Vo = +35V
0.2
0.1
10
0.50.2 50
nAnAµA
Istrobe Strobe Current 3 3 mA
tre Response Time - note 2)
2. The response time specified (see definitions) is for a 100mV input step with 5mV overdrive.
200 200 ns
LM111-LM211-LM311
4/9
LM111-LM211-LM311
5/9
LM111-LM211-LM311
6/9
LM111-LM211-LM311
7/9
LM111-LM211-LM311
8/9
PACKAGE MECHANICAL DATA8 PINS - PLASTIC DIP
DimensionsMillimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 3.32 0.131
a1 0.51 0.020
B 1.15 1.65 0.045 0.065
b 0.356 0.55 0.014 0.022
b1 0.204 0.304 0.008 0.012
D 10.92 0.430
E 7.95 9.75 0.313 0.384
e 2.54 0.100
e3 7.62 0.300
e4 7.62 0.300
F 6.6 0260
i 5.08 0.200
L 3.18 3.81 0.125 0.150
Z 1.52 0.060
LM111-LM211-LM311
9/9
PACKAGE MECHANICAL DATA8 PINS - PLASTIC MICROPACKAGE (SO)
DimensionsMillimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 1.75 0.069
a1 0.1 0.25 0.004 0.010
a2 1.65 0.065
a3 0.65 0.85 0.026 0.033
b 0.35 0.48 0.014 0.019
b1 0.19 0.25 0.007 0.010
C 0.25 0.5 0.010 0.020
c1 45° (typ.)
D 4.8 5.0 0.189 0.197
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 3.81 0.150
F 3.8 4.0 0.150 0.157
L 0.4 1.27 0.016 0.050
M 0.6 0.024
S 8° (max.)
b
e3
Aa2
s
L
C
E
c1
a3b1a1
DM
8 5
1 4F
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for theconsequences of use of such information nor for any infringement of patents or other rights of third parties which may result fromits use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specificationsmentioned in this publication are subject to change without notice. This publication supersedes and replaces all informationpreviously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices orsystems without express written approval of STMicroelectronics.
© The ST logo is a registered trademark of STMicroelectronics
© 2002 STMicroelectronics - Printed in Italy - All Rights ReservedSTMicroelectronics GROUP OF COMPANIES
Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - MalaysiaMalta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States
© http://www.st.com
1
Data sheet acquired from Harris SemiconductorSCHS117E
Features
• Buffered Inputs
• Typical Propagation Delay: 6ns at VCC = 5V,CL = 15pF, TA = 25oC
• Fanout (Over Temperature Range)- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTLLogic ICs
• HC Types- 2-V to 6-V Operation- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types- 4.5-V to 5.5-V Operation- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
Description
The CD54HC04, CD54HCT04, CD74HC04 andCD74HCT04 logic gates utilize silicon-gate CMOStechnology to achieve operating speeds similar to LSTTLgates, with the low power consumption of standard CMOSintegrated circuits. All devices have the ability to drive 10LSTTL loads. The 74HCT logic family functionally is pincompatible with the standard 74LS logic family.
PinoutCD54HC04, CD54HCT04 (CERDIP)
CD74HC04 (PDIP, SOIC)CD74HCT04 (PDIP, SOIC, TSSOP)
TOP VIEW
Ordering Information
PART NUMBERTEMP. RANGE
(oC) PACKAGE
CD54HC04F3A -55 to 125 14 Ld CERDIP
CD54HCT04F3A -55 to 125 14 Ld CERDIP
CD74HC04E -55 to 125 14 Ld PDIP
CD74HC04M -55 to 125 14 Ld SOIC
CD74HC04MT -55 to 125 14 Ld SOIC
CD74HC04M96 -55 to 125 14 Ld SOIC
CD74HCT04E -55 to 125 14 Ld PDIP
CD74HCT04M -55 to 125 14 Ld SOIC
CD74HCT04MT -55 to 125 14 Ld SOIC
CD74HCT04M96 -55 to 125 14 Ld SOIC
CD74HCT04PWR -55 to 125 14 Ld TSSOP
NOTE: When ordering, use the entire part number. The suffixes96 and R denote tape and reel. The suffix T denotes asmall-quantity reel of 250.
1A
1Y
2A
2Y
3A
3Y
GND
VCC
6A
6Y
5A
5Y
4A
4Y
1
2
3
4
5
6
7
14
13
12
11
10
9
8
August 1997 - Revised June 2004
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2004, Texas Instruments Incorporated
CD54HC04, CD74HC04,CD54HCT04, CD74HCT04
High-Speed CMOS Logic Hex Inverter
[ /Title(CD54HC04,CD54HCT04,CD74HC04,CD74HCT04)/Subject(HighSpeed
2
Functional Diagram
Logic Symbol
TRUTH TABLE
INPUTS
nA nY
L H
H L
H = High Voltage Level, L = Low Voltage Level
1A
1Y
2Y
3A
3Y
GND
1
2
3
4
5
6
14
13
12
11
VCC
5A
4Y
5Y
6Y
6A
10
87
94A
2A
nA nY
CD54HC04, CD74HC04, CD54HCT04, CD74HCT04
3
Absolute Maximum Ratings Thermal InformationDC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7VDC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mADC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mADC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mADC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Operating ConditionsTemperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oCSupply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6VHCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCCInput Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 1) θJA (oC/W)E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Maximum Junction Temperature (Hermetic Package or Die) . . . 175oCMaximum Junction Temperature (Plastic Package) . . . . . . . . 150oCMaximum Storage Temperature Range . . . . . . . . . .-65oC to 150oCMaximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating, and operationof the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER SYMBOL
TESTCONDITIONS
VCC (V)
25oC -40oC TO +85oC -55oC TO 125oC
UNITSVI (V) IO (mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level InputVoltage
VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level InputVoltage
VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level OutputVoltageCMOS Loads
VOH VIH orVIL
-0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level OutputVoltageTTL Loads
- - - - - - - - - V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level OutputVoltageCMOS Loads
VOL VIH orVIL
0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level OutputVoltageTTL Loads
- - - - - - - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input LeakageCurrent
II VCC orGND
- 6 - - ±0.1 - ±1 - ±1 µA
CD54HC04, CD74HC04, CD54HCT04, CD74HCT04
4
Quiescent DeviceCurrent
ICC VCC orGND
0 6 - - 2 - 20 - 40 µA
HCT TYPES
High Level InputVoltage
VIH - - 4.5 to5.5
2 - - 2 - 2 - V
Low Level InputVoltage
VIL - - 4.5 to5.5
- - 0.8 - 0.8 - 0.8 V
High Level OutputVoltageCMOS Loads
VOH VIH orVIL
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level OutputVoltageTTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
Low Level OutputVoltageCMOS Loads
VOL VIH orVIL
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level OutputVoltageTTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
Input LeakageCurrent
II VCCandGND
0 5.5 - ±0.1 - ±1 - ±1 µA
Quiescent DeviceCurrent
ICC VCC orGND
0 5.5 - - 2 - 20 - 40 µA
Additional QuiescentDevice Current PerInput Pin: 1 Unit Load
∆ICC(Note 2)
VCC- 2.1
- 4.5 to5.5
- 100 360 - 450 - 490 µA
NOTE:
2. For dual-supply systems, theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TESTCONDITIONS
VCC (V)
25oC -40oC TO +85oC -55oC TO 125oC
UNITSVI (V) IO (mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
nB 1.2
NOTE: Unit Load is ∆ICC limit specified in DC ElectricalSpecifications table, e.g. 360µA max at 25oC.
Switching Specifications Input tr, tf = 6ns
PARAMETER SYMBOLTEST
CONDITIONSVCC(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation Delay,Input to Output (Figure 1)
tPLH, tPHL CL = 50pF 2 - - 85 - 105 - 130 ns
4.5 - - 17 - 21 - 26 ns
6 - - 14 - 18 - 22 ns
Propagation Delay, Data Input toOutput Y
tPLH, tPHL CL = 15pF 5 - 6 - - - - - ns
CD54HC04, CD74HC04, CD54HCT04, CD74HCT04
5
Transition Times (Figure 1) tTLH, tTHL CL = 50pF 2 - - 75 - 95 18 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Input Capacitance CI - - - - 10 - 10 - 10 pF
Power Dissipation Capacitance(Notes 3, 4)
CPD - 5 - 21 - - - - - pF
HCT TYPES
Propagation Delay, Input toOutput (Figure 2)
tPLH, tPHL CL = 50pF 4.5 - - 19 - 24 - 29 ns
Propagation Delay, Data Input toOutput Y
tPLH, tPHL CL = 15pF 5 - 7 - - - - - ns
Transition Times (Figure 2) tTLH, tTHL CL = 50pF 4.5 - - 15 - 19 - 22 ns
Input Capacitance CI - - - - 10 - 10 - 10 pF
Power Dissipation Capacitance(Notes 3, 4)
CPD - 5 - 24 - - - - - pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per gate.
4. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER SYMBOLTEST
CONDITIONSVCC(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
Test Circuits and Waveforms
FIGURE 1. HC TRANSITION TIMES AND PROPAGATIONDELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATIONDELAY TIMES, COMBINATION LOGIC
tPHL tPLH
tTHL tTLH
90%50%10%
50%10%INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns tf = 6ns
90%
tPHL tPLH
tTHL tTLH
2.7V1.3V0.3V
1.3V10%INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns tf = 6ns
90%
CD54HC04, CD74HC04, CD54HTC04, CD74HCT04
PACKAGING INFORMATION
Orderable Device Status (1) PackageType
PackageDrawing
Pins PackageQty
Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CD54HC04F ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC
CD54HC04F3A ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC
CD54HCT04F ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC
CD54HCT04F3A ACTIVE CDIP J 14 1 None Call TI Level-NC-NC-NC
CD74HC04E ACTIVE PDIP N 14 25 Pb-Free(RoHS)
CU NIPDAU Level-NC-NC-NC
CD74HC04M ACTIVE SOIC D 14 50 Pb-Free(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/Level-1-235C-UNLIM
CD74HC04M96 ACTIVE SOIC D 14 2500 Pb-Free(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/Level-1-235C-UNLIM
CD74HC04MT ACTIVE SOIC D 14 250 Pb-Free(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/Level-1-235C-UNLIM
CD74HCT04E ACTIVE PDIP N 14 25 Pb-Free(RoHS)
CU NIPDAU Level-NC-NC-NC
CD74HCT04M ACTIVE SOIC D 14 50 Pb-Free(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/Level-1-235C-UNLIM
CD74HCT04M96 ACTIVE SOIC D 14 2500 Pb-Free(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/Level-1-235C-UNLIM
CD74HCT04MT ACTIVE SOIC D 14 250 Pb-Free(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/Level-1-235C-UNLIM
CD74HCT04PWR ACTIVE TSSOP PW 14 2000 Pb-Free(RoHS)
CU NIPDAU Level-1-250C-UNLIM
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part ina new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additionalproduct content details.None: Not yet available Lead (Pb-Free).Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirementsfor all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be solderedat high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak soldertemperature.
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PACKAGE OPTION ADDENDUM
www.ti.com 28-Feb-2005
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE14 PINS SHOWN
0,65 M0,10
0,10
0,25
0,500,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,606,20
8
0,19
4,304,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIMPINS **
0,05
4,90
5,10
Seating Plane
0°–8°
NOTES: A. All linear dimensions are in millimeters.B. This drawing is subject to change without notice.C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.D. Falls within JEDEC MO-153
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Copyright 2005, Texas Instruments Incorporated
©2001 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.1
Features• Output Current up to 1A • Output Voltages of 5, 6, 8, 9, 10, 12, 15, 18, 24V • Thermal Overload Protection • Short Circuit Protection• Output Transistor Safe Operating Area Protection
DescriptionThe MC78XX/LM78XX/MC78XXA series of three terminal positive regulators are available in the TO-220/D-PAK package and with several fixed output voltages, making them useful in a wide range of applications. Each type employs internal current limiting,thermal shut down and safe operating area protection, making it essentially indestructible. If adequate heat sinkingis provided, they can deliver over 1A output current.Although designed primarily as fixed voltage regulators,these devices can be used with external components toobtain adjustable voltages and currents.
TO-220
D-PAK
1. Input 2. GND 3. Output
1
1
Internal Block Digram
MC78XX/LM78XX/MC78XXA3-Terminal 1A Positive Voltage Regulator
MC78XX/LM78XX/MC78XXA
2
Absolute Maximum Ratings
Electrical Characteristics (MC7805/LM7805)(Refer to test circuit ,0°C < TJ < 125°C, IO = 500mA, VI = 10V, CI= 0.33µF, CO= 0.1µF, unless otherwise specified)
Note:1. Load and line regulation are specified at constant junction temperature. Changes in Vo due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
Parameter Symbol Value UnitInput Voltage (for VO = 5V to 18V)(for VO = 24V)
VIVI
3540
VV
Thermal Resistance Junction-Cases (TO-220) RθJC 5 oC/WThermal Resistance Junction-Air (TO-220) RθJA 65 oC/WOperating Temperature Range TOPR 0 ~ +125 oCStorage Temperature Range TSTG -65 ~ +150 oC
Parameter Symbol ConditionsMC7805/LM7805
UnitMin. Typ. Max.
Output Voltage VOTJ =+25 oC 4.8 5.0 5.25.0mA ≤ Io ≤ 1.0A, PO ≤ 15WVI = 7V to 20V 4.75 5.0 5.25 V
Line Regulation (Note1) Regline TJ=+25 oCVO = 7V to 25V - 4.0 100
mVVI = 8V to 12V - 1.6 50
Load Regulation (Note1) Regload TJ=+25 oCIO = 5.0mA to1.5A - 9 100
mVIO =250mA to 750mA - 4 50
Quiescent Current IQ TJ =+25 oC - 5.0 8.0 mA
Quiescent Current Change ∆IQIO = 5mA to 1.0A - 0.03 0.5
mAVI= 7V to 25V - 0.3 1.3
Output Voltage Drift ∆VO/∆T IO= 5mA - -0.8 - mV/ oCOutput Noise Voltage VN f = 10Hz to 100KHz, TA=+25 oC - 42 - µV/Vo
Ripple Rejection RR f = 120HzVO = 8V to 18V 62 73 - dB
Dropout Voltage VDrop IO = 1A, TJ =+25 oC - 2 - VOutput Resistance rO f = 1KHz - 15 - mΩShort Circuit Current ISC VI = 35V, TA =+25 oC - 230 - mAPeak Current IPK TJ =+25 oC - 2.2 - A
MC78XX/LM78XX/MC78XXA
3
Electrical Characteristics (MC7806)(Refer to test circuit ,0°C < TJ < 125°C, IO = 500mA, VI =11V, CI= 0.33µF, CO= 0.1µF, unless otherwise specified)
Note:1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
Parameter Symbol ConditionsMC7806
UnitMin. Typ. Max.
Output Voltage VOTJ =+25 oC 5.75 6.0 6.255.0mA ≤ IO ≤ 1.0A, PO ≤ 15WVI = 8.0V to 21V 5.7 6.0 6.3 V
Line Regulation (Note1) Regline TJ =+25 oCVI = 8V to 25V - 5 120
mVVI = 9V to 13V - 1.5 60
Load Regulation (Note1) Regload TJ =+25 oCIO =5mA to 1.5A - 9 120
mVIO =250mA to750A - 3 60
Quiescent Current IQ TJ =+25 oC - 5.0 8.0 mA
Quiescent Current Change ∆IQIO = 5mA to 1A - - 0.5
mAVI = 8V to 25V - - 1.3
Output Voltage Drift ∆VO/∆T IO = 5mA - -0.8 - mV/ oCOutput Noise Voltage VN f = 10Hz to 100KHz, TA =+25 oC - 45 - µV/Vo
Ripple Rejection RR f = 120HzVI = 9V to 19V 59 75 - dB
Dropout Voltage VDrop IO = 1A, TJ =+25 oC - 2 - VOutput Resistance rO f = 1KHz - 19 - mΩShort Circuit Current ISC VI= 35V, TA=+25 oC - 250 - mAPeak Current IPK TJ =+25 oC - 2.2 - A
MC78XX/LM78XX/MC78XXA
4
Electrical Characteristics (MC7808)(Refer to test circuit ,0°C < TJ < 125°C, IO = 500mA, VI =14V, CI= 0.33µF, CO= 0.1µF, unless otherwise specified)
Note:1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
Parameter Symbol ConditionsMC7808
UnitMin. Typ. Max.
Output Voltage VOTJ =+25 oC 7.7 8.0 8.35.0mA ≤ IO ≤ 1.0A, PO ≤ 15WVI = 10.5V to 23V 7.6 8.0 8.4 V
Line Regulation (Note1) Regline TJ =+25 oCVI = 10.5V to 25V - 5.0 160
mVVI = 11.5V to 17V - 2.0 80
Load Regulation (Note1) Regload TJ =+25 oCIO = 5.0mA to 1.5A - 10 160
mVIO= 250mA to 750mA - 5.0 80
Quiescent Current IQ TJ =+25 oC - 5.0 8.0 mA
Quiescent Current Change ∆IQIO = 5mA to 1.0A - 0.05 0.5
mAVI = 10.5A to 25V - 0.5 1.0
Output Voltage Drift ∆VO/∆T IO = 5mA - -0.8 - mV/ oCOutput Noise Voltage VN f = 10Hz to 100KHz, TA =+25 oC - 52 - µV/VoRipple Rejection RR f = 120Hz, VI= 11.5V to 21.5V 56 73 - dBDropout Voltage VDrop IO = 1A, TJ=+25 oC - 2 - VOutput Resistance rO f = 1KHz - 17 - mΩShort Circuit Current ISC VI= 35V, TA =+25 oC - 230 - mAPeak Current IPK TJ =+25 oC - 2.2 - A
MC78XX/LM78XX/MC78XXA
5
Electrical Characteristics (MC7809)(Refer to test circuit ,0°C < TJ < 125°C, IO = 500mA, VI =15V, CI= 0.33µF, CO= 0.1µF, unless otherwise specified)
Note:1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
Parameter Symbol ConditionsMC7809
UnitMin. Typ. Max.
Output Voltage VOTJ =+25°C 8.65 9 9.355.0mA≤ IO ≤1.0A, PO ≤15WVI= 11.5V to 24V 8.6 9 9.4 V
Line Regulation (Note1) Regline TJ=+25°CVI = 11.5V to 25V - 6 180
mVVI = 12V to 17V - 2 90
Load Regulation (Note1) Regload TJ=+25°CIO = 5mA to 1.5A - 12 180
mVIO = 250mA to 750mA - 4 90
Quiescent Current IQ TJ=+25°C - 5.0 8.0 mA
Quiescent Current Change ∆IQIO = 5mA to 1.0A - - 0.5
mAVI = 11.5V to 26V - - 1.3
Output Voltage Drift ∆VO/∆T IO = 5mA - -1 - mV/ °COutput Noise Voltage VN f = 10Hz to 100KHz, TA =+25 °C - 58 - µV/VoRipple Rejection RR f = 120Hz
VI = 13V to 23V 56 71 - dB
Dropout Voltage VDrop IO = 1A, TJ=+25°C - 2 - VOutput Resistance rO f = 1KHz - 17 - mΩShort Circuit Current ISC VI= 35V, TA =+25°C - 250 - mAPeak Current IPK TJ= +25°C - 2.2 - A
MC78XX/LM78XX/MC78XXA
6
Electrical Characteristics (MC7810)(Refer to test circuit ,0°C< TJ < 125°C, IO = 500mA, VI =16V, CI= 0.33µF, CO=0.1µF, unless otherwise specified)
Note:1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
Parameter Symbol ConditionsMC7810
UnitMin. Typ. Max.
Output Voltage VOTJ =+25 °C 9.6 10 10.45.0mA ≤ IO≤1.0A, PO ≤15WVI = 12.5V to 25V 9.5 10 10.5 V
Line Regulation (Note1) Regline TJ =+25°CVI = 12.5V to 25V - 10 200
mVVI = 13V to 25V - 3 100
Load Regulation (Note1) Regload TJ =+25°CIO = 5mA to 1.5A - 12 200
mVIO = 250mA to 750mA - 4 400
Quiescent Current IQ TJ =+25°C - 5.1 8.0 mA
Quiescent Current Change ∆IQIO = 5mA to 1.0A - - 0.5
mAVI = 12.5V to 29V - - 1.0
Output Voltage Drift ∆VO/∆T IO = 5mA - -1 - mV/°COutput Noise Voltage VN f = 10Hz to 100KHz, TA =+25 °C - 58 - µV/Vo
Ripple Rejection RR f = 120HzVI = 13V to 23V 56 71 - dB
Dropout Voltage VDrop IO = 1A, TJ=+25 °C - 2 - VOutput Resistance rO f = 1KHz - 17 - mΩShort Circuit Current ISC VI = 35V, TA=+25 °C - 250 - mAPeak Current IPK TJ =+25 °C - 2.2 - A
MC78XX/LM78XX/MC78XXA
7
Electrical Characteristics (MC7812)(Refer to test circuit ,0°C < TJ < 125°C, IO = 500mA, VI =19V, CI= 0.33µF, CO=0.1µF, unless otherwise specified)
Note:1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
Parameter Symbol ConditionsMC7812
UnitMin. Typ. Max.
Output Voltage VOTJ =+25 oC 11.5 12 12.55.0mA ≤ IO≤1.0A, PO≤15WVI = 14.5V to 27V 11.4 12 12.6 V
Line Regulation (Note1) Regline TJ =+25 oCVI = 14.5V to 30V - 10 240
mVVI = 16V to 22V - 3.0 120
Load Regulation (Note1) Regload TJ =+25 oCIO = 5mA to 1.5A - 11 240
mVIO = 250mA to 750mA - 5.0 120
Quiescent Current IQ TJ =+25 oC - 5.1 8.0 mA
Quiescent Current Change ∆IQIO = 5mA to 1.0A - 0.1 0.5
mAVI = 14.5V to 30V - 0.5 1.0
Output Voltage Drift ∆VO/∆T IO = 5mA - -1 - mV/ oCOutput Noise Voltage VN f = 10Hz to 100KHz, TA =+25 oC - 76 - µV/Vo
Ripple Rejection RR f = 120HzVI = 15V to 25V 55 71 - dB
Dropout Voltage VDrop IO = 1A, TJ=+25 oC - 2 - VOutput Resistance rO f = 1KHz - 18 - mΩShort Circuit Current ISC VI = 35V, TA=+25 oC - 230 - mAPeak Current IPK TJ = +25 oC - 2.2 - A
MC78XX/LM78XX/MC78XXA
8
Electrical Characteristics (MC7815)(Refer to test circuit ,0°C < TJ < 125°C, IO = 500mA, VI =23V, CI= 0.33µF, CO=0.1µF, unless otherwise specified)
Note:1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
Parameter Symbol ConditionsMC7815
UnitMin. Typ. Max.
Output Voltage VOTJ =+25 oC 14.4 15 15.65.0mA ≤ IO ≤ 1.0A, PO ≤ 15WVI = 17.5V to 30V 14.25 15 15.75 V
Line Regulation (Note1) Regline TJ =+25 oCVI = 17.5V to 30V - 11 300
mVVI = 20V to 26V - 3 150
Load Regulation (Note1) Regload TJ =+25 oCIO = 5mA to 1.5A - 12 300
mVIO = 250mA to 750mA - 4 150
Quiescent Current IQ TJ =+25 oC - 5.2 8.0 mA
Quiescent Current Change ∆IQIO = 5mA to 1.0A - - 0.5
mAVI = 17.5V to 30V - - 1.0
Output Voltage Drift ∆VO/∆T IO = 5mA - -1 - mV/ oCOutput Noise Voltage VN f = 10Hz to 100KHz, TA =+25 oC - 90 - µV/Vo
Ripple Rejection RR f = 120HzVI = 18.5V to 28.5V 54 70 - dB
Dropout Voltage VDrop IO = 1A, TJ=+25 oC - 2 - VOutput Resistance rO f = 1KHz - 19 - mΩShort Circuit Current ISC VI = 35V, TA=+25 oC - 250 - mAPeak Current IPK TJ =+25 oC - 2.2 - A
MC78XX/LM78XX/MC78XXA
9
Electrical Characteristics (MC7818)(Refer to test circuit ,0°C < TJ < 125°C, IO = 500mA, VI =27V, CI= 0.33µF, CO=0.1µF, unless otherwise specified)
Note:1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
Parameter Symbol ConditionsMC7818
UnitMin. Typ. Max.
Output Voltage VOTJ =+25 oC 17.3 18 18.75.0mA ≤ IO ≤1.0A, PO ≤15WVI = 21V to 33V 17.1 18 18.9 V
Line Regulation (Note1) Regline TJ =+25 oCVI = 21V to 33V - 15 360
mVVI = 24V to 30V - 5 180
Load Regulation (Note1) Regload TJ =+25 oCIO = 5mA to 1.5A - 15 360
mVIO = 250mA to 750mA - 5.0 180
Quiescent Current IQ TJ =+25 oC - 5.2 8.0 mA
Quiescent Current Change ∆IQIO = 5mA to 1.0A - - 0.5
mAVI = 21V to 33V - - 1
Output Voltage Drift ∆VO/∆T IO = 5mA - -1 - mV/ oCOutput Noise Voltage VN f = 10Hz to 100KHz, TA =+25 oC - 110 - µV/Vo
Ripple Rejection RR f = 120HzVI = 22V to 32V 53 69 - dB
Dropout Voltage VDrop IO = 1A, TJ=+25 oC - 2 - VOutput Resistance rO f = 1KHz - 22 - mΩShort Circuit Current ISC VI = 35V, TA=+25 oC - 250 - mAPeak Current IPK TJ =+25 oC - 2.2 - A
MC78XX/LM78XX/MC78XXA
10
Electrical Characteristics (MC7824)(Refer to test circuit ,0°C < TJ < 125°C, IO = 500mA, VI =33V, CI= 0.33µF, CO=0.1µF, unless otherwise specified)
Note:1. Load and line regulation are specified at constant junction temperature. Changes in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
Parameter Symbol ConditionsMC7824
UnitMin. Typ. Max.
Output Voltage VOTJ =+25 oC 23 24 255.0mA ≤ IO ≤ 1.0A, PO ≤ 15WVI = 27V to 38V 22.8 24 25.25 V
Line Regulation (Note1) Regline TJ =+25 oCVI = 27V to 38V - 17 480
mVVI = 30V to 36V - 6 240
Load Regulation (Note1) Regload TJ =+25 oCIO = 5mA to 1.5A - 15 480
mVIO = 250mA to 750mA - 5.0 240
Quiescent Current IQ TJ =+25 oC - 5.2 8.0 mA
Quiescent Current Change ∆IQIO = 5mA to 1.0A - 0.1 0.5
mAVI = 27V to 38V - 0.5 1
Output Voltage Drift ∆VO/∆T IO = 5mA - -1.5 - mV/ oCOutput Noise Voltage VN f = 10Hz to 100KHz, TA =+25 oC - 60 - µV/Vo
Ripple Rejection RR f = 120HzVI = 28V to 38V 50 67 - dB
Dropout Voltage VDrop IO = 1A, TJ=+25 oC - 2 - VOutput Resistance rO f = 1KHz - 28 - mΩShort Circuit Current ISC VI = 35V, TA=+25 oC - 230 - mAPeak Current IPK TJ =+25 oC - 2.2 - A
MC78XX/LM78XX/MC78XXA
11
Electrical Characteristics (MC7805A)(Refer to the test circuits. 0°C < TJ < 125°C, Io =1A, V I = 10V, C I=0.33µF, C O=0.1µF, unless otherwise specified)
Note:1. Load and line regulation are specified at constant junction temperature. Change in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
Parameter Symbol Conditions Min. Typ. Max. Unit
Output Voltage VOTJ =+25 oC 4.9 5 5.1
VIO = 5mA to 1A, PO ≤ 15WVI = 7.5V to 20V 4.8 5 5.2
Line Regulation (Note1) Regline
VI = 7.5V to 25VIO = 500mA - 5 50
mVVI = 8V to 12V - 3 50
TJ =+25 oCVI= 7.3V to 20V - 5 50VI= 8V to 12V - 1.5 25
Load Regulation (Note1) Regload
TJ =+25 oCIO = 5mA to 1.5A - 9 100
mVIO = 5mA to 1A - 9 100IO = 250mA to 750mA - 4 50
Quiescent Current IQ TJ =+25 oC - 5.0 6 mA
Quiescent Current Change ∆IQ
IO = 5mA to 1A - - 0.5mAVI = 8 V to 25V, IO = 500mA - - 0.8
VI = 7.5V to 20V, TJ =+25 oC - - 0.8Output Voltage Drift ∆V/∆T Io = 5mA - -0.8 - mV/ oC
Output Noise Voltage VNf = 10Hz to 100KHzTA =+25 oC - 10 - µV/Vo
Ripple Rejection RR f = 120Hz, IO = 500mAVI = 8V to 18V - 68 - dB
Dropout Voltage VDrop IO = 1A, TJ =+25 oC - 2 - VOutput Resistance rO f = 1KHz - 17 - mΩShort Circuit Current ISC VI= 35V, TA =+25 oC - 250 - mAPeak Current IPK TJ= +25 oC - 2.2 - A
MC78XX/LM78XX/MC78XXA
12
Electrical Characteristics (MC7806A)(Refer to the test circuits. 0°C < TJ < 125°C, Io =1A, V I =11V, C I=0.33µF, C O=0.1µF, unless otherwise specified)
Note:1. Load and line regulation are specified at constant junction temperature. Change in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
Parameter Symbol Conditions Min. Typ. Max. Unit
Output Voltage VOTJ =+25 oC 5.58 6 6.12
VIO = 5mA to 1A, PO ≤ 15WVI = 8.6V to 21V 5.76 6 6.24
Line Regulation (Note1) Regline
VI= 8.6V to 25VIO = 500mA - 5 60
mVVI= 9V to 13V - 3 60
TJ =+25 oCVI= 8.3V to 21V - 5 60VI= 9V to 13V - 1.5 30
Load Regulation (Note1) Regload
TJ =+25 oCIO = 5mA to 1.5A - 9 100
mVIO = 5mA to 1A - 4 100IO = 250mA to 750mA - 5.0 50
Quiescent Current IQ TJ =+25 oC - 4.3 6 mA
Quiescent Current Change ∆IQ
IO = 5mA to 1A - - 0.5mAVI = 9V to 25V, IO = 500mA - - 0.8
VI= 8.5V to 21V, TJ =+25 oC - - 0.8Output Voltage Drift ∆V/∆T IO = 5mA - -0.8 - mV/ oC
Output Noise Voltage VNf = 10Hz to 100KHzTA =+25 oC - 10 - µV/Vo
Ripple Rejection RR f = 120Hz, IO = 500mAVI = 9V to 19V - 65 - dB
Dropout Voltage VDrop IO = 1A, TJ =+25 oC - 2 - VOutput Resistance rO f = 1KHz - 17 - mΩShort Circuit Current ISC VI= 35V, TA =+25 oC - 250 - mAPeak Current IPK TJ=+25 oC - 2.2 - A
MC78XX/LM78XX/MC78XXA
13
Electrical Characteristics (MC7808A)(Refer to the test circuits. 0°C < TJ < 125°C, Io =1A, V I = 14V, C I=0.33µF, C O=0.1µF, unless otherwise specified)
Note:1. Load and line regulation are specified at constant junction temperature. Change in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
Parameter Symbol Conditions Min. Typ. Max. Unit
Output Voltage VOTJ =+25 oC 7.84 8 8.16
VIO = 5mA to 1A, PO ≤15WVI = 10.6V to 23V 7.7 8 8.3
Line Regulation (Note1) Regline
VI= 10.6V to 25VIO = 500mA - 6 80
mVVI= 11V to 17V - 3 80
TJ =+25 oCVI= 10.4V to 23V - 6 80VI= 11V to 17V - 2 40
Load Regulation (Note1) Regload
TJ =+25 oCIO = 5mA to 1.5A - 12 100
mVIO = 5mA to 1A - 12 100IO = 250mA to 750mA - 5 50
Quiescent Current IQ TJ =+25 oC - 5.0 6 mA
Quiescent Current Change ∆IQIO = 5mA to 1A - - 0.5
mAVI = 11V to 25V, IO = 500mA - - 0.8VI= 10.6V to 23V, TJ =+25 oC - - 0.8
Output Voltage Drift ∆V/∆T IO = 5mA - -0.8 - mV/ oC
Output Noise Voltage VNf = 10Hz to 100KHzTA =+25 oC - 10 - µV/Vo
Ripple Rejection RR f = 120Hz, IO = 500mAVI = 11.5V to 21.5V - 62 - dB
Dropout Voltage VDrop IO = 1A, TJ =+25 oC - 2 - VOutput Resistance rO f = 1KHz - 18 - mΩShort Circuit Current ISC VI= 35V, TA =+25 oC - 250 - mAPeak Current IPK TJ=+25 oC - 2.2 - A
MC78XX/LM78XX/MC78XXA
14
Electrical Characteristics (MC7809A)(Refer to the test circuits. 0°C < TJ < 125°C, Io =1A, V I = 15V, C I=0.33µF, C O=0.1µF, unless otherwise specified)
Note:1. Load and line regulation are specified at constant, junction temperature. Change in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
Parameter Symbol Conditions Min. Typ. Max. Unit
Output Voltage VOTJ =+25°C 8.82 9.0 9.18
VIO = 5mA to 1A, PO≤15WVI = 11.2V to 24V 8.65 9.0 9.35
Line Regulation (Note1) Regline
VI= 11.7V to 25VIO = 500mA - 6 90
mVVI= 12.5V to 19V - 4 45
TJ =+25°C VI= 11.5V to 24V - 6 90 VI= 12.5V to 19V - 2 45
Load Regulation (Note1) Regload
TJ =+25°CIO = 5mA to 1.0A - 12 100
mVIO = 5mA to 1.0A - 12 100IO = 250mA to 750mA - 5 50
Quiescent Current IQ TJ =+25 °C - 5.0 6.0 mA
Quiescent Current Change ∆IQ
VI = 11.7V to 25V, TJ=+25 °C - - 0.8mAVI = 12V to 25V, IO = 500mA - - 0.8
IO = 5mA to 1.0A - - 0.5Output Voltage Drift ∆V/∆T IO = 5mA - -1.0 - mV/ °C
Output Noise Voltage VNf = 10Hz to 100KHzTA =+25 °C - 10 - µV/Vo
Ripple Rejection RR f = 120Hz, IO = 500mAVI = 12V to 22V - 62 - dB
Dropout Voltage VDrop IO = 1A, TJ =+25 °C - 2.0 - VOutput Resistance rO f = 1KHz - 17 - mΩShort Circuit Current ISC VI= 35V, TA =+25 °C - 250 - mAPeak Current IPK TJ=+25°C - 2.2 - A
MC78XX/LM78XX/MC78XXA
15
Electrical Characteristics (MC7810A)(Refer to the test circuits. 0°C < TJ < 125°C, Io =1A, V I = 16V, C I=0.33µF, C O=0.1µF, unless otherwise specified)
Note:1. Load and line regulation are specified at constant junction temperature. Change in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
Parameter Symbol Conditions Min. Typ. Max. Unit
Output Voltage VO TJ =+25°C 9.8 10 10.2
V IO = 5mA to 1A, PO ≤ 15W VI =12.8V to 25V 9.6 10 10.4
Line Regulation (Note1) Regline
VI= 12.8V to 26V IO = 500mA - 8 100
mV VI= 13V to 20V - 4 50
TJ =+25 °C VI= 12.5V to 25V - 8 100 VI= 13V to 20V - 3 50
Load Regulation (Note1) Regload
TJ =+25 °C IO = 5mA to 1.5A - 12 100
mV IO = 5mA to 1.0A - 12 100 IO = 250mA to 750mA - 5 50
Quiescent Current IQ TJ =+25 °C - 5.0 6.0 mA
Quiescent Current Change ∆IQ
VI = 13V to 26V, TJ=+25 °C - - 0.5mA VI = 12.8V to 25V, IO = 500mA - - 0.8
IO = 5mA to 1.0A - - 0.5Output Voltage Drift ∆V/∆T IO = 5mA - -1.0 - mV/ °C
Output Noise Voltage VN f = 10Hz to 100KHz TA =+25 °C - 10 - µV/Vo
Ripple Rejection RR f = 120Hz, IO = 500mA VI = 14V to 24V - 62 - dB
Dropout Voltage VDrop IO = 1A, TJ =+25°C - 2.0 - VOutput Resistance rO f = 1KHz - 17 - mΩShort Circuit Current ISC VI= 35V, TA =+25 °C - 250 - mAPeak Current IPK TJ=+25 °C - 2.2 - A
MC78XX/LM78XX/MC78XXA
16
Electrical Characteristics (MC7812A)(Refer to the test circuits. 0°C < TJ < 125°C, Io =1A, V I = 19V, C I=0.33µF, C O=0.1µF, unless otherwise specified)
Note:1. Load and line regulation are specified at constant junction temperature. Change in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
Parameter Symbol Conditions Min. Typ. Max. Unit
Output Voltage VO TJ =+25 °C 11.75 12 12.25
V IO = 5mA to 1A, PO ≤15W VI = 14.8V to 27V 11.5 12 12.5
Line Regulation (Note1) Regline
VI= 14.8V to 30V IO = 500mA - 10 120
mV VI= 16V to 22V - 4 120
TJ =+25 °C VI= 14.5V to 27V - 10 120 VI= 16V to 22V - 3 60
Load Regulation (Note1) Regload
TJ =+25 °C IO = 5mA to 1.5A - 12 100
mV IO = 5mA to 1.0A - 12 100 IO = 250mA to 750mA - 5 50
Quiescent Current IQ TJ =+25°C - 5.1 6.0 mA
Quiescent Current Change ∆IQ
VI = 15V to 30V, TJ=+25 °C - 0.8mA VI = 14V to 27V, IO = 500mA - 0.8
IO = 5mA to 1.0A - 0.5Output Voltage Drift ∆V/∆T IO = 5mA - -1.0 - mV/°C
Output Noise Voltage VN f = 10Hz to 100KHz TA =+25°C - 10 - µV/Vo
Ripple Rejection RR f = 120Hz, IO = 500mA VI = 14V to 24V - 60 - dB
Dropout Voltage VDrop IO = 1A, TJ =+25°C - 2.0 - VOutput Resistance rO f = 1KHz - 18 - mΩShort Circuit Current ISC VI= 35V, TA =+25 °C - 250 - mAPeak Current IPK TJ=+25 °C - 2.2 - A
MC78XX/LM78XX/MC78XXA
17
Electrical Characteristics (MC7815A)(Refer to the test circuits. 0°C < TJ < 125°C, Io =1A, V I =23V, C I=0.33µF, C O=0.1µF, unless otherwise specified)
Note:1. Load and line regulation are specified at constant junction temperature. Change in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
Parameter Symbol Conditions Min. Typ. Max. Unit
Output Voltage VO TJ =+25 °C 14.7 15 15.3
V IO = 5mA to 1A, PO ≤15W VI = 17.7V to 30V 14.4 15 15.6
Line Regulation (Note1) Regline
VI= 17.9V to 30V IO = 500mA - 10 150
mV VI= 20V to 26V - 5 150
TJ =+25°C VI= 17.5V to 30V - 11 150 VI= 20V to 26V - 3 75
Load Regulation (Note1) Regload
TJ =+25 °C IO = 5mA to 1.5A - 12 100
mV IO = 5mA to 1.0A - 12 100 IO = 250mA to 750mA - 5 50
Quiescent Current IQ TJ =+25 °C - 5.2 6.0 mA
Quiescent Current Change ∆IQ
VI = 17.5V to 30V, TJ =+25 °C - - 0.8mA VI = 17.5V to 30V, IO = 500mA - - 0.8
IO = 5mA to 1.0A - - 0.5Output Voltage Drift ∆V/∆T IO = 5mA - -1.0 - mV/°C
Output Noise Voltage VN f = 10Hz to 100KHz TA =+25 °C - 10 - µV/Vo
Ripple Rejection RR f = 120Hz, IO = 500mA VI = 18.5V to 28.5V - 58 - dB
Dropout Voltage VDrop IO = 1A, TJ =+25 °C - 2.0 - VOutput Resistance rO f = 1KHz - 19 - mΩShort Circuit Current ISC VI= 35V, TA =+25 °C - 250 - mAPeak Current IPK TJ=+25°C - 2.2 - A
MC78XX/LM78XX/MC78XXA
18
Electrical Characteristics (MC7818A)(Refer to the test circuits. 0°C < TJ < 125°C, Io =1A, V I = 27V, C I=0.33µF, C O=0.1µF, unless otherwise specified)
Note:1. Load and line regulation are specified at constant junction temperature. Change in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
Parameter Symbol Conditions Min. Typ. Max. Unit
Output Voltage VO TJ =+25 °C 17.64 18 18.36
V IO = 5mA to 1A, PO ≤15W VI = 21V to 33V 17.3 18 18.7
Line Regulation (Note1) Regline
VI= 21V to 33V IO = 500mA - 15 180
mV VI= 21V to 33V - 5 180
TJ =+25 °C VI= 20.6V to 33V - 15 180 VI= 24V to 30V - 5 90
Load Regulation (Note1) Regload
TJ =+25°C IO = 5mA to 1.5A - 15 100
mV IO = 5mA to 1.0A - 15 100 IO = 250mA to 750mA - 7 50
Quiescent Current IQ TJ =+25 °C - 5.2 6.0 mA
Quiescent Current Change ∆IQ
VI = 21V to 33V, TJ=+25 °C - - 0.8mA VI = 21V to 33V, IO = 500mA - - 0.8
IO = 5mA to 1.0A - - 0.5Output Voltage Drift ∆V/∆T IO = 5mA - -1.0 - mV/ °C
Output Noise Voltage VN f = 10Hz to 100KHz TA =+25°C - 10 - µV/Vo
Ripple Rejection RR f = 120Hz, IO = 500mA VI = 22V to 32V - 57 - dB
Dropout Voltage VDrop IO = 1A, TJ =+25°C - 2.0 - VOutput Resistance rO f = 1KHz - 19 - mΩShort Circuit Current ISC VI= 35V, TA =+25°C - 250 - mAPeak Current IPK TJ=+25 °C - 2.2 - A
MC78XX/LM78XX/MC78XXA
19
Electrical Characteristics (MC7824A)(Refer to the test circuits. 0°C < TJ < 125°C, Io =1A, V I = 33V, C I=0.33µF, C O=0.1µF, unless otherwise specified)
Note:1. Load and line regulation are specified at constant junction temperature. Change in VO due to heating effects must be taken
into account separately. Pulse testing with low duty is used.
Parameter Symbol Conditions Min. Typ. Max. Unit
Output Voltage VO TJ =+25 °C 23.5 24 24.5
V IO = 5mA to 1A, PO ≤15W VI = 27.3V to 38V 23 24 25
Line Regulation (Note1) Regline
VI= 27V to 38V IO = 500mA - 18 240
mV VI= 21V to 33V - 6 240
TJ =+25 °C VI= 26.7V to 38V - 18 240 VI= 30V to 36V - 6 120
Load Regulation (Note1) Regload
TJ =+25 °C IO = 5mA to 1.5A - 15 100
mV IO = 5mA to 1.0A - 15 100 IO = 250mA to 750mA - 7 50
Quiescent Current IQ TJ =+25 °C - 5.2 6.0 mA
Quiescent Current Change ∆IQ
VI = 27.3V to 38V, TJ =+25 °C - - 0.8mA VI = 27.3V to 38V, IO = 500mA - - 0.8
IO = 5mA to 1.0A - - 0.5Output Voltage Drift ∆V/∆T IO = 5mA - -1.5 - mV/ °C
Output Noise Voltage VN f = 10Hz to 100KHz TA = 25 °C - 10 - µV/Vo
Ripple Rejection RR f = 120Hz, IO = 500mA VI = 28V to 38V - 54 - dB
Dropout Voltage VDrop IO = 1A, TJ =+25 °C - 2.0 - VOutput Resistance rO f = 1KHz - 20 - mΩShort Circuit Current ISC VI= 35V, TA =+25 °C - 250 - mAPeak Current IPK TJ=+25 °C - 2.2 - A
MC78XX/LM78XX/MC78XXA
20
Typical Perfomance Characteristics
Figure 1. Quiescent Current
Figure 3. Output Voltage
Figure 2. Peak Output Current
Figure 4. Quiescent Current
I
MC78XX/LM78XX/MC78XXA
21
Typical Applications
Figure 5. DC Parameters
Figure 6. Load Regulation
Figure 7. Ripple Rejection
Figure 8. Fixed Output Regulator
Input OutputMC78XX/LM78XX
Input OutputMC78XX/LM78XX
Input OutputMC78XX/LM78XX
Input OutputMC78XX/LM78XX
MC78XX/LM78XX/MC78XXA
22
Figure 9. Constant Current Regulator
Notes:(1) To specify an output voltage. substitute voltage value for "XX." A common ground is required between the input and the
Output voltage. The input voltage must remain typically 2.0V above the output voltage even during the low point on the inputripple voltage.
(2) CI is required if regulator is located an appreciable distance from power Supply filter.(3) CO improves stability and transient response.
VO = VXX(1+R2/R1)+IQR2Figure 10. Circuit for Increasing Output Voltage
IRI ≥5 IQVO = VXX(1+R2/R1)+IQR2
Figure 11. Adjustable Output Regulator (7 to 30V)
Input OutputMC78XX/LM78XX
CI
Co
Input OutputMC78XX/LM78XX
CICo
IRI 5IQ≥
Input OutputMC7805LM7805
LM741Co
CI
MC78XX/LM78XX/MC78XXA
23
Figure 12. High Current Voltage Regulator
Figure 13. High Output Current with Short Circuit Protection
Figure 14. Tracking Voltage Regulator
Input
OutputMC78XX/LM78XX
Input
OutputMC78XX/LM78XX
MC78XX/LM78XX
LM741
MC78XX/LM78XX/MC78XXA
24
Figure 15. Split Power Supply ( ±15V-1A)
Figure 16. Negative Output Voltage Circuit
Figure 17. Switching Regulator
MC7815
MC7915
Input
Output
MC78XX/LM78XX
Input Output
MC78XX/LM78XX
MC78XX/LM78XX/MC78XXA
25
Mechanical DimensionsPackage
4.50 ±0.209.90 ±0.20
1.52 ±0.10
0.80 ±0.102.40 ±0.20
10.00 ±0.20
1.27 ±0.10
ø3.60 ±0.10
(8.70)
2.80
±0.
1015
.90
±0.2
0
10.0
8 ±0
.30
18.9
5MA
X.
(1.7
0)
(3.7
0)(3
.00)
(1.4
6)
(1.0
0)
(45°)
9.20
±0.
2013
.08
±0.2
0
1.30
±0.
10
1.30+0.10–0.05
0.50+0.10–0.05
2.54TYP[2.54 ±0.20]
2.54TYP[2.54 ±0.20]
TO-220
MC78XX/LM78XX/MC78XXA
26
Mechancal Dimensions (Continued)
Package
6.60 ±0.20
2.30 ±0.10
0.50 ±0.10
5.34 ±0.30
0.70
±0.
20
0.60
±0.
200.
80 ±
0.20
9.50
±0.
30
6.10
±0.
20
2.70
±0.
209.
50 ±
0.30
6.10
±0.
20
2.70
±0.
20
MIN
0.55
0.76 ±0.10 0.50 ±0.10
1.02 ±0.20
2.30 ±0.20
6.60 ±0.20
0.76 ±0.10
(5.34)
(1.50)
(2XR0.25)
(5.04)
0.89
±0.
10
(0.1
0)(3
.05)
(1.0
0)
(0.9
0)
(0.7
0)
0.91
±0.
10
2.30TYP[2.30±0.20]
2.30TYP[2.30±0.20]
MAX0.96
(4.34)(0.50) (0.50)
D-PAK
MC78XX/LM78XX/MC78XXA
27
Ordering InformationProduct Number Output Voltage Tolerance Package Operating Temperature
LM7805CT ±4% TO-220 0 ~ + 125°C
Product Number Output Voltage Tolerance Package Operating TemperatureMC7805CT
±4%
TO-220
0 ~ + 125°C
MC7806CTMC7808CTMC7809CTMC7810CTMC7812CTMC7815CTMC7818CTMC7824CT
MC7805CDT
D-PAK
MC7806CDTMC7808CDTMC7809CDTMC7810CDTMC7812CDTMC7805ACT
±2% TO-220
MC7806ACTMC7808ACTMC7809ACTMC7810ACTMC7812ACTMC7815ACTMC7818ACTMC7824ACT
MC78XX/LM78XX/MC78XXA
7/2/01 0.0m 001Stock#DSxxxxxxxx
2001 Fairchild Semiconductor Corporation
LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
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