POS-PHY Level 4 (SPI-4.2) Loopback Reference Design · 2020. 11. 12. · development kits. This reference design uses two instances of the POS-PHY Level 4 MegaCore function, the POS-PHY

© May 2010 Altera Corporation

© May 2010

AN 606: POS-PHY Level 4 (SPI-4.2)Loopback Reference Design

AN-606-1.0

The packet over SONET/SDH physical layer (POS-PHY) Level 4—Phase 2 (SPI-4.2) loopback reference design shows how you can transmit and receive data using the Altera® POS-PHY Level 4 MegaCore® function and the Stratix® IV and Stratix III development kits. This reference design uses two instances of the POS-PHY Level 4 MegaCore function, the POS-PHY Level 4 transmitter MegaCore function and receiver MegaCore function. The reference design provides a general platform for you to control, test, and monitor the POS-PHY Level 4 operations.

This application note describes how to use the loopback interface with the Stratix IV and Stratix III FPGA development board that is available in the Stratix IV and Stratix III development kit, and a high-speed mezzanine card (HSMC).

f For more information about the Stratix IV and Stratix III development kits, refer to the Stratix IV Development Kit User Guide and the Stratix III Development Kit User Guide. For more information about the Stratix IV and Stratix III FPGA board, refer to the Stratix IV E Development FPGA Development Board Reference Manual and Stratix III Development Board Reference Manual; for more information about the HSMC, refer to the High Speed Mezzanine Card (HSMC) Specification. For more information about the POS-PHY Level 4 MegaCore function, refer to the POS-PHY Level 4 MegaCore Function User Guide or contact your Altera representative.

Functional DescriptionThe reference design has the following features:

■ Demonstrates synchronous data streaming using the POS-PHY Level 4 transmitter MegaCore function and receiver MegaCore function.

■ Uses the Atlantic Master module with the Atlantic™ interface to generate data packets.

■ Uses the Atlantic Slave module with the Atlantic interface as a data sinking mechanism to demonstrate data packets counter and protocol error detection.

■ Uses the system initialization module to bring up the system.

■ Incorporates the In-System Sources and Probes Editor and the SignalTap® II Logic Analyzer for debugging purposes.

AN 606: POS-PHY Level 4 (SPI-4.2) Loopback Reference Design

http://www.altera.com/literature/manual/rm_stratixiii_dev_kit_host_board.pdf

http://www.altera.com/literature/manual/rm_stratixiii_dev_kit_host_board.pdf

http://www.altera.com/literature/ug/ug_posphy4.pdf


http://www.altera.com/literature/ds/hsmc_spec.pdf

http://www.altera.com/literature/manual/rm_sive_fpga_dev_board.pdf

http://www.altera.com/literature/ug/ug_siii_devkit.pdf

http://www.altera.com/literature/ug/ug_sive_fpga_dev_kit.pdf

Page 2 Functional Description

Figure 1 shows a high-level block diagram of the loopback reference design.

The following sections describe the various modules of the block diagram.

Figure 1. Loopback Reference Design Block Diagram (Note 1)

Note to Figure 1:

(1) The reference design does not use the PLL_ref_125MHz PLL. However, you can connect the PLL_ref_125MHz PLL to the transmitter MegaCore function and receiver MegaCore function to run the reference design with clock outputs of 125 MHz, 250 MHz, and 500 MHz.

Stratix IV FPGA

POS-PHY Level 4 Transmitter MegaCore Function

POS-PHY Level 4 Receiver MegaCore Function

PLL

PLL_ref_125 MHz

System Initialization

In-System Sources and Probes Editor

SignalTap II

JTAG Controller

50 MHz

125 MHz

Altera Programming

Hardware

trefclk

rxsys_clk

Atlantic Master

(Packet Checker)

System PLLs

(Packet Generator)

Atlantic Slave

Atlantic Interface

Atlantic Interface

System-Level Debugging Tools

Quartus II

AN 606: POS-PHY Level 4 (SPI-4.2) Loopback Reference Design © May 2010 Altera Corporation

Functional Description Page 3

POS-PHY Level 4 Transmitter MegaCore FunctionFigure 2 shows the high-level block diagram of the POS-PHY Level 4 transmitter MegaCore function internal modules and clock network that the loopback reference design uses.

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The loopback reference design uses the Shared Buffer with Embedded Addressing mode to instantiate only a single Atlantic buffer, where each data word carries a tag containing the port number. The Shared Buffer with Embedded Addressing mode does not provide a transmit scheduler. The data packets are pulled from the buffer and transmitted in the same order in which the data are pushed in. The Atlantic Master module schedules the data transmission and dictates the order in which data packets are written to the Atlantic buffer. In the reference design, the shared buffer is instantiated with 16 ports and 128 bits data path width in single clock domain mode. The tdint_clk signal clocks the Atlantic buffer and the status processor.

The data processor performs two important functions—Atlantic conversion and insertion of control word, and DIP-4 calculation and training pattern insertion. The Atlantic conversion block transfers data from the Atlantic Master module to the Atlantic buffer. When Ignore Backpressure is enabled, a SATISFIED status for any port enables a continuous transfer of data packets on the Atlantic interface. The data processor block also inserts control words and performs DIP-4 calculation and insertion in between data burst. The data processor also inserts the training patterns at the interval defined by the Maximum Training Sequence Interval parameter (MaxT). The MaxT value ranges from 0 to 65,535 bytes. For example, if MaxT is set to 1,024 bytes, the transmitter MegaCore function sends training patterns after every 1KB of data packets sent.

Figure 2. POS-PHY Level 4 Transmitter MegaCore Function High-level Block Diagram

SERDES

LVDSPLL

LVTTL

LVTTL

Data Processor Atlantic Buffer

Status Processor

ALTLVDS Megafunction

Atlantic Interface

txsys_clk

2tstat[1:0]

ctl_ts_statedge

tsclk

trefclk

tclclk

tdint_clk

tctl

tdat[15:0]

© May 2010 Altera Corporation AN 606: POS-PHY Level 4 (SPI-4.2) Loopback Reference Design


The ALTLVDS megafunction block converts parallel data packets into high-speed SPI-4.2 LVDS standard data bits operating at eight times the internal frequency because the reference design uses the 128-bit variation. The status processor block monitors and decodes the tstat status channel from the receiver MegaCore function. The txsys_clk is used to clock the status processor. In the reference design, the txsys_clk is connected to the tdint_clk. The status processor interprets the status channel in two modes—Optimistic and Pessimistic. This reference design uses the Optimistic mode setting. In this mode, the status information from the receiver MegaCore function is passed to the Atlantic Master module before the DIP-2 cycle is received. If DIP-2 errors are flagged, there is no effect on the status provided to the Atlantic Master module.

Table 1, Table 2, and Table 3 show the parameter settings of the POS-PHY transmitter MegaCore function for this reference design.

Table 1. Basic Parameters Page

Options Value

Device Family Stratix III

Data Flow Direction Transmitter

Dynamic Phase Alignment —

LVDS Data Rate 800 Mbps

PLL Input Frequency 100.0

Data Path Width 128 bits

Buffer Mode Shared Buffer with Embedded Addressing

Number of Ports 16

Buffer Size 4096 Bytes

Atlantic FIFO Clock Mode Single Clock Domain

Atlantic I/F width 128 bit

Status Channel Clock Edge Negative Edge

Status Channel I/O Standard LVTTL

Table 2. Optional Features Page

Options Value

Atlantic Error Checking Enabled

Parity Protected Memory —

Transmitter Options

Lite Transmitter —

Status Interpretation Mode Optimistic

Ignore Backpressure Enabled

Switch on End of Packet —

Burst Limit Enabled —

FIFO RAM Blocks 4 RAM Blocks



f For more information about the parameter settings for the transmitter MegaCore function, refer to Chapter3: Parameterizing the MegaCore Function in the POS-PHY Level 4 MegaCore Function User Guide.

POS-PHY Level 4 Receiver MegaCore FunctionFigure 3 shows the high-level block diagram of the POS-PHY Level 4 receiver MegaCore function internal modules and clock network that the loopback reference design uses.

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The loopback reference design uses the 64-bit variation of the receiver MegaCore function. For 64-bit variation, the Altera ALTLVDS megafunction desterilizes the SPI-4.2 rdat or rctl lines into words at one quarter of the rdat data rate. The rdint_clk is derived from the internal LVDS fast PLL and is the clock that drives the internal blocks of the receiver MegaCore function. The channel aligner block performs channel alignment through bit slip feature by using the SPI-4.2 training patterns. This process is called the dynamic phase alignment (DPA). The DPA is enabled in the reference design because the data rate is running at 800 Mbps. For a 64-bit data path width, the DPA uses a deserialization factor of 4.

Table 3. Protocol Parameters Page

Options Value

Parameter Type Real Time Programmable

Calendar Options

Asymetric Port Support —

Programmable Calendar Length Support Enabled

Figure 3. POS-PHY Level 4 Receiver MegaCore Function High-level Block Diagram

DPA/SERDES

LVDSPLL

LVTTL

Channel Aligner Data Processor

Status Processor

ALTLVDS Megafunction

2rstat[1:0]

rdclk

rdint_clk

rctl

rdat[15:0]

LVTTL

Atlantic Buffer

rsclkrxsys_clk

Atlantic Interface

a0_arxclk





The receiver MegaCore function Atlantic buffer is configured as a shared buffer with embedded addressing. The shared buffer is a single Atlantic buffer, where for each data word, a tag is carried containing the port number. The Atlantic-side logic cannot selectively pick a port to access so data bursts from all ports are stored collectively into one shared physical buffer, and the ordering of the data bursts is maintained in the order in which they were received on the SPI-4.2 bus. The shared buffer of the loopback reference design is instantiated as 16 ports and 64-bit data path width with multiple clocks domain mode. In the reference design, the rxsys_clk clock is used to drive the a0_arxclk clock. However, you can use an asynchronous clock to drive the a0_arxclk clock.

The status processor block calculates, formats, and transmits the buffer status over the status channel. The status processor block generates the rsclk clock in the following conditions:

■ In 128-bit variations, the rsclk clock runs at the rdint_clk clock rate

■ In 64-bit variations, the rsclk clock runs at half the rdint_clk clock rate

■ In 32-bit variations, the rsclk clock runs at one-quarter of the rdint_clk clock rate

The reference design of the receiver MegaCore function uses the rsclk clock that runs at half the rate of rdint_clk clock, which is 100 MHz given that the rdint_clk clock is 200 MHz. The status processor block compares the Atlantic buffer fill levels to the almost empty (AE) and almost full (AF) values for the requested port. In the shared buffer with embedded addressing mode, because there is only a single Atlantic buffer, the status for any port is calculated according to the single level as opposed to a per-port basis. The buffer status of each port is encoded in two bits and is transmitted synchronous to the rsclk clock.

Table 4 describes the two-bit status value that is sent through the rstat bus.

1 The MaxBurst1 and MaxBurst2 parameters are only applicable for individual buffer mode of the transmitter MegaCore function. For shared buffer with embedded addressing mode of the transmitter MegaCore function, the external scheduler interprets the status bits information and provides the appropriate amount of data transfer over to the Atlantic interface.

Table 4. Status Channel Field

MSB LSB Description

1 1 Reserved for framing

1 0 SATISFIED—FIFO buffer is almost full. New credits must be granted in the far end scheduler

0 1 HUNGRY—FIFO buffer is midpoint. MaxBurst2 credits must be granted in the far end scheduler

0 0 STARVING—FIFO buffer is almost empty. MaxBurst1 credits must be granted in the far end scheduler



Table 5, Table 6, and Table 7 show the parameter settings of the POS-PHY receiver MegaCore function for this reference design.

f For more information about the parameter settings for the receiver MegaCore function, refer to Chapter 3: Parameterizing the MegaCore Function in the POS-PHY Level 4 MegaCore Function User Guide.

Table 5. Basic Parameters Page

Options Value

Device Family Stratix IV

Data Flow Direction Receiver

Dynamic Phase Alignment Enabled

LVDS Data Rate 800 Mbps

Data Path Width 64 bits

Buffer Mode Shared Buffer with Embedded Addressing

Number of Ports 16

Buffer Size 1024 Bytes

Atlantic FIFO Clock Mode Multiple Clock Domain

Atlantic I/F width 64 bit

Status Channel Clock Edge Negative Edge

Status Channel I/O Standard LVTTL

Table 6. Optional Features Page

Options Value

Atlantic Error Checking Enabled

Parity Protected Memory Enabled

FIFO RAM Blocks 4 RAM Blocks

Receiver Options

Ignore LVDS DPA locked After Training Enabled

DIP-4 Error Marking Optimistic

End of Packet Based Data Available Enabled

Status Source Buffer Fill Level

Safe External (User Controlled Status) Enabled

Table 7. Protocol Parameters Page

Options Value

Parameter Type Real Time Programmable

Calendar Options

Asymetric Port Support —

Programmable Calendar Length Support —





Atlantic Master (Packet Generator)The Atlantic Master module uses the Atlantic interface to generate the SPI-4.2 data packets to the transmitter MegaCore function on a 128-bit data path. The SPI-4.2 data packets are clocked with the tdint_clk clock from the transmitter MegaCore function. The data output port from the Atlantic Master module is synchronous with the a0_atxdat of the Atlantic buffer. The Atlantic Master module is capable of generating randomize data packets. The Atlantic Master module also generates the SPI-4.2 data headers and data payloads. The data header consists of 16 bits header, 8 bits packet type, 16 bits packet serial number, and 16 bits packet length. For data payload generation, two types of data payload are generated—data payload without error injection and data payload with error injection.

Figure 4 describes the state machine of the Atlantic Master module.

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Atlantic Slave (Packet Checker)The Atlantic Slave module receives data from the POS-PHY Level 4 receiver MegaCore function. The Atlantic Slave module also supports 64 bits of data path width. The Atlantic Slave module is clocked with the rxsys_clk clock from the receiver MegaCore function. The data input port of the Atlantic Slave module is synchronous with the a0_arxdat output port of the receiver MegaCore function Atlantic buffer.

The Atlantic Slave module performs the following functions:

■ Protocol error detection

■ Atlantic slave source data control signal generation

■ Data payload counter and sinking

■ Packet serial number error counter

■ Packet counter

■ Header error counter

■ DIP-4 error counter

Figure 4. Atlantic Master Data Packet Generation State Machine

Data Payload Generation

IDLE

Data Header Generation Gap Randomization

Packet Size Randomization



The protocol error detection mechanism detects the following error conditions:

■ An idle state being followed by an end-of-packet (EOP) signal assertion

■ An EOP signal being followed by another EOP signal assertion

■ A start-of-packet (SOP) signal being followed by another SOP signal

The Atlantic Slave module drives the data transfer enable signal. The enable signal is used to control the flow of data across the Atlantic interface. Because the Atlantic Slave module is a master sink, the enable signal behaves as a read enable to the receiver MegaCore function Atlantic buffer. The data payload counter counts the number of incoming data packets from the receiver MegaCore function Atlantic buffer and latch them onto the registers. On the other hand, the Packet Serial Number (PSN) error counter counts the number of error packets while the header error counter counts the number of errors detected in the data header. The DIP-4 error counter increments whenever the DIP-4 error signal toggles.

System PLLThe PLL module uses the ALTPLL MegaWizard™ interface. The PLL module is instantiated to generate the clock outputs of 250 MHz, 200 MHz, and 100 MHz for the internal modules of the reference design. The PLL module uses the 50 MHz input clock. The PLL_ref_125MHz PLL is not used in this reference design. However, the PLL_ref_125MHz PLL is used to generate clock outputs of 125 MHz, 250 MHz, and 500 MHz respectively for SPI-4.2 data rates other than 800 Mbps.

System InitializationThe system initialization module initializes the transmitter MegaCore function and receiver MegaCore function during power-up or when you toggle the reset_n signal.

Figure 5 shows the system initialization for this reference design.

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Figure 5. System Initialization State Machine Diagram

IDLE

PU

PLL0_LOCK

PLL0_RDY

DONE

CLK_RDY_1

CLK_RDY



On power-up or when you toggle the asynchronous reset_n signal of the reference design, the system is driven to the idle state of the state machine. In both the idle and pll0_lock states, the system initialization module resets the transmitter MegaCore function and receiver MegaCore function core logic and their internal LVDS PLL. The pll0_rdy state indicates whether the system PLL has been locked. After the system PLL lock signal is asserted, the PU state deasserts the reset of the transmitter MegaCore function LVDS PLL while other modules remain in the reset mode. In the clk_rdy state, when the transmitter MegaCore function LVDS PLL locks, the state machine releases the transmitter MegaCore function logic reset. In the clk_rdy_1 state, the receiver MegaCore function LVDS PLL reset is released. When the receiver MegaCore function LVDS PLL lock signal is asserted, the state machine deasserts the receiver MegaCore function logic reset.

In-System Sources and Probes EditorThe In-System Sources and Probes Editor consists of the ALTSOURCE_PROBE megafunction that offers you the flexibility to drive and control internal module signals of the reference design in a dynamic debugging environment. Traditional debugging techniques often use an external pattern generator to exercise the logic and a logic analyzer to study the output waveforms during run time. With the availability of the In-System Sources and Probes Editor incorporated into this reference design, you can sample and drive internal signals in real time using the JTAG connection to shift data to and from the ALTSOURCE_PROBE megafunction instance. The ALTSOURCE_PROBE megafunction sets up a register chain to either drive or sample the selected nodes in the reference design.

Figure 6 shows a block diagram of the components that make up the In-System Sources and Probes Editor.

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Figure 6. In-System Sources and Probes Editor Diagram

Probes

Design LogicFPGA

Sources

ALTSOURCE_PROBE Megafunction

JTAG Controller

Altera Programming

Hardware

Quartus II Software

D Q

D Q



Table 8 describes the internal signals of the reference design that are used in the In-System Sources and Probes Editor. The source signals drive inputs to your design while the probe signals are monitored.

Table 8. In-System Sources and Probes Signals (Part 1 of 4)

Signal Description

Source Signals

reset_n A master reset that resets the entire reference design. This signal is active low. When this signal is toggled, the system initialization goes into idle state.

ry_rsfrm When asserted, this signal forces the receiver MegaCore function status channel into framing mode beginning at the end of the next frame. The receiver MegaCore function sends training sequence “11” on the rstat port.

ts_rsfrm When asserted, this signal disables the status state machine at the beginning of the next frame. stat_tx_sync is forced low and stat_ts_disabled is asserted.

rx_pll_reset When asserted, this signal resets the internal receiver MegaCore function fast LVDS PLL.

tx_pll_reset When asserted, this signal resets the internal transmitter MegaCore function fast LVDS PLL.

rxreset_n This signal resets the receiver MegaCore function internal logic when driven low.

ctl_rd_dpa_force_unlock When asserted, this signal forces the DPA circuitry and PLL to unlock and the receiver MegaCore function to go into training mode. The SPI-4.2 standard training sequence is sent from the transmitter MegaCore function.

ctl_ry_dip2_err_ins This is a forced error insertion signal. When asserted, this signal forces the status channel to insert error status.

tx_reset_n This signal resets the transmitter MegaCore function internal logic when driven low.

ctl_rd_abuf_flush When asserted, this signal flushes the internal buffer and no data is written to the Atlantic buffers. Data is lost until this signal is deasserted. This signal must be asserted for one rdint_clk clock cycle only and any subsequent assertion has to be done after a minimum of approximately 20 clock cycles because some ABUF internal signals are sent from one clock domain to another.

payload_err_ins When asserted, this signal inserts errors during data payload generation in the Atlantic Master module.

psn_err_ins The reference design does not use this signal.

header_err_ins When asserted, this signal injects errors in the data header packets.



rand_pkt_size When this signal is asserted, the packet size generation is randomized in the Atlantic Master module.

rand_pkt_gape When this signal is asserted, packet gap generation is randomimized in the Atlantic Master module.

pkt_size[15:0] This 16-bit bus determines the size of the data packet that is sent over to the transmitter MegaCore function Atlantic buffer.

Probe Signals

pll0_refclk The 50 MHz input clock.

tdint_clk Derived from the trefclk clock. This clock is generated by the internal PLL of the transmitter MegaCore function.

pll0_lock PLL lock signal for the system PLL.

txreset_n The active low reset signal for the transmitter MegaCore function internal logic.

rxreset_n_1 The active low reset signal for the receiver MegaCore function internal logic.

reset_n_pad The active low reset signal that is a result of the cpu_reset AND with reset_n signal.

cpu_reset Push button reset (S2) on Stratix IV development board.

tx_pll_locked Transmitter MegaCore function LVDS fast PLL lock signal.

rx_pll_lock Receiver MegaCore function LVDS fast PLL lock signal.

tsclk SPI-4.2 transmit status clock.

rdclk SPI-4.2 differential receive clock. The double-data rate clock synchronous to the rctl and rdat.

tstat[1:0] SPI-4.2 transmit status channel. Indicates the downstream device’s FIFO buffers fill levels to the upstream device’s scheduler.

rxsys_clk Receiver MegaCore function system clock for internal modules.

stat_rd_rat_sync Main receiver MegaCore function data path synchronous signal that is a combination of the DPA lock, channel aligner sync, and DIP-4 status.

dip_switch0_s Input from SW3.1. The reference design does not use this signal.



dip_switch3_s Input from SW3.4. This signal is not used in the reference design.


Signal Description



led_out_0 Represents the stat_rd_dpa_lvds_locked signal.

led_out_1 Represents the stat_rd_dpa_locked signal.

pkt_cnt Packet counter register of the Atlantic Slave module.

payload_err_cnt Data payload error counter of the Atlantic Slave module.

a0_atxdav Transmitter MegaCore function Atlantic data is available. This signal is asserted when the Atlantic buffer has at least ctl_atx_fth bytes of free space.

a0_atxena Transmitter MegaCore function Atlantic enable.

a0_atxsop Transmitter MegaCore function Atlantic start of packet.

a0_atxeop Transmitter MegaCore function Atlantic end of packet.

a0_atxerr Transmitter MegaCore function Atlantic error signal.

err_ts_dip2 Indicates that the calculated DIP-2 does not match the DIP-2 word in the status frame. This signal is asserted synchronous to stat_ts_dip2state.

a0_arxdav Receiver MegaCore function Atlantic data is available. This signal is asserted when the Atlantic buffer has at least ctl_atx_fth bytes of free space.

a0_arxena Receiver MegaCore function Atlantic enable.

a0_arxval Receiver MegaCore function Atlantic data valid.

a0_arxsop Receiver MegaCore function Atlantic start of packet.

a0_ardeop Receiver MegaCore function Atlantic end of packet.

a0_arxerr Receiver MegaCore function Atlantic error signal.

led_out_2 stat_rd_rdat_sync signal AND with inverted err_rd_dpa signal.

stat_rd_dip4_oos Receiver MegaCore function out-of-service flag. When asserted, the MegaCore function continues to pass data even though it receives the DIP-4 errors above threshold.

rdint_clk This clock is derived from the rdclk clock and generated from the receiver MegaCore function LVDS fast PLL.

stat_rd_dpa_locked When asserted, this signal indicates that the DPA aligner is aligned to the training patterns.

err_rd_dip4 When asserted at each clock cycle, this signal indicates that one or more calculated DIP-4 values does not match the received DIP-4 values.

current_state[2:0] State machine of the system initialization module.

stat_rd_dpa_lvds_locked[16:0] When signals are high, this signal indicates that the DPA PLL is locked.


Signal Description



For more information about the ALTSOURCE_PROBE megafunction, refer to Design Debugging Using In-Sources and Probes section in Section IV. In-System Design Debugging chapter in volume 3 of the Quartus® II Handbook.

atx_dat[127:64] Transmitter MegaCore function Atlantic data bus.

arx_dat[63:0] Receiver MegaCore function Atlantic data bus.


Signal Description


http://www.altera.com/literature/hb/qts/qts_qii5v3_05.pdf

Getting Started Page 15

Getting StartedThis section discusses the requirements and related procedures to demonstrate the POS-PHY Level 4 reference design with the Stratix IV or Stratix III development board. This section contains the following topics:

■ Hardware and Software Requirements

■ Obtaining the Design

■ Setting Up the Hardware

■ Running the Reference Design

Hardware and Software RequirementsThe demonstration requires the following hardware and software:

■ Stratix IV GX or Stratix III FPGA development kit

■ Loopback HSMC

■ 20V, 3.2A maximum output power supply

■ USB cable for embedded JTAG

■ POS-PHY Level 4 MegaCore function

■ Quartus® II software, version 9.0 or later

■ ModelSim®-Altera software 6.5b

Obtaining the DesignFigure 7 shows the directory structure of the reference design.

Figure 7. Directory Structure

dbContains the encrypted database files for Quartus II synthesis

<path> Installation directory

PLLContains the ALTPLL megafunction of 50 MHz clock inputPLL_ref_125mContains the ALTPLL megafunction of 125 MHz clock inputSOURCE_PROBEContains the In-System Sources and Probes source filesSPI4_RXContains the SPI-4.2 receive core source files and the IP simulation modelSPI4_TXContains the SPI-4.2 transmit core source files and the IP simulation modelTB

Contains the packet monitor module (atlantic_slave.v )Contains the packet generator module (atlantic_master.v )Contains the system initialization state machine (sys_init.v )Contains the top module of the whole system (top.v )

Project file (SPI4.qpf)Archive file (top.qar )Source and Probe file (Spf1.spf)SignalTap file (stp1.stp )Synopsys Design Constraints file (top.sdc )

stratix4-spi4-loop-back-on-development-board.zip


Page 16 Getting Started

Setting Up the HardwareFigure 8 shows how the Stratix IV GX FPGA development board is connected to the HSMC.

f For more information about the Stratix IV GX FPGA development board, refer to the Stratix IV GX FPGA Development Board Reference Manual; for more information about the HSMC, refer to the High Speed Mezzanine Card (HSMC) Specification.

Figure 8. Hardware Setup

JTAG port

S120V power supply HSMC

USB cable


http://www.altera.com/literature/manual/rm_sivgx_fpga_dev_board.pdf

http://www.altera.com/literature/ds/hsmc_spec.pdf


Running the Reference Design To run the reference design, perform the following steps:

1. Set up the following board connections:

a. Connect the HSMC to Port A of the FPGA development board. Refer to Figure 8 on page 16.

b. Specify the default board settings located on the back of the FPGA development board. For more information about the default development board settings, refer to the development board reference manual of your target device.

c. Connect the USB-Blaster™ download cable to the board’s USB Type-B Connector (J6).

1 For Stratix III FPGA board, remove J2 and J3. Ensure that SW1 is configured with the following settings:

■ FPGA_BYPASS = OFF

■ HSMA_BYPASS = OFF

■ MAX_ENABLE = OFF

d. Connect the FPGA development board (J4) to the power supply

e. Turn on the switch (S1) to power-up the board

2. Launch the Quartus II software and select the following speed grade settings for your device:

■ Stratix IV non-ES (top_EP4GX230KF40C2.sof) = C2

■ Stratix IV ES (top_EP4XGX230KF40C3ES.sof) = C3

■ Stratix III (top_EP3SL150F1152C2.sof) = C2

To set the speed grade settings for Stratix IV non-ES device, perform the following steps:

a. In the Quartus II software, on the Assignments menu, click Settings. The Settings dialog box appears.

b. In the Category list, select Device.

c. In the Family list, select Stratix IV(GT/GX/E).

d. Under Available Devices, select EP4GX230KF40C2, and click OK.

e. In the Speed grade list, select C2.

3. To compile the reference design, perform the following steps:

a. On the File menu, click Open Project, navigate to \<directory>\SPI4.qpf, and click Open.

b. On the Processing menu, click Start Compilation.



4. To program the Stratix IV GX SRAM object file (.sof) with the appropriate speed grade settings for your FPGA device, perform the following steps:

a. On the Tools menu, click Programmer. The file is automatically detected by the software during compilation and it appears on the pop-up window.

b. Click Start to download the Quartus II-generated file to the FPGA board. If the file does not appear in the pop-up window, click Add File, navigate to \<directory>\top_EP4GX230KF40C2.sof, and click Open.

1 The following SDC design rules are applied:

■ All timing violations due to signals that go across two different clock domains can be ignored.

■ The reset removal and recovery can be ignored because all the reset signals have been synchronized in the design.

■ The system is over-constrained to run at a 20% higher clock frequency by adjusting the frequency of the PLL reference clock. Ensure that timing violations are within the margin.

5. On the File menu, click Open, navigate to \<directory>\Spf1.spf, and click Open. The In-System Sources and Probes Editor window appears.



6. From the In-System Sources and Probes Editor window, ensure that tx_reset_n and rxreset_n are set to high (1), and rx_pll_reset and tx_pll_reset are set to low (0).

7. On the Processing menu, click Continuously Read Probe Data. Click to toggle the source value (1 or 0) of the reset_n signal in the Data column to start sending data packets from the TX Atlantic Master.

8. Observe the following signals activity in the In-System Sources and Probes Editor window:

■ The stat_rd_rdat_sync signal is high, which indicates that the DPA is locked and the system is ready to function.

■ The err_rd_dip4 signal is low, which indicates that there are no error in the data channels.

■ The err_tis_dip2_1 signal is low, which indicates that the status channel is properly received

9. On the File menu, click Open, navigate to \<directory>\stp1.stp, and click Open. The SignalTap II logic analyzer window appears. Observe and analyze more signals activity in the SignalTap II logic analyzer window.

Figure 9. In-System Sources and Probes Editor



Figure 10. SignalTap II Logic Analyzer



Simulating the Reference DesignThis section describes the RTL simulation testbench and the simulation results of the reference design. The RTL simulation testbench provides you with the RTL design verification at software level before implementing the reference design onto the development board. The reference design provides a simple testbench for loopback environment between the transmitter MegaCore function and the receiver MegaCore function. The simple testbench generates a 50 MHz clock, a 125 MHz clock, and a cpu_resetn active low reset signal toggling.

To run the simulation of the reference design in the ModelSim-Altera software, perform the following steps:

1. Download SPI4_LoopBack.zip and extract the file to the C:\ directory only.

1 Simulation does not work if you extract the .zip file to any other directory. If you do so, you must manually modify the .do script for the simulation to work.

2. Start the ModelSim-Altera software.

3. On the File menu, click Change Directory.

4. Select the folder located at the C:\SPI4_LoopBack\simulation\modelsim path, in which you unzipped the files. Click OK.

5. Click and place the cursor at the ModelSim command prompt.

6. On the File menu, click Load.

7. Select the top_run_msim_rtl_verilog.do file and click Open. This is a script file for the ModelSim-Altera software that automates all necessary settings for the simulation.

8. Verify the results shown in the Waveform Viewer window. You can rearrange signals, remove signals, add signals and change the radix by modifying the script in top_run_msim_rtl_verilog.do accordingly.



Simulation ResultsThe following sequence describes how the data packets are transmitted from the transmitter MegaCore function to the receiver MegaCore function, and the sequence corresponds to the numbered items in Figure 11:

1. The system PLL is locked when the pll0_locked signal is asserted.

2. The transmitter MegaCore function fast PLL ctl_tx_pll_areset signal is deasserted. This signal behavior asserts the stat_tx_pll_locked signal, which indicates that the transmitter MegaCore function fast PLL is locked.

3. The ctl_rx_pll_areset signal is deasserted while the stat_rx_pll_locked signal is asserted, which indicates that the receiver MegaCore function fast PLL is locked.

4. The system initialization state machine releases the tx_reset_n and rx_reset_n signals. The transmitter MegaCore function and receiver MegaCore function logic comes out of reset and send training patterns to the receiver MegaCore function.

5. During the synchronization phase, the err_rd_dip4 signal toggles.

6. The stat_rdat_sync_d signal is asserted, which indicates that the receiver MegaCore function is in sync with the transmitter MegaCore function data path. The err_rd_dip4 signal no longer toggles after the stat_rd_rdat_sync_d signal is asserted. This signal behavior indicates that no DIP-4 error is found in the data packets that are received. The data packets that are transmitted are similar to the data packets that are received in the receiver MegaCore function.

7. The Atlantic Master module sends data packets to the transmitter MegaCore function. The transmitter MegaCore function sends SPI-4.2 data packets over to the receiver MegaCore function.


AN 606: POS-PHY Level 4 (SPI-4.2) Loopback Reference DesignPage 23

Getting Started

© M

ay 2010Altera Corporation

AN 606: POS-PHY Level 4 (SPI-4.2) Loopback Reference Design

[6]

3.30us 3.35us 3.40us 3.4

F000 0FFF F000 0FFF F000 0FFF F000 0FFF F000 0FFF F000 0FFF F000 0FFF F000

F000 0FFF F000 0FFF F000 0FFF F000 0FFF F000 0FFF F000 0FFF F000 0FFF F000

30.0us

[7]

Figure 11 shows the simulation waveform of the reference design.

.

Figure 11. Simulation Waveform

[1] [2] [3][4] [4]

[5]

500ns 550ns 600ns 650ns 700ns 750ns 800ns 2.80us 3.10u 3.25us

tdclktctl

tdat[15:0]cpu_resetclk_125m

tsclktstat[1:0]

rdclkrctl

rdat[15:0]pll0_refclk

rsclkrstat[1:0]

dip_switch0dip_switch1dip_switch2dip_switch3pll0_locked

pll0_refclk_internalreset_n_pad

rxsys_clktrefclk

URRENT_STATE[2:0]txreset_nrxreset_n

ctl_rx_pll_aresetctl_tx_pll_areset

stat_tx_pll_lockedstat_rx_pll_locked

stat_rd_rdat_sync_derr_rd_dip4

first_rd_rdat_synctdint_clk

txinfo_aot[12:0]a0_arxval

a0_atxdava0_atxena

a0_atxdat[127:0]a0_atxsopa0_atxeop

a0_atxmty[3:0]a0_atxerr

a0_atxadr[7:0]stat_td_fifo_empty0

0000 000F 0FFF F000 0FFF F000 0FFF F000 F000 0FFF F000 0FFF F000 F000 0FFF F000 0FFF F000 0FFF F000 0FFF

0 3

0000 000F 0FFF F000 0FFF F000 0FFF F000 F000 0FFF F000 0FFF F000 F000 0FFF F000 0FFF F000 0FFF F000 0FFF

0 3

1 2 3 4 5

00000000000000000000000000000000

Revision History

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Copyright © 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ConclusionThis application note provides ways to use the loopback reference design with the Stratix IV GX or Stratix III FPGA board and HSMC. You can use this reference design to evaluate the operation and robustness of the POS-PHY Level 4 MegaCore function for integration into Stratix IV and Stratix III FPGA designs.

Revision HistoryTable 9 shows the revision history for this application note.

Table 9. Document Revision History

Date and Revision Changes Made Summary of Changes

May 2010

version 1.0

Initial release. —

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http://www.altera.com/support

Documents

POS-PHY Level 4 (SPI-4.2) Loopback Reference Design · 2020. 11. 12. · development kits. This reference design uses two instances of the POS-PHY Level 4 MegaCore function, the POS-PHY