Polysilicon MOSFET as a SpinFET base

• Current technology uses electron charge

• Spin MOSFET, SpinFET, manipulates charge and spin of electron

• Fabrication of necessary feature sizes currently requires SEM nano-lithography– Mainstream lithography options available by

2020

NMOSFET Background

• Fabrication of polysilicon NMOSFET (NMOS) using a self aligning process

• NMOS is a four contact device.• MOS capacitor operates in four modes

– Accumulation– Flat band– Depletion– Inversion

• Fabrication accomplished in four processing steps.

• Possible 1um features in University of Utah microfab facility

• ITRS published projections estimate physical gate lengths on the order of 18nm by 2010.

Processing Steps

• Four patterning masks used in process:– Gate oxide– Polysilicon gates– Contact vias– Metal contact pads

• Additional steps required for doping and polysilicon deposition.

• Spin on Glass (SOG). This is applied using a standard spinner and then baked for one hour ramping the temperature from 250C to 400C.

• A metal pad is connected to the polysilicon gate for probing and bonding.

SpinFET Concept

• Traditional semiconductors make use of the electron charge but not its spin.

• SpinFET devices will utilize both the charge and spin of the electron to create a modified 2D electron system that is spin coupled.

• Poisson’s equation shows the potential at the Si-Si02 interface of a traditional MOS capacitor. Four regimes are considered including accumulation, flat band, depletion and inversion.

• In the SpinFET device, the 2D electron system will not be uniform but will have localized potential peaks that confine electrons in the inversion layer to lattice points at the Si-Si02 surface. Adjacent electrons will couple due to Coulomb repulsion and take opposite spins.

SpinFET Fabrication Steps

• Several additional processing steps are required to create a SpinFET device from an NMOSFET device. These steps occur after depositing phosphorus and before applying spin on glass

– Apply PMMA– Pattern spin lattice using SEM. Lattice features will be on the order of 20-50 nm.– Develop– Use reactive ion etching to etch lattice pattern through polysilicon and gate oxide

just slightly etching Si surface

Actual Devices

• Development of the polysilicon process required some refining and further characterizing various process parameters

– Polysilicon etch rates needed adjustment from SOP definitions.

– SOG etch rates were considerably faster than traditional field oxide etch rates. Experiment revealed etch rates of 10nm/sec.

– SEM alignment patterns were changed and new masks made to ensure proper focus of electron beam during patterning. New alignment marks were placed on top of a gate oxide layer to be at the same height as polysilicon gates.

Preliminary Characterization

• Test devices on the die include– Polysilicon resistors.

Measurements indicate a resistance of 1.2 ohms per square.

– Substrate to poly and poly to metal capacitors to test quality and thickness of oxide layers. Due to the drastically different etch rate for SOG no substrate contact is achieved.

• NMOSFET devices were measured before and after annealing. Standard MOS curves were not achieved. After annealing curves merged and appeared resistive.

• Analysis and discussion…

Conclusions

• Traditional CMOS fabrication using a polysilicon self aligning gate is mainstream.

• Minor adjustments to the CMOS fabrication process make possible the fabrication of a spin lattice device

• Small feature sizes currently achieved using e-beam lithography are projected to be mainstream by 2010. This makes large scale production of SpinFET technology possible within five years.

• Some of the theoretical predictions for SpinFET devices include decreased power consumption and superconductivity due to a bandgap structure controlled by an applied gate voltage.

Thank You!

Questions