PolyMUMPs_03092015

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MUMPsMUMPs

( ( Multi-user Manufacturing ProcessMulti-user Manufacturing Process ) )

Allows inexpensive access to siliconAllows inexpensive access to silicon

by sharing design on the same wafer by sharing design on the same wafer

PolyMUMPsPolyMUMPs

SOIMUMPsSOIMUMPsMetalMUMPsMetalMUMPs

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The baseline process of the the MUMPs program is the 3-layer

polysilicon surface micromachining process known as

PolyMUMPs

PolyMUMPS developed in Berkeley BSAC in the 80s

The basic process includes 8 lithography levels, and 7 physicallayers

– 2 mechanical and 1 electrical layer of polysilicon

– 2 sacrificial layers

– 1 electrical conduction– 1 electrical isolation layer

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• The baseline process of the the MUMPs® program

is the 3-layer polysilicon surface micromachining

process (“polysurf”) no!n as PolyMUMPs• The basic process inclu"es #$ lithography le%els&

an" ' physical layers mechanical an" * electrical layer of polysilicon

sacrificial layers

* electrical con"uction

* electrical isolation layer

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PolyMUMPs ProcessPolyMUMPs Process

Nitride Poly 0 1st Oxide Poly 1 2nd Oxide Poly 2 Metal

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Seven Physical LayersSeven Physical Layers

• +itri"e Isolation between substrate and electrical

surface layers

• Poly ,ero Electrical poly layer for ground plane or electrode formation.

Below the first mechanical layer

• irst o.i"e First sacrificial oxide layer, providing gap between poly1 andsubstrate/nitride

• Poly * First mechanical layer

• /econ" o.i"e econd sacrificial oxide layer, provides gap between second

and first polysilicon

• Poly econd mechanical layer

• Metal !rovides electrical connection to pac"age

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Eight Lithography LevelsEight Lithography Levels

• P012 450 #efines the polysilicon $ero features

• 6+7805 * 0pens points%of%contact between first polysilicon and substrate &nitride

or poly '(

• 9:MP14 ;enerates )bumps) in under%surface of poly 1 to minimi$e stiction

• P012 * 9efines first polysilicon features

• P012*<P012<=:6 0pens points%of%contact between first and second polysilicon

• 6+7805 0pens points%of%contact between second polysilicon and

substrate/nitride

• P012 9efines second polysilicon features

• M4T61 9efines location of metal features

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Common Layout Terminology Common Layout Terminology

• 1ayer a physical layer of material "eposite" "uring the fabrication

process

• 6l!ays represente" in mi.e"-case letters

• 14=41 a lithographic le%el use" to pattern a physical layer> :t may or may

not correspon" !ith a physical layer • e>g> poly*? P012*& but /econ" o.i"e is patterne" by both 6+7805 an"

P012*<P012<=:6• 6l!ays represente" in 76P:T61 letters

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• 9imples small& shallo! features in the un"ersi"e of the lo!er

polysilicon layer to minimi,e the area of contact bet!een

the polysilicon an" the substrate

• 7=9@ 7hemical =apor 9eposition a metho" of "epositing layers of material through the

interaction of gases at lo! %acuum an" increase"

temperature• 6 7=9 "eposition is generally conformal - follo!s closely the un"erlying

topography

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• P/;@ Phospho-silicate-glass a phosphorous containing silicon "io.i"e layer generate" by

7=9 an" use" for its fast etching properties

• /acrificial o.i"e a layer of fast etching silicon "io.i"e use" to "efine the

separation bet!een the mechanical layers an" the substrate

• 5:4@ 5eacti%e :on 4tching

a "ry physical or chemical etching metho" !hich remo%esspecific material through the interaction of gas an" plasma !ith

the !afer surface

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• /tringer a ribbon of material left behin" after an 5:4 etch step>

;enerally create" at a topographic e"ge

• 1ift-off a metho" of "epositing metal !hich uses a polymer

template> The si"e!all profile of the polymer is "efine"

such that the continuity of the "eposite" metal is

interrupte" by the step& an" subseAuent insertion into a

sol%ent bath remo%es the polymer layer an" the metal

resi"ing upon it

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• 5elease the last step of the process !here the sacrificial layers are

remo%e" by submersion into 8

• /tiction the sticing effect bet!een polysilicon an" the substrate

!hich occurs "uring the remo%al of the sacrificial o.i"e>

Many attempts to limit stiction& inclu"ing "imples& special

release chemicals an" processes& are trie"& some

successfully

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Why Design Rules?Why Design Rules?

• 9esign rules "efine configurations that are

allo!e" an" those !hich are not

• 9etermine" by normal manufacturing

limitations (process !in"o!) Minimum resolution of the lithography system

6lignment bet!een le%els

Topography effects of multiple layers

4tch reAuirements• /electi%ity bet!een materials

• 4tch rates

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MUMPs® Design RulesMUMPs® Design Rules

• Most process rules in MUMPs® are

Ba"%isoryB !arn of possible negati%e interactions

must be taen in conte.t of the "esign

%iolations are at UserCs ris

• 6 fe! rules are man"atory an" may not be

%iolate"

Minimum line an" spaces - "etermine" bylithographic resolution

6 fe! interle%el interactions - reAuire" by process !in"o!

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POCl3 diffusion

Silicon Substrate


• 8ea%ily "ope" +D layer "iffuse" into

surface of starting !afer Minimi,es charge fee"-through on !afer surface

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Poly 0Nitride

POCl3 diffusion

Photoresist

Silicon Substrate


• 1o! stress nitri"e an" poly ,ero layers are

"eposite" (blanet)> Eafer is spin coate"

!ith photoresist& a U= photo-imagable

material>

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Poly 0Nitride

POCl3 diffusion

Photoresist

Silicon Substrate

Reactive Ion Etch (RIE)


• The photoresist is e.pose" using the firstmas le%el (P012F) an" the image is"e%elope">

• The e.pose" polysilicon is then remo%e" by

5:4 etching& transferring the P012F patternonto the !afer>

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Poly 0

Nitride

POCl3 diffusion

Silicon Substrate


• The photoresist is strippe" in sol%ent after

etch>

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POCl3 diffusion

Di!les

Nitride" Poly 0

Photoresist

Silicon Substrate

1st Oxide


• The first o.i"e layer (>F Gm) is "eposite"

on the !afer by lo! temperature 7=9>

• The !afer is coate" !ith photoresist an"

secon" mas le%el (9:MP14) is e.pose"an" "e%elope">

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RIE

POCl3 diffusion

Di!les

Nitride" Poly0

Photoresist

Silicon Substrate

1st Oxide


• The "imple photoresist is strippe" an" a ne!

layer of photoresist is applie" for the thir"

mas le%el (6+7805*)> The first o.i"e is

patterne" an" then processe" through 5:4 toremo%e the o.i"e from the anchor area>

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Nitride" Poly0

POCl3 diffusion

Silicon Substrate

1st Oxide


• The photoresist is strippe" in a sol%ent bath

an" the !afer is rea"y for poly * processing>

• 6+7805* "efine" !here poly * !ill be

attache" to the substrate& an" the thicnessof the first o.i"e "efines ho! far abo%e the

substrate (either nitri"e or polyF) poly * !ill

sit after release>

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#st O$ide"" Poly0" NitridePOCl3 diffusion

Silicon Substrate

PS% hard as&

Poly #


• 6fter the !afer is cleane"& the first

polysilicon layer is "eposite" by 1P7=9>

6n a""itional thin P/; layer is "eposite" on

top of the poly * an" the !afer is anneale" athigh temperature to re"uce the resi"ual

stress an" "ope the poly *>

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1st Oxide"" Poly0" NitridePOCl3 diffusion

Silicon Substrate

Photoresist

PS% hard as&

Poly #


• The !afer is coate" !ith photoresist an" the

fourth mas (P012*) is patterne"> The

!afer is 5:4 etche"& stopping on the first

o.i"e& using both the photoresist an" thinP/; (top) layer as mass for the poly *

layer>Etch

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1st Oxide"" Poly0" Nitride

Silicon Substrate

'nd O$ide

Poly #

Poly # e$!osed by

PO#*PO'*+I, etchPoly # e$!osed by

PO#*PO'*+I, etch



fifth mas (P012*<P012<=:6) is

patterne" an" 5:4 etche"> This "efine" the

contact regions bet!een poly * an" poly >

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Silicon Substrate

Photoresist

#st and 'nd O$ides etched by ,NC-OR' etch


'nd O$ide

Poly #

• The photoresist is strippe" an" the !afer is

recoate"> The si.th mas (6+7805) is patterne"

an" both first o.i"e an" secon" o.i"e are etche" in

one step> This "efines the region !here poly !ill

contact the substrate (either nitri"e or polyF)>

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POCl3 diffusion

Silicon Substrate

1st Oxide

PO#*PO'*+I, cutPO#*PO'*+I, cut

,NC-OR' cut


'nd O$ide

Poly #


• The photoresist is strippe" an" the !afer is

rea"y for poly "eposition>

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POCl3 diffusion

Silicon Substrate

Poly '

PS% hard as&

1st Oxide, Poly0" Nitride

Poly #

• The secon" polysilicon layer is "eposite" follo!e"

by a thin P/; layer> The is anneale" to re"uce the

poly stress an" "ope the poly > Hecause the 7=9

film is conformal& all the holes !ill be fille"& to

%arying "egrees& !ith poly >

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POCl3 diffusion

Nitride

Silicon Substrate

Poly 1

Poly 2

PSG hard mask

Photoresist


se%enth mas (P012) is patterne"> Hoth the

photoresist an" thin P/; (har" mas) !ill mas the

5:4 etch>

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POCl3 diffusion

Nitride

Silicon Substrate

Poly 1

Poly 2

1st Oxide

2nd Oxide


• 6fter the poly layer is etche" an" the

!afer is strippe"& the basic mechanical

structure is complete>

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POCl3 diffusionNitride

Silicon Substrate

Poly 1

Poly 2

PhotoresistMetal

Metal


• 6 lift-off template is use" to "eposit the metal layer

on the !afer> Photoresist is patterne" using the

eighth (an" ninth) mass (M4T61) an" the metal is

"eposite"& a"hering to the poly & !here e.pose"&

an" breaing continuity as it goes o%er the photoresist step>

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POCl3 diffusion

Silicon Substrate

Metal

Metal


• The photoresist an" remnant metal are

remo%e" by rinsing in sol%ent> The structure

is no! complete" an" rea"y for releasing>

NitridePoly 1

Poly 2

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POCl3 diffusionNitride

Silicon Substrate

Poly #

Poly '.etal

Poly 0


• 6 minute soa in concentrate" 8

remo%es all the sacrificial o.i"e layers an"

releases the mo%eable mechanical parts> The

rotor is no! free to spin about the center pin&an" the stator poles are fi.e" an"

electrically acti%e>

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Release using Hydrofluoric Acid Release using Hydrofluoric Acid

• 5emo%e the protecti%e photoresist layer in a

sol%ent bath

• :mmerse chips in a bath of straight JKL 8

at room temperature for >I minutes torelease the structures

• 5inse chips in 9: !ater& follo!e" by

soaing in isopropyl alcohol an" baing in a

con%ection o%en

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!M Cross ection!M Cross ection

Poly2 Undercut

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Bread-loafing of Ox2

KeyholePoly2 Stringer

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Poly Stringers

Documents

PolyMUMPs_03092015