PLL-based high-speed demodulation of FM signalsfor real-time AFM applications

Benedikt Schlecker, Maurits Ortmanns and Jens AndersInstitute of Microelectronics

University of UlmD-89081 Ulm, Germany

Email: benedikt.schlecker@uni-ulm.de,maurits.ortmanns@uni-ulm.de, jens.anders@uni-ulm.de

Georg FantnerLaboratory for Bio- and Nano-Instrumentation

Ecole Polytechnique Federale de LausanneCH-1015 Lausanne, Switzerland

Email: georg.fantner@epfl.ch

Abstract—In this paper we present a new architecture for PLL-based high-speed demodulation of frequency-modulated AFMsignals. In our approach, we use single-sideband frequency up-conversion to translate the AFM signal from the position sensitivedetector to a fixed intermediate frequency of 10 MHz. In this way,we fully benefit from the excellent noise performance of PLL-based FM demodulators still avoiding the intrinsic bandwidthlimitation of such systems. Furthermore, the system becomesindependent of the cantilever’s resonance frequency. To inves-tigate if the additional noise introduced by the single-sidebandupconverter degrades the system noise figure we present a modelof the AM-to-FM noise conversion in the PLL phase detector.Using this model, we can predict an upper corner frequency forthe demodulation bandwidth above which the converted noisefrom the single-sideband upconverter becomes the dominantnoise source and therefore begins to deteriorate the overallsystem performance. The approach is validated by measured dataobtained with a PCB-based prototype implementing the proposeddemodulator architecture.

I. INTRODUCTION

Recently, atomic force microscopy (AFM) has gained sig-nificant attention in the field of life science as a tool forstudying biological structures at the cellular and subcellularlevel. In contrast to conventional AFM applications in ma-terial science where imaging time is of minor importance,in biological AFM applications people are often interestedin high temporal resolutions in order to study biologicalprocesses with relatively fast time scales such as the dy-namic behavior of proteins. Since it has been shown that theminimum detectable force gradient in amplitude modulated(AM) AFM is proportional to 1/

pQ, where Q is the quality

factor of the utilized cantilever, high-resolution AM AFMintrinsically requires the use of high-Q cantilevers. However,the frequency response of the cantilever motion with respectto amplitude variations is limited by the same quality factorresulting in an inevitable resolution-bandwidth tradeoff in AMAFM. In frequency modulated (FM) AFM this resolution-bandwidth tradeoff does not exist because the cantilever canrespond instantaneously, i.e. without bandwidth limitations, toperturbations in its oscillation frequency [1] and [2] and thetheoretically achievable bandwidth in this operating mode iseventually only limited by the cantilever resonant frequencyitself. Therefore, in order to fully benefit from this large

theoretically achievable bandwidth there is need for high-speedFM demodulators which can provide both the excellent noiseperformance required in AFM applications and demodulatesignals with modulation bandwidths as large as the cantileverresonant frequency.

To account for both of these contradicting design goals,we propose the use of a single-sideband (SSB) upconverter incombination with a subsequent phase-locked loop (PLL) basedFM demodulator. Thanks to their closed-loop structure, PLL-based FM demodulators show the best noise performance ofall available FM demodulator architectures [3]. However, theirdemodulation bandwidth is limited to a value between one fifthand one tenth of their input carrier frequency [3]. Therefore, astandalone PLL-based FM demodulator cannot be used whenattempting to fully exploit the available signal bandwidthprovided by the cantilever. To overcome this problem, we usean SSB upconverter which translates the center frequency ofthe AFM signal from the cantilever resonant frequency to anintermediate frequency (IF) of 10 MHz without introducing afrequency component at the so-called image frequency whichcould perturb the lock-in process of the subsequent PLL. Inthis way, we can select a PLL bandwidth of 1 MHz and itbecomes possible for cantilevers with resonance frequenciesbelow 1 MHz to fully exploit their intrinsic bandwidth forhigh-resolution AFM with high frame rates.

The paper is organized as follows: In section II, we presenta detailed overview of the proposed FM demodulator archi-tecture. Section III then deals with the problem of AM-to-FM noise conversion in the PLL phase detector (PD) and wepresent an analytical model which allows the prediction of themaximally achievable demodulation bandwidth without SNRdegradation due to the additional AM noise introduced by theSSB modulator. We then present the details of a PCB-basedprototype of the proposed architecture in section IV and showmeasured results obtained with this prototype in section V. Weconclude the paper with a short summary and a brief outlookon future work in section VI.

II. SYSTEM OVERVIEW

The architecture of the proposed highspeed FM demodu-lator is shown in Fig. 1. According to the figure, the AFM

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PPF PLL0°/90°-

Quadrature modulator

0°

90°BP

Fig. 1. Illustration of the proposed system architecture.

signal coming from the position sensitive detector is fedinto a polyphase filter which generates the quadrature signalsrequired for the subsequent SSB upconversion. The SSBupconversion itself is then performed by means of a quadraturemodulator which contains two mixers driven by quadrature LOsignals. By adding or subtracting the outputs of the two mixers,the lower sideband (LSB) and the upper sideband (USB)can be selected, respectively. In order to limit the amountof integrated AM noise at the PLL input, the quadraturemodulator is followed by a bandpass filter centered aroundthe IF frequency. The output of the bandpass filter then drivesthe input of the PLL-based FM demodulator.

III. PLL NOISE MODEL

xin(t)

xVCO(t)

xout(t)=g(xin(t),xVCO(t))

g(.)

PD

(a)

Θin

xout(t)=Kd[g’(Δ θ)+n’(t)]

g’(.)

-

ΘVCO

Kd

n’(t)

equivalent PD

phase domain model

(b)

Fig. 2. (a) PD with noisy inputs and (b) equivalent PD phase domain modelwhich transforms the noise at the PD input into an equivalent phase noiseprocess n0(t) at the PD output.

An ideal FM demodulator is insensitive to AM noise in itsinput signal. However, any real FM demodulator converts afraction of the amplitude noise at its input into frequency noiseand, therefore, care has to be taken in the design process thatthe addition of the SSB modulator, which can significantlyincrease the amplitude noise level at the PLL input, doesnot degrade the overall system noise figure. Since in a PLL-based FM demodulator the AM-to-FM noise conversion takesplace in the phase detector, in this section, we will present ananalytical model which predicts the contribution of the variousnoise sources inside the PLL-based demodulator to the PLL’sinput referred frequency noise including the contribution fromamplitude noise at the PD input. To this end, we replace thePD with its input signal xin(t) = Ain sin(!0 t+✓in)+n(t) =

˜

Ain(t) sin(!0 t + ✓in + ✓n(t)) perturbed by both amplitudenoise and phase noise using the equivalent circuit depicted inFig. 2(b) by a phase domain model with a noise free input anda transformed noise process n0

(t) [4]. In the figure, g(·) is thenonlinear phase transfer characteristic of the employed phasedetector, the prime symbol indicates transformed quantitiesand Kd is the equivalent conversion gain of the phase detector.Applying the procedure outlined in [4] to a phase frequencydetector (PFD), we obtain for the transformed quantities:

g

0(�✓) = 4

1X

⌫=1

(�1)

⌫+1µ⌫

⌫

sin (⌫�✓) (1a)

µ⌫ = E [cos (⌫ ✓n)] =1

2

p⇡CNRexp

✓�CNR

2

◆

I

⌫�12

✓CNR

2

◆+ I

⌫+12

✓CNR

2

◆�(1b)

CNR =

˜

A

2in

2�

2n

(1c)

SN 0N 0(j!) =

�

2n0

Bn0(1d)

�

2n0 = E

⇥g

2(✓n)

⇤=

⇡Z

�⇡

✓

2n p(✓n)d✓n

=

⇡

3

3

+ 4

1X

⌫=1

(�1)

⌫ µ⌫

⌫

2(1e)

Bn0 ⇡ Bn

h1 + 0.35 exp

⇣�CNR

h1� ⇡

4

i⌘i, (1f)

where µ⌫ is the so-called signal suppression factor [4], I⌫(·)is the modified Bessel function of order ⌫, CNR is the inputcarrier to noise ratio, �n is the variance of the additiveinput amplitude noise process n(t), �

0n is the variance of

the transformed noise process n

0(t), Bn0 is the equivalent

noise bandwidth of n0(t) and SN 0N 0

(j!) is the power spectraldensity of n

0(t). The equivalent phase detector model of

Fig. 2(b) can be incorporated into the standard phase domainPLL model according to Fig. 3 where all noisy componentsare replaced by additive equivalent noise sources [3] and [5].Assuming moderate fluctuations due to noise, the nonlinear PDtransfer characteristic can be linearized around its operatingpoint using the equivalent gain K

0d [4] or [5]. For the PFD

employed here K

0d is given by:

K

0d =

dg

0(�✓)

d�✓

�����✓=0

= 4

1X

⌫=1

(�1)

⌫+1µ⌫ . (2)

Using this model, we have performed numerical simulationsin MATLAB to compute the contribution to the input referredfrequency noise of each noise source. For our simulations wehave used the loop filter topology shown in Fig. 4 which wealso implemented in the PCB-based prototype discussed insection IV, whose transfer function F (s) is given by:

Kd F (s) =

ICP

2⇡

b� 1

b

R3

R3 +R4

1 + s ⌧1�1 +

s ⌧1b

�sC1

1

1 + s ⌧out,

(3)

198

θin

÷N

θn,VCO

θn,div

vn,PD vn,LFvout

F(s)-

KVCO/s

n’

KdK’

Fig. 3. PLL model incorporating the linearized PD model of Fig. 2(b) andadditive noise sources for all remaining noise contributors.

where ICP is the charge pump current, b = 1 + C1/C2,⌧1 = R1 C1 and ⌧out = R2 C3. Simulation results of the inputreferred frequency noise spectral density for three differentinput amplitude noise levels are shown in Fig. 5. The modelparameters used for the simulation are listed in the figurecaption. In the figure, we see that for low frequencies theinput referred frequency noise is dominated by the VCO noiseand that a corner frequency exists at which the transformedamplitude noise becomes the dominant noise source and afterwhich the total input referred frequency noise increases witha slope of 20 dB/dec.

R1

R2

R3

R4

C1

C2

C3

Iin(s)Vout(s)

Fig. 4. Schematic of the utilized loop filter topology. Capacitors C1 and C2and resistor R1 transform the current from the PFD charge pump combinationinto a voltage and the remaining circuitry provides a further pole which canincorporate the large load capacitance of the discrete VCO.

IV. PCB-BASED PROTOTYPE

In order to validate the proposed demodulator architectureexperimentally, we have designed and fabricated a PCB-basedprototype with discrete off-the-shelf electronics. The annotatedlayout of this prototype illustrating the different buildingblocks is shown in Fig. 6. In order to be compatible withstandard AFMs, the prototype design incorporates an inputstage which adjusts the signal amplitudes coming from theposition sensitive detector to the levels required for the on-board signal processing. The polyphase filter (PPF) generatesthe quadrature signals required for the single-sideband modu-lation. It consists of 8 stages to achieve the required minimumimage rejection ratio (IRR) of about 26 dB (corresponding to anoise figure of 0.01 dB due to noise coming from the unwantedsideband) over its bandwidth from 1 kHz to 3 MHz. With thisPPF bandwidth, the system can work with cantilevers with

Fig. 5. Simulation results for the input referred frequency noise of thePLL-based FM demodulator for three different levels of AM noise at thePLL input. The remaining simulation parameters correspond to the PCBbased prototype described in section IV and are given by: C1 = 11 pF,C2 = 876 pF, C3 = 1.233 nF, R1 = 1.47 k⌦, R2 = 12⌦, R3 = 1 k⌦,R4 = 220⌦, VCO: Minicircuits ROS-70-119+, PLL chip: Analog DevicesADF4002, charge pump current ICP = 5mA.

PPF

input stages

output stages

IQ-modulator

band-pass

VCO

PD

loopfilter

programming

power supply

Fig. 6. Annotated layout of the fabricated PCB-based FM demodulatorprototype.

vinp

vinn

vout,Ip

vout,In

vout,Qp

vout,Qn

R

C1

R

C1

R

C1

R

C1

R

C2

R

C2

R

C2

R

C2

R

Cn

R

Cn

R

Cn

R

Cn

Fig. 7. Schematic of the passive polyphase filter generating the quadraturesignals for the SSB modulator.

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resonance frequencies between about 10 kHz and 1.5 MHzand signal bandwidths close to the corresponding cantileverresonance frequency. Although the IRR could be improvedby a nonuniform placement of the PPF poles and zerosby about 1.5 dB [6] this improvement is not significant andeven further diminished by the tolerances of standard discretecomponents. Therefore, in the presented prototype the pole andzero locations are logarithmically distributed between 1 kHzand 3 MHz. The SSB modulator (LTC5598, Linear Technol-ogy) which upconverts the AFM signal to the intermediatefrequency fIF = 10MHz is followed by a passive bandpassfilter which removes out of band noise and interferences. TheLO signal required for the upconversion at a frequency offLO = fIF + fres, where fres is the resonance frequency ofthe cantilever, i.e. the center frequency of the AFM signal,is generated by an external signal source generator. ThePLL-based FM demodulator (PLL-chip: ADF4002, AnalogDevices, VCO: ROS-70-119+, Minicircuits) is designed fora demodulation bandwidth of 1 MHz and followed by tunableoutput stages with variable gain and bandwidth settings (gainsettings: 11, 51, 101, corner frequencies of 4th order But-terworth filters: 10 kHz, 250 kHz, 1.2 MHz) which allow thedemodulator to be adjusted for different cantilever resonancefrequencies and scan rates. In addition to the signal processingelectronics, the PCB also contains the electronics for a stableand low-noise supply voltage generation and a microcontrollerto program the ADF4002 through its SPI interface at power-up.

V. MEASUREMENTS

Fig. 8. Measured input referred frequency noise floor of the PCB-basedprototype for input center frequencies of 400 kHz and 2 MHz, respectively.

The measured input referred frequency noise of the proto-type described in the previous section is shown for the twodifferent center frequencies of 400 kHz and 2 MHz in Fig. 8.The spectrum was obtained by measuring the output referredvoltage noise of the PLL and dividing this voltage noise floorby the measured PLL closed-loop sensitivity of 140µV/Hz.From the figure we see that the noise is identical for the two

different input center frequencies. The spurious tone in thespectrum measured with an input center frequency of 400 kHzoriginates in the LO leakage of the LTC5598 modulator chip.It is due to an imperfect matching of the common mode levelsof the modulator’s baseband inputs and will be suppressedin future prototype generations by a trimming of these inputcommon mode levels. Overall, the measured frequency noisespectrum matches well (within a factor of 2.5) with the modelpresented in section III. For lower frequencies, it is dominatedby the VCO noise and the converted amplitude noise startsto dominate at a corner frequency of about 100 kHz. Theintegrated frequency noise in a 400 kHz bandwidth is about19 Hz.

VI. CONCLUSION AND OUTLOOK

In this paper, we have presented a new architecture forhigh-speed PLL-based FM demodulation for real-time AFMapplications incorporating an SSB modulator to allow the PLLto operate at a higher center frequency and thereby removeits intrinsic bandwidth limitation. We have identified the AMnoise additionally introduced by the SSB modulator whichis converted into frequency noise in the PLL PD as thelimiting factor for the achievable detection bandwidth of thesystem. The model of this AM-to-FM conversion presented insection III allows to quantify this limitation and account forit during the design phase. In section V, we have presentedmeasured results of a PCB-based prototype of the proposedsystem which both validates the PLL model of section IIIand provides a proof of principle that the proposed detectorarchitecture can indeed increase the PLL bandwidth withoutdeteriorating the system noise figure over a certain frequencyband. With its integrated frequency noise of about 19 Hz ina frequency bandwidth of 400 kHz, it can safely demodulateAFM signals originating from a cantilever with a resonantfrequency of 400 kHz and the corresponding maximum scanrate. However, due to the positive slope of the frequency noisefloor originating from the transformed AM noise, the presentedprototype cannot demodulate frequencies much higher than400 kHz. Therefore, we are currently working on an improvedprototype with a lower AM noise floor which will allow towork with even higher cantilever resonant frequencies and thecorresponding increased demodulation bandwidths.

REFERENCES

[1] R. L. Stratonovich, Topics in the theory of random noise, ser. Mathematicsand its applications. New York: Gordon and Breach, 1963.

[2] J. Anders, M. Ortmanns, and G. Boero, “Noise in frequency-sensitive esrdetectors,” in Proceedings of the MATHMOD 2012, Vienna.

[3] F. M. Gardner, Phaselock techniques, 3rd ed. Hoboken, NJ: John Wiley,2005.

[4] W. Rosenkranz, “Phase-locked loops with limiter phase-detectors in thepresence of noise,” Ieee Transactions on Communications, vol. 30, no. 10,pp. 2297–2304, 1982.

[5] H. Meyr and G. Ascheid, Synchronization in digital communications, ser.Wiley series in telecommunications. New York: Wiley, 1990.

[6] J. Kaukovuori, K. Stadius, J. Ryynanen, and K. Halonen, “Analysis anddesign of passive polyphase filters,” IEEE Transactions on Circuits andSystems I: Regular Papers, vol. 55, no. 10, pp. 3023–3037, November2008.

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