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Plasma interconnects and circuits for logic gates and computer sub-circuits Pradeep Pai and Massood Tabib-Azar Citation: Applied Physics Letters 104, 244104 (2014); doi: 10.1063/1.4884421 View online: http://dx.doi.org/10.1063/1.4884421 View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/104/24?ver=pdfcov Published by the AIP Publishing Articles you may be interested in Computational modeling of droplet based logic circuits AIP Conf. Proc. 1479, 220 (2012); 10.1063/1.4756102 Realization of reliable and flexible logic gates using noisy nonlinear circuits Appl. Phys. Lett. 95, 194102 (2009); 10.1063/1.3245318 Device study, chemical doping, and logic circuits based on transferred aligned single-walled carbon nanotubes Appl. Phys. Lett. 93, 033101 (2008); 10.1063/1.2956677 Reliability analysis method for low- k interconnect dielectrics breakdown in integrated circuits J. Appl. Phys. 98, 034503 (2005); 10.1063/1.1999028 Circuit and technique for characterizing switching delay history effects in silicon-on-insulator logic gates Rev. Sci. Instrum. 75, 768 (2004); 10.1063/1.1647697 This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP: 130.39.62.90 On: Wed, 03 Sep 2014 10:32:54

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Page 1: Plasma interconnects and circuits for logic gates and computer sub-circuits

Plasma interconnects and circuits for logic gates and computer sub-circuitsPradeep Pai and Massood Tabib-Azar

Citation: Applied Physics Letters 104, 244104 (2014); doi: 10.1063/1.4884421 View online: http://dx.doi.org/10.1063/1.4884421 View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/104/24?ver=pdfcov Published by the AIP Publishing Articles you may be interested in Computational modeling of droplet based logic circuits AIP Conf. Proc. 1479, 220 (2012); 10.1063/1.4756102 Realization of reliable and flexible logic gates using noisy nonlinear circuits Appl. Phys. Lett. 95, 194102 (2009); 10.1063/1.3245318 Device study, chemical doping, and logic circuits based on transferred aligned single-walled carbon nanotubes Appl. Phys. Lett. 93, 033101 (2008); 10.1063/1.2956677 Reliability analysis method for low- k interconnect dielectrics breakdown in integrated circuits J. Appl. Phys. 98, 034503 (2005); 10.1063/1.1999028 Circuit and technique for characterizing switching delay history effects in silicon-on-insulator logic gates Rev. Sci. Instrum. 75, 768 (2004); 10.1063/1.1647697

This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP: 130.39.62.90

On: Wed, 03 Sep 2014 10:32:54

Page 2: Plasma interconnects and circuits for logic gates and computer sub-circuits

Plasma interconnects and circuits for logic gates and computer sub-circuits

Pradeep Pai and Massood Tabib-Azara)

Department of Electrical and Computer Engineering, University of Utah, Salt Lake City, Utah 84112, USA

(Received 3 April 2014; accepted 4 June 2014; published online 18 June 2014)

Logic gates using plasma-linked microplasma devices are demonstrated in this work. The

space charge around a microplasma was used to lower the breakdown voltage of nearby device

by 20–40 V. This mechanism was used to establish electrical connection between neighboring

microplasma devices without the use of metallization traces. The decay lengths of the space charge

were in the range of 178–400 lm depending on the type of gas used. He and Ar gases were used at

atmospheric pressure to evaluate the effect of gas species on the space charge decay length.

Plasmas can be used to connect devices in 3 dimensions, and their decay constant can be adjusted

using pressure, boundary conditions, and gaseous species. Using plasma interconnects, universal

gates including OR, AND, NOT, and XOR and computer sub-circuits such as 1 bit adders were

designed and characterized. VC 2014 AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4884421]

Plasmas are used for a variety of applications at both

macro and micro scales.1,2 Most of the applications that use

plasma utilize its optical, thermal, and high current switch-

ing properties. In recent years, there has been interest to de-

velop passive3,4 and active plasma sensors and electronic

components.5–10 Programmable antennas, radiation hard

electronics, smart flight skins, plasma metamaterial energy

management skins are all but a few examples of devices

and systems that are being investigated. The advantage of

plasma-based electronic devices over semiconductor devi-

ces is in their ability to withstand high temperature

(>300 �C) and ionizing radiation conditions.5 The micro-

plasma switches and transistors reported in the past mainly

operated as analog devices. Here, we further develop the

applications of microplasma devices (lPDs) in digital cir-

cuits and introduce a method of electrically connecting

lPDs to realize digital logic gates and circuits using the

spatial decay characteristics of plasmas.

We demonstrated logic gates using microplasmas in our

recent work,11 using diode-resistor logic approach and metal

interconnect. The space-charge surrounding microplasmas

was used in the past to modify the breakdown voltage and

demonstrate AND logic operation for switching pixels in

plasma display panels.12 The AND operation was achieved

through a combination of plasma space charge effect and

time-controlled switching. In our work presented here, the

switching is completely based on the effect of space charge

that electrically connects lPDs to form logic gates withoutany metal interconnects. Once the plasma is turned off, the

functional electrical link between the input and the output is

completely lost. Moreover, different logical operations can

be performed using identical devices and inter-device distan-

ces by simply changing the plasma characteristics (density,

temperature, and spatial decay constant) electronically. This

would allow a user to dynamically program the functionality

of lPD circuits in real-time.

To realize logical operations, lPDs were placed in close

proximity to each other so that when a device was turned on,

the nearby devices’ breakdown voltage was lowered by the

presence of the space-charge produced by the adjacent de-

vice. The logic states of the input and output depended on

the plasma being ON or OFF. When the plasma was OFF

(ON), we obtained the logic “0” (“1”) state. The devices

were fabricated using electroplated Cu electrodes with a sep-

aration gap of �5 lm (Figs. 1(a) and 1(b)).

The space-charge region at the boundary of the plasma

is similar to the Debye sheath that separates the charge-

neutral inner plasma region from the outside. Under dc exci-

tation, plasma develops a positive space charge boundary

due to accumulation of heavier ions.13 This positive space

charge induces an opposing negative charge through elec-

trons in the surrounding neutral gas region. The effect of

these seed electrons on the breakdown voltage of a central

device EP2 in Fig. 1(a) was determined while generating

plasma in nearby devices EP1, EP3. All measurements in

this work were carried out at atmospheric pressure in He.

The current was limited to 100 lA in most of our measure-

ments to minimize damage to the cathode from ion sputter-

ing. The breakdown voltage for EP2 was 210 V when both

EP1 and EP3 were OFF (Fig. 1(d)). Turning either EP1 or

EP3 ON lowered the EP2 breakdown voltage to 190 V. The

breakdown voltage was lowered further to 182 V when both

EP1 and EP3 were ON.

We note that the breakdown voltage (Vb) of a gas at

small inter-electrode spacing (d) is determined by the

Townsend condition14

ðci þ c0Þ½eApd expð�Bpd=VbÞ � 1� ¼ 1; (1)

where ci is the secondary emission co-efficient for bombard-

ing ions, c0 is the secondary emission co-efficient for ion-

enhanced field emission,14 A and B are gas constants, and pis the gas pressure. For inter-electrode spacing of less than

10 lm, the ion-enhanced field emission is the dominant cause

of gas breakdown and hence c0 � ci. ci� 0.0075, is a con-

stant for a given electrode material and gas species, whereas

c0 is a function of the applied electric field.14 The breakdown

a)Author to whom correspondence should be addressed. Electronic mail:

[email protected].

0003-6951/2014/104(24)/244104/4/$30.00 VC 2014 AIP Publishing LLC104, 244104-1

APPLIED PHYSICS LETTERS 104, 244104 (2014)

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Page 3: Plasma interconnects and circuits for logic gates and computer sub-circuits

voltage of He for different inter-electrode spacing was exper-

imentally obtained and modeled in our earlier work.10 A

breakdown voltage of 210 V shown in Fig. 1(d) corresponds

to electrode spacing of �4 lm. The value of c0 for 4 lm elec-

trode spacing is calculated to be 0.067, which translates to

0.067 electrons emitted for every ion. In the presence of seed

electrons generated by space-charge of a nearby device, Eq.

(1) can be modified to obtain the new breakdown voltage as

ðcs þ ci þ c0Þ½eApd expð�Bpd=VbÞ � 1� ¼ 1; (2)

where cs is the electrons available per ionizing collision due

to space-charge. The breakdown voltage of EP2 reduced

from 210 V to 190 V when EP1 or EP3 was turned ON.

Substituting this new breakdown voltage into Eq. (3), we get

cs¼ 0.074 (compare c0 ¼ 0.067). This implies that there are

0.074 additional electrons available per ionizing collision,

which results in a lower breakdown voltage. Similarly, the

breakdown voltage reduced from 210 V to 182 V when both

EP1 and EP3 were turned on, which corresponds to

cs¼ 0.084. cs is a function of the charge density on the

plasma electrodes and the spacing between adjacent electro-

des, which consequently affects the breakdown voltage.

The spatial range of the space charge surrounding

plasma was determined by measuring conductance of the gas

surrounding the plasma electrodes at distances varying from

100 to 500 lm. The effect of different gases was determined

using He and Ar mixtures as noted in Fig. 2. The charge den-

sity (Cp) as a function of distance can be calculated using the

Fick’s law, and it is approximately given by the exponential

relation

CPðrÞ ¼ CPð0Þ: exp

�� r

l

�; (3)

where “r” is the distance from the plasma source (Fig. 1(a))

and “L” is the charge diffusion length.

Fig. 2(a) shows the conductance of EP0 (Fig. 1(a)) as a

function of the distance to other devices at distance “r” that

were subsequently turned “ON” with: (i) pure Ar plasma, (ii)

pure He plasma, and (iii) 50% He–50% Ar. Fig. 2(a) clearly

shows that a nearby plasma affects the conductance and the

breakdown voltage of EP0. To understand the spatial-decay

of this plasma effect, we re-plotted the conductance-distance

in a log-linear scale in Fig. 2(b). In all three cases (i)–(iii),

two distinct decay regimes were observed as shown in

Fig. 2(b). Noting that the decay constant L is the plasma dif-

fusion length: L¼ (Ds)1/2, it can be seen that the two distinct

decay regimes are associated with two different diffusion

coefficients (D) and recombination lifetimes (s) associated

with (a) neutral part of the plasma and (b) space-charge

region in the plasma boundary created by the different elec-

tronic and ionic mobilities. In the space-charge region, the

diffusion lengths are higher than the charge-neutral regime.

This can be qualitatively understood by noting that the elec-

trons usually have larger mobility and smaller lifetime than

ions. Once electrons diffuse away, ions are left behind giving

rise to longer diffusion length observed in our devices. It is

also interesting to note that the decay constants of pure gas

plasmas are similar. In the long decay regime, the 50–50 gas

plasma had longer decay constant. The boundary layer

space-charge region usually has lower electron density than

the central and neutral part of the plasma. We also noted that

the conductance change due to nearby plasma almost linearly

increased as the plasma current was increased from 50 lA to

500 lA as shown in Fig. 2(c).

The above observations and the plasma hysteresis (once

it is turned “ON” it stays ON at voltages below the original

breakdown voltage) were used to design and implement

logic gates and a 1 bit adder as described below.

The OR logic operation was implemented using the

arrangement shown in Fig. 3(a). If the central device (X) is

biased at 195 V, the voltage would be insufficient to cause a

breakdown in the absence of any space charge. However, if

either Input A or Input B is turned ON, the space-charge

from their plasma will create plasma at X (Fig. 3(b)). After

X is turned ON, it does not turn OFF if the inputs A and B

FIG. 1. SEM micrograph of devices

used for logic gates (a). The adjacent

devices are separated by 100 lm. A

close-up of one of the electrode pairs is

shown in (b). The electrode configura-

tion used to determine the effect of

space charge on breakdown voltage of

nearby device is shown in (c). The ex-

perimental results are plotted in (d).

Inset shows optical images of the de-

vice during operation.

244104-2 P. Pai and M. Tabib-Azar Appl. Phys. Lett. 104, 244104 (2014)

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Page 4: Plasma interconnects and circuits for logic gates and computer sub-circuits

are turned OFF because the plasma at X remains self-

sustained at this stage. X can be turned OFF by turning down

the bias voltage significantly or turning it OFF. The output

voltage is valid only in the duration when the output bias is

high.

The AND logic was implemented with the same arrange-

ment of devices used for the OR operation by using a lower

bias voltage of 185 V across the output device X. The

response of the AND gate is shown in Fig. 4(a). The problem

with this configuration was that the difference in breakdown

voltage for AND and OR logic was too small (8 V) to switch

reproducibly. Alternately, when the biasing voltage was set

much lower than the breakdown voltage, the electric field was

insufficient to produce a breakdown but was strong enough to

drive the space-charge electrons and produce an appreciable

current (Fig. 4(b)). In this case since there was no plasma gen-

erated in the output device, the bias voltage was fixed and did

not have to be pulsed. Although there is a finite output voltage

with one of the inputs high, there is an appreciable margin to

differentiate between the two cases. A threshold voltage can

be defined to differentiate between the “0” and “1” states.

FIG. 2. The effect of nearby plasma measured as a function of distance from

EP0 (Fig. 1(a)) is shown in (a). The decay constant associated with different

plasma gases are shown in (b): L50-50 is the decay constant (or diffusion

length) of plasma generated in 50% He and 50% Ar while L100 is that of the

pure Ar or pure He. The plasma current directly determines the plasma den-

sity and proportionately increases the conductance of the nearby device as

shown in (c).

FIG. 3. The electrode configuration used to implement OR logic is shown in

(a) and is similar to the experiment shown in Fig. 1(c). The response of the

OR gate is shown in (b). The output is valid only when output bias is high.

The amplitude of output bias pulse is 195 V in this case.

FIG. 4. (a) shows the response of the AND gate. The logic is implemented

using the same configuration as in Fig. 2(a), but with the output biasing volt-

age set to 185 V. (b) shows response of the AND gate implemented using an

alternate approach. The biasing voltage is set to 150 V, which prevents

breakdown at output electrodes. But the electric field is sufficient to setup a

current using the space-charge.

244104-3 P. Pai and M. Tabib-Azar Appl. Phys. Lett. 104, 244104 (2014)

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Page 5: Plasma interconnects and circuits for logic gates and computer sub-circuits

The XOR gate was implemented with only 2 devices

(Fig. 5(a)). The output bias was set to 195 V. Plasma was

generated on the input electrode only when inputs A and B

were different. The device response is shown in Fig. 5(b).

The same electrode configuration can be used to obtain a

NOT gate response by connecting Input (B) to 300 V. The

device response is shown in Fig. 5(c).

Similar to the logic-gate implementation, a 1-bit half-ad-

der circuit was also realized. The number of lPD devices

and shared input signals required for operation was mini-

mized by optimum placement of lPD devices (Fig. 6(a)).

The operation of the device for the “Sum” bit is the same as

that of XOR. The “Carry” operation was realized by using a

resistor R1 (�100 KX) in series that allowed plasma genera-

tion at Carry electrode only when A and B were high as

shown in Fig. 6(d).

An advantage of implementing logic gates using

plasma-linked lPDs is in the reduction of number of active

switching elements. For example, AND and OR gate imple-

mented using CMOS require 4 transistors each while XOR

requires 8 transistors. Implementing these gates with plasma-

connected circuits requires only 2–3 lPDs. lPD devices

reported here were to show the feasibility of realizing func-

tional plasma gates and sub-circuit.

The above gates had a switching transition speed of

around 5 ls. It is possible to achieve 0.1 ns switching15 with

actively recombining plasmas at the expense of increased

power consumption.

This work was supported by DARPA MPD program

(Award No. N000141110932) under Dr. Daniel Purdy.

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(2014), pp. 171–174.10P. Pai and M. Tabib-Azar, Electron Dev. Lett. 35, 593–595 (2014).11P. Pai and M. Tabib-Azar, “Micro-plasma logic gates” (submitted).12J. Ryeom, Jpn. J. Appl. Phys., Part 2 44, L1122 (2005).13Y. P. Raizer, Gas Discharge Physics (Springer-Verlag, 1991).14R. Tirumala and D. B. Go, Appl. Phys. Lett. 97, 151502 (2010).15P. Pai and M. Tabib-Azar, “10 GHz Microplasma field effect transistors”

(submitted).

FIG. 5. Schematic of the electrode configuration for the XOR gate is shown

in (a). The input plasma turns ON only when A and B are different. The out-

put bias is set to 195 V similar to the OR gate. The device exhibits an XOR

logic as shown in (b). By connecting Input B to 300 V, the device responds

like a NOT gate (c).

FIG. 6. (a) Schematic representation of the electrode setup for 1-bit half-adder.

State of the Sum and Carry bits are represented by plasma on their correspond-

ing electrodes for the input states (A, B¼ 0), (A¼ 1, B¼ 0) and (A, B¼ 1) in

(b), (c) and (d), respectively.

244104-4 P. Pai and M. Tabib-Azar Appl. Phys. Lett. 104, 244104 (2014)

This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP: 130.39.62.90

On: Wed, 03 Sep 2014 10:32:54