Upload
gianna
View
38
Download
0
Tags:
Embed Size (px)
DESCRIPTION
Pixel Upgrade Status & Plans. CMS Engineering & Integration Meeting CERN, 2. March 2011 R. Horisberger, PSI. Present Pixel Detector with 3 hit coverage works very well !. 3 barrel layers & 2 F/B disks easy & quick removal / installation in shut down - PowerPoint PPT Presentation
Citation preview
Pixel UpgradeStatus & Plans
CMS Engineering &
Integration Meeting
CERN, 2. March 2011
R. Horisberger, PSI
Present Pixel Detector with 3 hit coverage works very well !
• 3 barrel layers & 2 F/B disks • easy & quick removal / installation in shut down• designed for luminosity < 1x1034 cm-2 sec-1
• design fluence < 0.6x1015n/cm2 (tolerate more)
Measured resolutionr = 13mz = 25m
Pixel Thresholdsmean = 2450 e
1
• BPIX 3 Layer 4 Layers • FPIX 2x2 Disk 3x2 Disk
Proposed Pixel Upgrade
• CO2 cooling based Ultra Light Mechanics
• Shift material budget out of tracking –region
Increase number pixel tracking points 3 4
Significant X/X0 reduction
pixel tracking & vertexing significant improved and robustified
• ROC modifications for operation up to L ~ 2x1034
• Use same cabling DC/DC converters for power 320MHz digital readout on fibres
• Minimize 1 Layer radius reduced impact xy & z error
2
Shift material budget out of tracking region
Current BPIX Services Upgraded BPIX Services
<2.2 : weight = 16.9 Kg (3 layer) <2.2 : weight = 6.5 Kg (4 layer)
shift out
~1.5 : -conversion for H from 22% to 11% for new 4 Layer Pixel System
Current 3 layerUpgraded 4 layer
Current 2 diskUpgraded 3 layer
Ra
dia
tio
n l
en
gth
Ra
dia
tio
n l
en
gth
3
BPIX / FPIX Envelope Definition & Insertion into CMS
CO2 cooling loopsstainless steel pipeswall thickness = 100diameter =1.8mm
Barrel Supply Tube
Insertion of new system verified
CF hinge
4
BPIX Upgrade Mechanics 1216 modules 81M pixel (1.6 x present BPIX)
If beam pipe r < 22.5 mm 1st Layer: 12 faces <R>=29.5mm 5
(present)
bas
elin
e• Full module type only
Layer 1: R 39mm; 16 faces
Layer 2: R 68mm; 28 faces
Layer 3: R 109mm; 44 faces
Layer 4: R 160mm; 64 faces
Clearance to beam pipe 4mm
current
upgrade
22.5
mm
24.7mm < 29.5mm >
Ultra Light Mechanics BPIX Prototype
100 bar pressure testedTubes, 50 wall thickness
Weight Layer1 42g + 7g CO2 30% of old first layer X/X0
Layer 1
Low mass CO2 cooling pipes
less multiple scattering in impact parameter resolution
Present Pixel Barrel
z-im
pac
t p
aram
. r
es.
[m
]
azimutal angle 6
FPIX Mechanics & Prototype
• inner & outer ring for easier replacement
• 6 disk of 112 sensors each 672 modules
• one module size with 2x8 ROC / module
10’752 ROC’s ~ 44M pixel (2.5 x old FPIX)
CO2 coolingloops
7
Impact Parameter of old / new Pixel System
Beam pipe r<23mm : 16 faces to 12 faces reduce MS term by ~0.75 total 0.75x0.6 = 0.45 !
0<<1.0
0<<1.0
tran
sver
se IP
lon
git
ud
inal
IP
tran
sver
se IP
lon
git
ud
inal
IP
Barrel Region
Barrel Region
Forward Region
Forward Region
0.6
current
upgraded
upgraded
current
8
~0.75
IP estimate for 12 face 1st Layer
Upgrade of Pixel Readout Chain
Data losses removed by ROC
changes:
1) increase depth of Status
- data buffer 32 80 done
- timestamps 12 24 done
2) add readout buffer done
3) 160Mbit/sec serial binary data out now
4) deal with PKAM events DAQ
resync
control interface block CIB
8005 um (52 pixel)
9935
um
80 p
ixel
DC
OL
1
DC
OL
2
DC
OL
3
DC
OL
26
12
tim
e
sta
mp
s3
2 d
ata
bu
ffe
rs
11
76m
300m
PSI46 ROCPresent ROC for 1st Layer:
Luminosity bx-spacing Data Loss
1x1034cm-2s-1 25nsec 4%50nsec 16%
2x1034cm-2s-1 25nsec 15%50nsec ~50%
50nsec operation of LHC was not planned in original ROC architecture in 1998.
125 µm
20 µm
Al core + Cu
Self Bonding EnamelPolyamide
IsolationPolyesterimide
CuAl core
3.125 ns
40m
V
-twisted CCA pair (Copper-Cladded Aluminum)
• 1m long low mass link at 320MHz , chips done !
9
Current / Upgraded Pixel Track Seeding at 2x1034cm-2s-1
upgraded
current
current
upgraded
current
upgraded
Red
uced
data lo
ss and
qu
adru
plet seed
ing
im
pro
ves efficiency an
d red
uces fake rate !
10
b-tagging of Current / Upgraded Pixel System
Current detector
Upgraded detector
~5x fake ratereduction
+25% efficiency gain
Lumiosity =
Efficient b-jet tagging crucial to many physics analysis
e.g. 4-b-jet channel fake rate reduction by factor ~600 or ~2.4 x signal gain
ttbar 80<pt<120 GeV Combined Seondary Vertex Tagger
11
Pixel Upgrade Schedule
13
2011 2012 2013 2014 2015 2016 2017 2018
7 TeV shut down LS1 14 TeV LS2LHC machine
present beampipe
new beampipe (45mm)
CMS open
Pixel (rep/ mod/ test/ inst)
new pixel instal. test
PP1 preparation
CO2 plant (pre) install.
CO2 – pixel load tests
Pixel (instal./comm./oper)
14 TeVTSTS 7 TeV 14 TeVTS TS 14 TeV
( ) ( ) ( )
Pixel tests @ PixTIF
( )
New LHC Schedule drives Pixel Schedule
The new LHC schedule after Chamonix 2011 constraints our possible time planning
New beam pipe for pixel upgrade
CMS Technical Coordination requested in Nov 2010 a CAD design study for a beam pipe diameter that still would be compatible in installation and required clearances with 12 face innermost barrel layer.
BPIX design study finished in Jan. 2011
Considered:
• cabling clearances• inner shield imperfections• beam displacements < 2 mm• minimal overlaps of sensor areas
Conclusion:
• mean 1st layer Si- radius = 29.8 mm• need 2 mm clearance to beam pipe• need adjustable closing mechanism• Beam pipe diameter (outer) = 45 mm !
Installation: Adjust & Close Tests in LS1
Current BPIX design has 7.5mm tolerance from inner shield to beam pipe. Observe ~3.2mm beam pipe displacement to nominal CMS tracker ! (z-dependent)
New upgrade pixel assumes courageous 2 mm tolerance gap to new beam pipe !
Only possible by adjustable BPIX pixel rail feet ! ( how about FPIX? )
Insertion past beam pipe support ring may require closing mechanism in final z-position !
Propose installation tests with duplicate of new upgrade pixel mechanics.
1) test tolerances2) test adjustment to beam pipe displacement3) test closing mechanism in situ
worm gear
BPIX & FPIX should both do these tests !
to be done ~ Mai 2014
CO2-Cooling / Power Pixel Load Tests
BPIX / FPIX service tubes with ohmic power loads and CO2- cooling loops
Ohmic power loads with CO2-cooling.
Propose to build dummy supply tubes with ohmic power loads and CO2 cooling loops with identical power cabling and final cooling loop connections as real detector for PP0.
PP0
Pixel power / cooling load cylinders are used to verify and commission CO2 cooling plant at the PixTIF and the cooling plant in CMS prior to the installation of the new pixel in CMS.
can be shortened
300 m
1176
m
32 d
ata
buff
ers
576
m
12 ti
me
stam
p bu
ffer
s25
2 m
control interface block CIB
8005 um (52 pixel)
9935
um
80 p
ixel
DC
OL
1
DC
OL
2
DC
OL
3
DC
OL
26
Development of digital PSI46 ROC
Reduce data losses by:
1) increase depth of- data buffer 32 80 - timestamps 12 24
2) add readout buffer3) 160Mbit/sec serial binary data out4) deal with PKAM events
Tests with LHC rate beams- rare errors with data- SEU errors
Next data losses term after 1) & 2) is dc-reset loss, removal possible by use of an extra marker bit (*)
modify data buffer logic !
Submission planned Sept. 2011
Submission possible in 2012 !
(*) based on an idea by H-C. Kaestli (2010)
Submission of digital PSI46 ROC
Submission of new digital PSI46dig (September 2011)
Submission with 4 chips / recticle
Qty Name Properties
1 PSI46 present analog readout ROC, as used now in FPIX / BPIX1 PSI46xdb analog readout ROC but with extended deeper data buffers1 PSI46dig digital ROC, extended data buffers & ROC readout buffers1 TBM etc TBM & faster ALT & various test chips
Submission of dc-reset loss corrected PSI46dig (possible 2012)
Submission with 4 chips / recticle
Qty Name Properties
3 PSI46dig digital ROC, extended data buffers & ROC readout buffers1 PSI46digx PSI46dig with dc-reset losses removed
Possible Recticle for September 2011 Submission
21200
HDI-driver chip
LCDS-driver chip
ALT chip
( Kapton cable drivers)
( Faster Analog Level Translator (ALT) chip for read out Opto Hybrid)
TBM chips
Old PSI46 ROC PSI46xdb- analog readout- extended db & ts buffers
PSI46dig- digital readout- extended db & ts buffers- readout buffers- pulse height ADC
mor
e te
st c
hips
redesigned
old TBM
old & PKAM clipping
digital TBM & PKAM clipping
FPIX Pilot Blades with PSI46dig ROC
FPIX mechanics, cooling & cabling was originally designed for 3 disks each side.
Present installed FPIX system has only 2 disks equipped.
All cables, fibres and cooling pipes for 3rd disk exist !
Proposal:
After repair of present FPIX during LS1 insert the 3rd disk mechanic and mount a few pilot blades of old design with new digital ROC (PSI46dig) and provide for these blades a few (already existing) readout fibres with old AOH, but new (faster) ALT chip.
Can operate and commission new digital ROC under realistic conditions (use CMS tracking as beam telescope) and write all the necessary software changes in DAQ, DB and DQM for a smooth and swift transition for the new upgraded pixel system in 2016/17
Available time slot for construction Jan. 2012-Feb. 2013 13 month !
1176
m
32 D
B57
6 m
12 T
S25
2 m
1532
m80
DB
896
m24
TS
288
m35
6 m
present ROC increased buffer sizecompact layout (done)
control interface block CIB
8005 um (52 pixel)
9935
um
80 p
ixel
DC
OL
1
DC
OL
2
DC
OL
3
DC
OL
26
PSI46xdb : analog ROC with extended data buffers
Present ROC with analog coded readout can be significantly improved for beyond LHC luminosity performance at very low radius layer by extended data & time stamp buffers
• PSI46xdb included in combined recticle in planned September 2011 submission.
• ROC becomes 356um larger may use in fresh BPIX 1st layer replacement in LS1 !
Replacement of 1st Layer of BPIX in SL1 ?
Replacement of 1st layer of BPIX with fresh silicon sensors and improved ROC chip with deeper data buffers could allow an efficient 1st BPIX layer operation for LHC running beyond standart luminosities.
Summer 2007, mounted modules of 1st pixel layer
This would cure the dominant dead time producing mechanism (data buffer overflow) and improve the 1st layer data loss (~5%) until installation of the new upgraded 4 layer pixel system with digital readout. For readout and software nothing changes.However, it will distract us from our main mission of a new 4 layer digital pixel system !
Use of PSI46xdb ROC that is logic design step along the path to produce PSI46dig.
Available production time slot Jan. 2012 – Feb. 2013 13 month
MU
X
core
ROC
ROC
ROC
ROC
ROC
ROC
160 MHz bus channel A
160 MHz bus channel B
320 MHz uplinkcoreToken A
Token B
TBM
Data digital pixel module / balanced coding
320 Mbit/s up link
Channel A (8 ROCs)160 Mbit/s Bus
LCDSRECV
160 MHz
320 MHz
LCDSDRV
Channel B (8 ROCs)160 Mbit/s Bus
160 MHz
320 MHz40 MHzPLL
1m micro twisted pair cable
Token A
Token B
A B! A B!
MUX
4
TBM A
4
TBM B
LCDSRECV
SER
SER
core
core
320 MHz read out signal is pseudo balanced by multiplexing by A with !B
good enough for ZARLINK ?
need encoding in TBM ? which? 4b/5b or 8b/10b
2011 2012 2013 2014 2015 2016 2017 2018
7 TeV shut down LS1 14 TeV LS2LHC machine
present beampipe
new beampipe (45mm)
CMS open
Pixel (rep/ mod/ test/ inst)
new pixel instal. test
PP1 preparation
CO2 plant (pre) install.
CO2 – pixel load tests
Pixel (instal./comm./oper)
New FPIX Pilot System for 2013
FPIX Pilot
constructon
14 TeVTSTS 7 TeV 14 TeVTS TS 14 TeV
( ) ( ) ( )
Pixel tests @ PixTIF
Pilot blades with PSI46dig for 3rd FPIX Disk: Jan 2012 – Feb. 2013 13 months ! !
( )
• Chamonix 2011 schedule for LHC has clear constraints for next years to come and the work that needs to be done in LS1.
• Schedule for LS2 not reliable known. Installation in extended TS (2016/17) conceivable.
• Should advance as many pixel installation jobs as possible to LS1. reduce personal irrad. dose; more time to react for problems; reduce task pile-up
• Beam pipe (outer) diameter of 45mm would allow 1st pixel layer radius <r>= 29.8mm
• Requires adjustabel feet to deal with clearance tolerances and disalignment of CMS
• ROC submission planned in Sept. 2011 with PSI46, PSI46xdb, PSI46dig & TBM’s plus extra chips like faster ALT, Gatekeeper etc.
• Propose to install in LS1 the FPIX system with partial equipped 3rd disks using a few pilot blades with the new digital ROC and digital readout chain. Allows concurrent running and commissioning of old & new system. Time slot for construction is very short. (~1 year)
• Common System & Integration (CSI) coordination is a very big task and linked to TC!
Summary & Conclusions
Spare Slides
CSI: Common Systems & Integration (1)
Pixel CSI Coordinator will have to organize and do many things:
• Beam-pipe planning, installation and taking care of all interface issues with the pixel detector (old & new) during Long Shutdown LS1 ~ 2013/14)
• Test installation during LS1 of pixel upgrade mechanics (adjustment & closing) with new beam pipe. Installation platforms, adjustment tools, inspection tools, clearance sensing & control to beam pipe in conjunction with the FPIX & BPIX groups
• Organization & Operations of Pixel Repair Lab at Point5 (dual use old / new pixel)
• Conceive, prepare, organize and get done with all required changes to services in PP1 / PP0 during LS1 that can be advanced from period in 2016/17. Stay operational with old system till installation of the upgrade pixel detector.
• CO2 Cooling plant: - basic conception, plant design & construction, - piping & sensors for open loop sensing or feed back
- control software and interlocks
• Pixel test facility at TIF (PixTIF): Conception, build up and operation of pixel test facility with correct length piping and CO2 cooling plant test pixel system
• Establishing & Coordination of DAQ / Power & Slow Control for complete system tests at PixTIF
• Shielding & radiation dose management of working people during LS1 & Installation feed back to project planning (dose spreading limits, show stopper ?)
• In situ power load & CO2 cooling tests with ohmic loads on installed service tube dummies and final PP0 LV-cabling & CO2-piping. Design & fabrication of dummy service tubes with ohmic loads for FPIX & BPIX.
• Take care and organize pixel common items:
- CAEN power supplies: firmware changes (2015), planning new units for 2018) - environmental control (humidity control during installation, etc. etc. ) - Optical link components, qualification & production of POH - Pixel FED: adaptation to serial protocol, board-production, etc.
• Installation of new upgrade pixel system in 2016 / 2017
• Prepare Software adaptation for switch over: old pixel new pixel in 2017
CSI: Common Systems & Integration (2)