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1 Pixel Area Detector Development at NSRRC Kuan-Li Yu, Te-Hui Lee, Hui-Fang Chuang, Hsin-Wei Chen, Chao-Chih Chiu, Duan-Jen Wang 2011/06/13

Pixel Area Detector Development at NSRRC

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Pixel Area Detector Development at NSRRC. Kuan-Li Yu, Te-Hui Lee, Hui-Fang Chuang, Hsin-Wei Chen, Chao-Chih Chiu, Duan-Jen Wang 2011/06/13. Outlines. Sensor ASIC: preamp, comparator, counter Bump bonding Readout system Timing control Interlock Data transfer and display. - PowerPoint PPT Presentation

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Page 1: Pixel Area Detector  Development at NSRRC

1

Pixel Area Detector Development at NSRRC

Kuan-Li Yu, Te-Hui Lee, Hui-Fang Chuang, Hsin-Wei Chen, Chao-Chih Chiu, Duan-Jen Wang

2011/06/13

Page 2: Pixel Area Detector  Development at NSRRC

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Outlines

• Sensor• ASIC: preamp, comparator, counter• Bump bonding• Readout system

– Timing control– Interlock– Data transfer and display

Page 3: Pixel Area Detector  Development at NSRRC

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Operation Principle

Page 4: Pixel Area Detector  Development at NSRRC

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Background Knowledge

• We started from scratch since 2009.• We learned sensor design from BNL.• We learned microstrip detector installation

and operation from D. Peter Siddons at BNL.

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General SpecificationDetector area 318.24 x 331.5 mm

Sensor pixels per area detector 81,320 x 40 = 3,252,800 (3 M pixels)

Module per area detector 8 x 5 = 40 modules

Frame rate 10 frame per second (fps)

Chips per module 2 x 4

Pixel size 170 x 170 um2

Energy range 6 ~ 30 keV

Counter in chip 16 or 20 bit (two operation mode)

Charge amplifier (CS AMP + shaper)

4 gains0.25 V/fC, 0.5 V/fC, 1 V/fC, 2V/fC

Intermodule gap between sensor to sensor area (Vertical)

3.4 mm, 20 pixelsSensor guard ring, wire bonding pads and mechanical structure

Intermodule gap between sensor to sensor area (Horizontal)

1.7 mm, 10 pixelsSensor guard ring and mechanical structure.

Page 6: Pixel Area Detector  Development at NSRRC

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Sensor

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Sensor Structure

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Sensor Wafer

6 inches

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Page 10: Pixel Area Detector  Development at NSRRC

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ASIC

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ASIC• ASIC is designed by outsourcing t-WIN Technology Servic

e Inc and manufactured by MXIC.– http://www.t-win.com.tw

• Analog Front End (AFE)– Preamp, shaper– High-pass filter– DAC, comparator

• Pseudo Random Counter (PRC)• Serial Peripheral Interface (SPI)

– Parameters settings– Counter values reading

Page 12: Pixel Area Detector  Development at NSRRC

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Requirements of Analog Front End• CS amplifier and shaper• Input: 50 nA/10 ns = 0.5 fC (10 keV photons)• Output: amplification 2 V/fC• Power consumption = 24 uW

– Operation current = 8 uA@3 V• Time response < 1 us• Implementation area 4,000 um2

• Radiation hardened• Low Equivalent Noise Charge (ENC)

Page 13: Pixel Area Detector  Development at NSRRC

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Input current pulse

Output signal

Page 14: Pixel Area Detector  Development at NSRRC

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AFE Test IC

2.8 mm

2.8 mm

Preamp + shaper

One pixel

Preamp + shaper + comparator

Page 15: Pixel Area Detector  Development at NSRRC

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Pixel CircuitAnalog Front End (AFE)

Pseudo Random Counter (PRC)

Serial Peripheral Interface (SPI)

Page 16: Pixel Area Detector  Development at NSRRC

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Analog Front End (AFE)preamp shaper

Threshold DAC

comparator

Amplification selection

Page 17: Pixel Area Detector  Development at NSRRC

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Pseudo Random Counter (PRC)

Overflow detection

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Pseudo Random Counter (PRC)0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

1Counting mode

Comparator output

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

1Reading mode

DCLK

20-bit counting mode

20-bit reading mode

Used=1,048,575,CLKNUM=1,048,576, 99.999905%, Last=0X7FFFF, First=0XFFFFFFFFFF(0),FFFFE(1),FFFFC(2),FFFF8(3),FFFF1(4),FFFE3(5),FFFC7(6),FFF8E(7),FFF1C(8),FFE38(9),FFC71(10),FF8E3(11),FF1C7(12),FE38E(13),FC71C(14),F8E38(15),F1C71(16),E38E3(17), …., 7FFFF

Page 19: Pixel Area Detector  Development at NSRRC

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Pixel Layout

AFE

PRC

SPI

170 um170 um

Page 20: Pixel Area Detector  Development at NSRRC

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Power Consumption Estimation• AFE :

– CSA(9)+SHP(9)+CMP(7.5)+BIAS(4.5)+DAC(4.5) = 35 uA • SPI :

– 60 uA when clock running• PRC :

– 30 uA when clock running• Total working current/pixel: 40 uA ~ 50 uA• Power Consumption

– 45 x 106 x 94 x 8 = 3.587 A– 3.587 A x 3 V = 10.76 W– 10.76 W/(66 mm x 38.3 mm) = 0.42 W/cm2

Page 21: Pixel Area Detector  Development at NSRRC

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Power Management in One Pixel

• Counting mode– AFE ON, PRC ON, SPI OFF

• Reading mode– AFE OFF, PRC ON, SPI ON

• Standby mode– AFE OFF, PRC OFF, SPI OFF

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Bump Bonding Process

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Bump Bonding Platform

load cell

prism

microscope

Vacuum chuck

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Motor controller

Control computer

Page 25: Pixel Area Detector  Development at NSRRC

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Readout System

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Readout System

SCB(sensor on

8 ASICs)serial MCB

8 x 20 Mb/s = 160 MbpsDAQ

Computer

NI PCIe 6537

MCB

MCB

MCB

SCB(sensor on

8 ASICs)serial

SCB(sensor on

8 ASICs)serial

SCB(sensor on

8 ASICs)serial

Master TCB

Power Supply

Control Comupter

Para

llel b

us

Ethernet switch Ethernet switch

Intr

anet

Optical fiber

Inside hutch, #1

Outside hutch

Power control, signal synchronization,

HV bias control, system reset,

interlock

Intr

anet

DAQ Computer

SlaveTCB

MCB: Memory Control Board

TCB: Timing Control Board

DAQ: Data Acquisition Computer

Unit #2 ~ #10

SCB: Serial Control Board

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Serial Control Board (SCB)

MCB

Sensor

ASIC

Serial Control Board (SCB)IC

PCB via

Wire bondFor signal and VCC

1 mm

Mechanical support

CN_SCB_S

CN_SCB_T

CN_MCB_T

Bump bonding for guard ringWire bondFor HV bias

Al

ASIC peripheral logic and power supply circuit

ASIC pixel circuit

Indium

Page 28: Pixel Area Detector  Development at NSRRC

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Memory Control Board (MCB)

Serial engineASIC #0

Serial engineASIC #1

Serial engineASIC #2

Serial engineASIC #3

Serial engineASIC #4

Serial engineASIC #5

Serial engineASIC #6

Serial engineASIC #7

Module, SCB

SRAM #1PRC lookup

tableDatabus_ram1

Databus out

FPGA

SRAM #0

FIFO

Databus, handshake signal

Ribbon cableDAQ

NI PCIe 6537

Databus in

Databus_ram0

Address

MCB

Page 29: Pixel Area Detector  Development at NSRRC

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Timing Control Board (TCB)• Power supply to MCB and SCB• Data transfer timing and exposure time contro

l• Synchronization of all modules• Interlock signal monitoring

– Cooling water flow and temperature– HV bias leakage current– SCBs temperature monitoring

• HV bias voltage supply and control

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Image Data Transfer

• High pulsatile data rate is converted to sustained slower data rate by FIFO memory

time

Data rate

SCBSerial to parallel

conversionFIFO DAQ

160 Mbps

Exposure time

PRC decode

320 MbpsData transfer

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SCB to MCB Write data to FIFO

20-bit PRC decode

MCB Timing Control

1 usec

Page 32: Pixel Area Detector  Development at NSRRC

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Data Transfer Speed• Serial to parallel conversion speed

– 20 MHz x 8 =160 Mbps• PRC decoding speed

– 16-bit PRC = 16 bit/125 ns = 128 Mbps– 20-bit PRC = 20 bit/200 ns = 100 Mbps

• National Instruments (NI) PCIe 6537 parallel interface– 16 bit x 50 MHz/4 MCB = 200 Mbps

• Estimated data transfer time for one module– 203,300 / 20,000,000 * 1.5 15.2 ms (20-bit)≒– 162,640 / 20,000,000 * 1.5 12.2 ms (16-bit)≒

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Start count

Image

Combine and DisplaySAMBA

Report received images

Image Viewer (FITS)http://fits.gsfc.nasa.gov/

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Develop a device support for areaDetector module

Write a driver inherits from ADDriver

tpsDetector

Page 35: Pixel Area Detector  Development at NSRRC

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Schedule

• July 2011: AFE Test IC• Dec. 2011: Single operational module• Aug. 2012: Integrated 40 modules• Dec. 2012: Integrated with EPICS control

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Thank you for your attention.

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Serial Control Board (SCB)

• Mechanical support for ASIC and sensor• Wire bonding with ASIC• Thermal conduction for ASIC heat dissipation

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Memory Control Board (MCB)

• SCB ASIC parameter settings• Serial to parallel signal conversion engine• FIFO data flow control• Pseudo Random Counter (PRC)

– Lookup table generation– Hardware decode (20-bit, 200 ns)

• SCB and ASIC temperature monitoring